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([178.197.222.113]) by smtp.gmail.com with ESMTPSA id s18-20020adfeb12000000b0031779a6b451sm12861246wrn.83.2023.08.08.01.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 01:27:57 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 08/11] clk: samsung: exynos7885: do not define number of clocks in bindings Date: Tue, 8 Aug 2023 10:27:35 +0200 Message-Id: <20230808082738.122804-9-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> References: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore this number of clocks should not be in the bindings, because otherwise we should not change it. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynos7885.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk= -exynos7885.c index 0c6a84764f7a..f7d7427a558b 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -16,6 +16,12 @@ #include "clk.h" #include "clk-exynos-arm64.h" =20 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1) +#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1) +#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) +#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1) + /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_TOP (0x12060000) */ @@ -333,7 +339,7 @@ static const struct samsung_cmu_info top_cmu_info __ini= tconst =3D { .nr_div_clks =3D ARRAY_SIZE(top_div_clks), .gate_clks =3D top_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(top_gate_clks), - .nr_clk_ids =3D TOP_NR_CLK, + .nr_clk_ids =3D CLKS_NR_TOP, .clk_regs =3D top_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(top_clk_regs), }; @@ -552,7 +558,7 @@ static const struct samsung_cmu_info peri_cmu_info __in= itconst =3D { .nr_mux_clks =3D ARRAY_SIZE(peri_mux_clks), .gate_clks =3D peri_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(peri_gate_clks), - .nr_clk_ids =3D PERI_NR_CLK, + .nr_clk_ids =3D CLKS_NR_PERI, .clk_regs =3D peri_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peri_clk_regs), .clk_name =3D "dout_peri_bus", @@ -661,7 +667,7 @@ static const struct samsung_cmu_info core_cmu_info __in= itconst =3D { .nr_div_clks =3D ARRAY_SIZE(core_div_clks), .gate_clks =3D core_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(core_gate_clks), - .nr_clk_ids =3D CORE_NR_CLK, + .nr_clk_ids =3D CLKS_NR_CORE, .clk_regs =3D core_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(core_clk_regs), .clk_name =3D "dout_core_bus", @@ -743,7 +749,7 @@ static const struct samsung_cmu_info fsys_cmu_info __in= itconst =3D { .nr_mux_clks =3D ARRAY_SIZE(fsys_mux_clks), .gate_clks =3D fsys_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(fsys_gate_clks), - .nr_clk_ids =3D FSYS_NR_CLK, + .nr_clk_ids =3D CLKS_NR_FSYS, .clk_regs =3D fsys_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(fsys_clk_regs), .clk_name =3D "dout_fsys_bus", --=20 2.34.1