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([178.197.222.113]) by smtp.gmail.com with ESMTPSA id s18-20020adfeb12000000b0031779a6b451sm12861246wrn.83.2023.08.08.01.27.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 01:27:47 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 03/11] clk: samsung: exynos5250: do not define number of clocks in bindings Date: Tue, 8 Aug 2023 10:27:30 +0200 Message-Id: <20230808082738.122804-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> References: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore this number of clocks should not be in the bindings, because otherwise we should not change it. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynos5250.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk= -exynos5250.c index 92fb09922f28..8ebe6155d8b7 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -100,6 +100,9 @@ #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) =20 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR (CLK_MOUT_VPLLSRC + 1) + /* list of PLLs to be registered */ enum exynos5250_plls { apll, mpll, cpll, epll, vpll, gpll, bpll, @@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_no= de *np) panic("%s: unable to determine soc\n", __func__); } =20 - ctx =3D samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); + ctx =3D samsung_clk_init(NULL, reg_base, CLKS_NR); hws =3D ctx->clk_data.hws; =20 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, --=20 2.34.1