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([178.197.222.113]) by smtp.gmail.com with ESMTPSA id s18-20020adfeb12000000b0031779a6b451sm12861246wrn.83.2023.08.08.01.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 01:27:44 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 01/11] clk: samsung: exynos3250: do not define number of clocks in bindings Date: Tue, 8 Aug 2023 10:27:28 +0200 Message-Id: <20230808082738.122804-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> References: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore this number of clocks should not be in the bindings, because otherwise we should not change it. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynos3250.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk= -exynos3250.c index 6cc65ccf867c..a02461667664 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -100,6 +100,11 @@ #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) =20 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1) +#define CLKS_NR_DMC (CLK_DIV_DMCD + 1) +#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1) + static const unsigned long exynos3250_cmu_clk_regs[] __initconst =3D { SRC_LEFTBUS, DIV_LEFTBUS, @@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initcon= st =3D { .nr_fixed_factor_clks =3D ARRAY_SIZE(fixed_factor_clks), .cpu_clks =3D exynos3250_cpu_clks, .nr_cpu_clks =3D ARRAY_SIZE(exynos3250_cpu_clks), - .nr_clk_ids =3D CLK_NR_CLKS, + .nr_clk_ids =3D CLKS_NR_MAIN, .clk_regs =3D exynos3250_cmu_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(exynos3250_cmu_clk_regs), }; @@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __ini= tconst =3D { .nr_mux_clks =3D ARRAY_SIZE(dmc_mux_clks), .div_clks =3D dmc_div_clks, .nr_div_clks =3D ARRAY_SIZE(dmc_div_clks), - .nr_clk_ids =3D NR_CLKS_DMC, + .nr_clk_ids =3D CLKS_NR_DMC, .clk_regs =3D exynos3250_cmu_dmc_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs), }; @@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __i= nitconst =3D { .nr_div_clks =3D ARRAY_SIZE(isp_div_clks), .gate_clks =3D isp_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(isp_gate_clks), - .nr_clk_ids =3D NR_CLKS_ISP, + .nr_clk_ids =3D CLKS_NR_ISP, }; =20 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) --=20 2.34.1