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Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Simon Horman , Joao Pinto Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xfr@outlook.com, rock.xu@nio.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next] net: stmmac: xgmac: RX queue routing configuration Date: Tue, 8 Aug 2023 00:09:55 +0800 Message-Id: <20230807160955.1111104-1-0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit abe80fdc6ee6 ("net: stmmac: RX queue routing configuration") introduced RX queue routing to DWMAC4 core. This patch extend the support to XGMAC2 core. Signed-off-by: Furong Xu <0x1207@gmail.com> --- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 14 +++++++ .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 37 ++++++++++++++++++- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 1913385df685..a2498da7406b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -74,8 +74,22 @@ #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2) #define XGMAC_RXQEN_SHIFT(x) ((x) * 2) #define XGMAC_RXQ_CTRL1 0x000000a4 +#define XGMAC_AVCPQ GENMASK(31, 28) +#define XGMAC_AVCPQ_SHIFT 28 +#define XGMAC_PTPQ GENMASK(27, 24) +#define XGMAC_PTPQ_SHIFT 24 +#define XGMAC_TACPQE BIT(23) +#define XGMAC_TACPQE_SHIFT 23 +#define XGMAC_DCBCPQ GENMASK(19, 16) +#define XGMAC_DCBCPQ_SHIFT 16 +#define XGMAC_MCBCQEN BIT(15) +#define XGMAC_MCBCQEN_SHIFT 15 +#define XGMAC_MCBCQ GENMASK(11, 8) +#define XGMAC_MCBCQ_SHIFT 8 #define XGMAC_RQ GENMASK(7, 4) #define XGMAC_RQ_SHIFT 4 +#define XGMAC_UPQ GENMASK(3, 0) +#define XGMAC_UPQ_SHIFT 0 #define XGMAC_RXQ_CTRL2 0x000000a8 #define XGMAC_RXQ_CTRL3 0x000000ac #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index a0c2ef8bb0ac..097b891a608d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -127,6 +127,39 @@ static void dwxgmac2_tx_queue_prio(struct mac_device_i= nfo *hw, u32 prio, writel(value, ioaddr + reg); } =20 +static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw, + u8 packet, u32 queue) +{ + void __iomem *ioaddr =3D hw->pcsr; + u32 value; + + static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] =3D { + { XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT }, + { XGMAC_PTPQ, XGMAC_PTPQ_SHIFT }, + { XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT }, + { XGMAC_UPQ, XGMAC_UPQ_SHIFT }, + { XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT }, + }; + + value =3D readl(ioaddr + XGMAC_RXQ_CTRL1); + + /* routing configuration */ + value &=3D ~dwxgmac2_route_possibilities[packet - 1].reg_mask; + value |=3D (queue << dwxgmac2_route_possibilities[packet - 1].reg_shift) & + dwxgmac2_route_possibilities[packet - 1].reg_mask; + + /* some packets require extra ops */ + if (packet =3D=3D PACKET_AVCPQ) { + value &=3D ~XGMAC_TACPQE; + value |=3D 0x1 << XGMAC_TACPQE_SHIFT; + } else if (packet =3D=3D PACKET_MCBCQ) { + value &=3D ~XGMAC_MCBCQEN; + value |=3D 0x1 << XGMAC_MCBCQEN_SHIFT; + } + + writel(value, ioaddr + XGMAC_RXQ_CTRL1); +} + static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw, u32 rx_alg) { @@ -1463,7 +1496,7 @@ const struct stmmac_ops dwxgmac210_ops =3D { .rx_queue_enable =3D dwxgmac2_rx_queue_enable, .rx_queue_prio =3D dwxgmac2_rx_queue_prio, .tx_queue_prio =3D dwxgmac2_tx_queue_prio, - .rx_queue_routing =3D NULL, + .rx_queue_routing =3D dwxgmac2_rx_queue_routing, .prog_mtl_rx_algorithms =3D dwxgmac2_prog_mtl_rx_algorithms, .prog_mtl_tx_algorithms =3D dwxgmac2_prog_mtl_tx_algorithms, .set_mtl_tx_queue_weight =3D dwxgmac2_set_mtl_tx_queue_weight, @@ -1524,7 +1557,7 @@ const struct stmmac_ops dwxlgmac2_ops =3D { .rx_queue_enable =3D dwxlgmac2_rx_queue_enable, .rx_queue_prio =3D dwxgmac2_rx_queue_prio, .tx_queue_prio =3D dwxgmac2_tx_queue_prio, - .rx_queue_routing =3D NULL, + .rx_queue_routing =3D dwxgmac2_rx_queue_routing, .prog_mtl_rx_algorithms =3D dwxgmac2_prog_mtl_rx_algorithms, .prog_mtl_tx_algorithms =3D dwxgmac2_prog_mtl_tx_algorithms, .set_mtl_tx_queue_weight =3D dwxgmac2_set_mtl_tx_queue_weight, --=20 2.34.1