From nobody Tue Dec 16 21:02:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A742C001DB for ; Mon, 7 Aug 2023 13:52:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234482AbjHGNwl (ORCPT ); Mon, 7 Aug 2023 09:52:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234467AbjHGNwh (ORCPT ); Mon, 7 Aug 2023 09:52:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D04E9E79 for ; Mon, 7 Aug 2023 06:52:36 -0700 (PDT) Message-ID: <20230807135026.471131104@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZB2Tk1eymt/PbXMe0IaE8sjzy2MyrXEyff6m5gvO+II=; b=VIgCRyLDM+TeTTjYWM7f7ZMNKjZaw7AKGeuhsqFUBNEvcfXO95cO8ih3k0HSdj/cJ+ovMp 7r3acC7grHSUIXryGZBQcmDLkNZVOi8om+PVcvjJZ8YGRCLWmVCfy5a39C5gY9K42ChBh9 4MIgh5SaNtZ6D8g/mfUJucIURiNGBijKJMBgdYnYNGsuMnx1O5HGFLVKFD05ihgSiRHDHr qfqAkzFmK3hVssjabfiuI6Hojn2TqxJ0FOyEMtPqSgflkik9ZXDyb9NwPqHLF96nH2rcjW BozJALw8NUSMDVDxGzhdjNowcC17PrcqZE/FRNfwtsU4iwrVKyKnUatVTrqQdg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZB2Tk1eymt/PbXMe0IaE8sjzy2MyrXEyff6m5gvO+II=; b=rEJdZnL380eOyNl4DeECbImyvDu62+fawzelWR3CXsCH7BhRa06BNE0t54zNI9Wy12SSTT srNI5MYAtz9G7ZCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 01/53] x86/cpu/topology: Cure off by one in fake_topology() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:34 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The shift count for a single core CPU is obviously 0 and not 1. Not that it matters much, but keep it correct. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -75,7 +75,7 @@ static bool fake_topology(struct topo_sc * which has useless CPUID information. */ topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); - topology_set_dom(tscan, TOPO_CORE_DOMAIN, 1, 1); + topology_set_dom(tscan, TOPO_CORE_DOMAIN, 0, 1); =20 return tscan->c->cpuid_level < 1 || xen_pv_domain(); } From nobody Tue Dec 16 21:02:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 125D6C001DB for ; Mon, 7 Aug 2023 13:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234499AbjHGNwp (ORCPT ); Mon, 7 Aug 2023 09:52:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234474AbjHGNwj (ORCPT ); Mon, 7 Aug 2023 09:52:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C51092 for ; Mon, 7 Aug 2023 06:52:38 -0700 (PDT) Message-ID: <20230807135026.528433010@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416356; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WJi6X1yIC43zDH6zaMpRD9ZckoH8t1jG0FLDTsc9drE=; b=vo8ZSYrGigDW+lveybRcUyoE0yAeso3KJgDMtkzOSoevZeD5daxgFasvS4bc6pCVEqppTr VteiTr5e90OtQrLsi7jNkfxlmZDyBNXISJFX7RBpB2r5mhMYoYppkaPkNzaUeJPO2Clb6A E/VEXGrCELg2Ml6T/A20LUvB3cTV3RY+cpm4/28ewHz0D3GZFk7pagLSTq3qPRhmu1pEtA I9RgA6vM2ykefyTF9enJ6VPnbXlNwnunhfxTZ3j3SMjrHCOPr58gIxKd5gNmLUuh14LAfi UDi3FRmtYSksJBHdm4BNuNN+NJckBX/yiuPfP22/PxKs5ihH8zSPBNAVWMh5LQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416356; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WJi6X1yIC43zDH6zaMpRD9ZckoH8t1jG0FLDTsc9drE=; b=WiPf0GwyvOudYS7HOskUAYOK5noAXwaKrsCmKYnyR9v5PzbkCyCsNziXLWouPJiLHSPYiG gUwxUfmw3Pe9DnBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 02/53] x86/cpu/topology: Make the APIC mismatch warnings complete References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:36 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Detect all possible combinations of mismatch right in the CPUID evaluation code. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/common.c | 15 ++------------- arch/x86/kernel/cpu/topology_common.c | 10 ++++++++++ 2 files changed, 12 insertions(+), 13 deletions(-) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1676,22 +1676,11 @@ static void generic_identify(struct cpui #endif } =20 -/* - * Validate that ACPI/mptables have the same information about the - * effective APIC id and update the package map. - */ -static void validate_apic_and_package_id(struct cpuinfo_x86 *c) +static void update_package_map(struct cpuinfo_x86 *c) { #ifdef CONFIG_SMP unsigned int cpu =3D smp_processor_id(); - u32 apicid; =20 - apicid =3D apic->cpu_present_to_apicid(cpu); - - if (apicid !=3D c->topo.apicid) { - pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", - cpu, apicid, c->topo.initial_apicid); - } BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); #else @@ -1876,7 +1865,7 @@ void identify_secondary_cpu(struct cpuin #ifdef CONFIG_X86_32 enable_sep_cpu(); #endif - validate_apic_and_package_id(c); + update_package_map(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); =20 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -176,6 +176,16 @@ void cpu_parse_topology(struct cpuinfo_x =20 parse_topology(&tscan, false); =20 + if (c->topo.initial_apicid !=3D c->topo.apicid) { + pr_err(FW_BUG "CPU%4u: APIC ID mismatch. CPUID: 0x%04x APIC: 0x%04x\n", + cpu, c->topo.initial_apicid, c->topo.apicid); + } + + if (c->topo.apicid !=3D cpuid_to_apicid[cpu]) { + pr_err(FW_BUG "CPU%4u: APIC ID mismatch. Firmware: 0x%04x APIC: 0x%04x\n= ", + cpu, cpuid_to_apicid[cpu], c->topo.apicid); + } + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) { if (tscan.dom_shifts[dom] =3D=3D x86_topo_system.dom_shifts[dom]) continue; From nobody Tue Dec 16 21:02:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 171E9C04A6A for ; Mon, 7 Aug 2023 13:52:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234505AbjHGNws (ORCPT ); Mon, 7 Aug 2023 09:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234479AbjHGNwk (ORCPT ); Mon, 7 Aug 2023 09:52:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D65C892 for ; Mon, 7 Aug 2023 06:52:39 -0700 (PDT) Message-ID: <20230807135026.583926152@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=d94K6TZuk9UQVnHU8hugmyHyNVbrMnQ9c00omcsE0/8=; b=XiJre2F21rkX+aipwOorw1II23Kx9Q/Ep5ull5Wq2PER54URIRU/SxCqdDgTa7Fz2y/HJh xeCTqjiW8rZpstGn8RzhpUpB4EF1zTifBCJY3S0JyyetIfe0MVCh6v/g36qwmlP6lfu4Z2 PpNT9EtIPeFpKD+Ailz8K65+J6Yb7gTgcPu9JW1x18pEnHFeBQhx0BkmNHB1w6NUdGSJpi gnoGYXXiG2JzbgeuJVt8ihQeciirYjtM4+C0cmwivSmjDiDNS4MNtHhtQvoO5+X8jGlJoI yQn/hC0yD5vHA8mmW0HKhlLwIwu4O6j9kDxzyJ6uz8f1goMG5YEqQjy2s+mM0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=d94K6TZuk9UQVnHU8hugmyHyNVbrMnQ9c00omcsE0/8=; b=BtHqpGBLjlz56f4CRT9zVPQI+4sj0XHUiDA2V/EzODvrqkSqRK3YFjvAI9OxJeW4A7xg2/ Ndk3bg2kbYRRGTAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 03/53] x86/platform/ce4100: Dont override x86_init.mpparse.setup_ioapic_ids References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:38 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no point to do that. The ATOMs have an XAPIC for which this function is a pointless exercise. Signed-off-by: Thomas Gleixner Cc: Andy Shevchenko Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/io_apic.h | 1 - arch/x86/kernel/apic/io_apic.c | 2 +- arch/x86/platform/ce4100/ce4100.c | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -140,7 +140,6 @@ extern void mask_ioapic_entries(void); extern int restore_ioapic_entries(void); =20 extern void setup_ioapic_ids_from_mpc(void); -extern void setup_ioapic_ids_from_mpc_nocheck(void); =20 extern int mp_find_ioapic(u32 gsi); extern int mp_find_ioapic_pin(int ioapic, u32 gsi); --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1458,7 +1458,7 @@ void restore_boot_irq_mode(void) * * by Matt Domsch Tue Dec 21 12:25:05 CST 1999 */ -void __init setup_ioapic_ids_from_mpc_nocheck(void) +static void __init setup_ioapic_ids_from_mpc_nocheck(void) { union IO_APIC_reg_00 reg_00; physid_mask_t phys_id_present_map; --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -139,7 +139,6 @@ void __init x86_ce4100_early_setup(void) x86_init.resources.probe_roms =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; x86_init.mpparse.find_smp_config =3D x86_init_noop; - x86_init.mpparse.setup_ioapic_ids =3D setup_ioapic_ids_from_mpc_nocheck; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48CFAC001DB for ; Mon, 7 Aug 2023 13:53:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234508AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234498AbjHGNwp (ORCPT ); Mon, 7 Aug 2023 09:52:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C72510D5 for ; Mon, 7 Aug 2023 06:52:41 -0700 (PDT) Message-ID: <20230807135026.636507272@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yzPalGwgNV+hv5fraMZh8WMCr4ypmAb2ZvNhqZKp6/4=; b=TCV6O+CG00GeXn+a1he4JPWxkG57mzG3b1yu3o/ohWynYnglIUDivLSqz9WmUsMXKUHMrB CWt2yeHBl3HF+uMq0c60c0aI4T7offUADhMCkvapN2UfTyihOfnn7yAEJJVU3xFTBL3jae rhp/mB5x65k9DIj8DfGmEd2PdDnUAZocOlRUpNtiwc2rxTWse00G2ZVdk5f27rPwDAI7lK A+fxMR1kRotwQpAUBmlQ6tyve4uJ9W8gJ336+3dJZ/YsLxYoknlotL6apqLyszTRx/A5JV kDBIx3o0NoBa5AO7kYMPyLMaOQU8LPQVzaHSsD7sDpCV7hR6pcvfZ5P0ZJHv+Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yzPalGwgNV+hv5fraMZh8WMCr4ypmAb2ZvNhqZKp6/4=; b=latYlXwaRgAi9FG6M3RL/5Pcp7XFqm5yOyA+yuH/0icD1crJzcUieocZ7hOuQprjxkMS2m CFFI7U91d3ycnSCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 04/53] x86/ioapic: Replace some more set bit nonsense References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:39 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Yet another set_bit() operation wrapped in oring a mask. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 3 --- arch/x86/kernel/apic/io_apic.c | 6 ++---- 2 files changed, 2 insertions(+), 7 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -86,9 +86,6 @@ typedef struct physid_mask physid_mask_t #define physid_set(physid, map) set_bit(physid, (map).mask) #define physid_isset(physid, map) test_bit(physid, (map).mask) =20 -#define physids_or(dst, src1, src2) \ - bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) - #define physids_clear(map) \ bitmap_zero((map).mask, MAX_LOCAL_APIC) =20 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2494,9 +2494,8 @@ unsigned int arch_dynirq_lower_bound(uns #ifdef CONFIG_X86_32 static int io_apic_get_unique_id(int ioapic, int apic_id) { - union IO_APIC_reg_00 reg_00; static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; - physid_mask_t tmp; + union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; =20 @@ -2542,8 +2541,7 @@ static int io_apic_get_unique_id(int ioa apic_id =3D i; } =20 - physid_set_mask_of_physid(apic_id, &tmp); - physids_or(apic_id_map, apic_id_map, tmp); + physid_set(apic_id, apic_id_map); =20 if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6EC5C001DB for ; Mon, 7 Aug 2023 13:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234478AbjHGNw5 (ORCPT ); Mon, 7 Aug 2023 09:52:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234497AbjHGNwp (ORCPT ); Mon, 7 Aug 2023 09:52:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CCA810DB for ; Mon, 7 Aug 2023 06:52:43 -0700 (PDT) Message-ID: <20230807135026.698506626@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WM7FtIAfN5V1o55rfOkqm3mZ5QhFQKaaoxABZtsnb3I=; b=yXwPOKLUDuGuTlV2kSMmQ2PSPmAkEdEJeXjPnSP54gdUnf8gf92OSI8qrH8oHPPX37gHF5 UfuV5Pdvf8OjHzYb49KBwHfLjexvlRcW+CaY4Wr0My3R2U+dkfhCv5dbIKIgDeWVWPP9nC Lmof4C1aFxxWsIoYPGFl59mlt40sRnqwpog0JxbXcS6qsdNk40MiJaMzzBhK36o3bNJw0p 6Z63JOimBkbsgwoJFhE5ZpAFPIiEc5XTaOjpgZZWcIE1Y1Lj3CyGSx+zufzQ7pCV/2dqII YyqTCi0HyoGDLUmrPhADen3L5npmc83uvu106Ymx7/mavx+HDn7Ifa6XBlueDA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WM7FtIAfN5V1o55rfOkqm3mZ5QhFQKaaoxABZtsnb3I=; b=+gLJP5wwGYhZA8HpB1gp7h5TTQeZmw0R6Z7d+2Jyx1LxCeqlC38ThUHRUR/UhSeR9NRj9a 9QybTMsH4ocZPADA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 05/53] x86/apic: Get rid of get_physical_broadcast() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:41 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no point for this function. The only case where this is used when there is no XAPIC available, which means the broadcast address is 0xF. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/apic/apic.c | 10 --------- arch/x86/kernel/apic/io_apic.c | 42 ++++++++++++++++++------------------= ----- 2 files changed, 19 insertions(+), 33 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -259,16 +259,6 @@ u64 native_apic_icr_read(void) return icr1 | ((u64)icr2 << 32); } =20 -#ifdef CONFIG_X86_32 -/** - * get_physical_broadcast - Get number of physical broadcast IDs - */ -int get_physical_broadcast(void) -{ - return modern_apic() ? 0xff : 0xf; -} -#endif - /** * lapic_get_maxlvt - get the maximum number of local vector table entries */ --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1460,12 +1460,12 @@ void restore_boot_irq_mode(void) */ static void __init setup_ioapic_ids_from_mpc_nocheck(void) { - union IO_APIC_reg_00 reg_00; physid_mask_t phys_id_present_map; - int ioapic_idx; - int i; + const u32 broadcast_id =3D 0xF; + union IO_APIC_reg_00 reg_00; unsigned char old_id; unsigned long flags; + int ioapic_idx, i; =20 /* * This is broken; anything with a real cpu count has to @@ -1484,11 +1484,10 @@ static void __init setup_ioapic_ids_from =20 old_id =3D mpc_ioapic_id(ioapic_idx); =20 - if (mpc_ioapic_id(ioapic_idx) >=3D get_physical_broadcast()) { - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", - ioapic_idx, mpc_ioapic_id(ioapic_idx)); - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", - reg_00.bits.ID); + if (mpc_ioapic_id(ioapic_idx) >=3D broadcast_id) { + pr_err("BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", + ioapic_idx, mpc_ioapic_id(ioapic_idx)); + pr_err("... fixing up to %d. (tell your hw vendor)\n", reg_00.bits.ID); ioapics[ioapic_idx].mp_config.apicid =3D reg_00.bits.ID; } =20 @@ -1499,15 +1498,14 @@ static void __init setup_ioapic_ids_from */ if (apic->check_apicid_used(&phys_id_present_map, mpc_ioapic_id(ioapic_idx))) { - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", + pr_err("BIOS bug, IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); - for (i =3D 0; i < get_physical_broadcast(); i++) + for (i =3D 0; i < broadcast_id; i++) if (!physid_isset(i, phys_id_present_map)) break; - if (i >=3D get_physical_broadcast()) + if (i >=3D broadcast_id) panic("Max APIC ID exceeded!\n"); - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", - i); + pr_err("... fixing up to %d. (tell your hw vendor)\n", i); physid_set(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { @@ -2495,6 +2493,7 @@ unsigned int arch_dynirq_lower_bound(uns static int io_apic_get_unique_id(int ioapic, int apic_id) { static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; + const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; @@ -2515,9 +2514,9 @@ static int io_apic_get_unique_id(int ioa reg_00.raw =3D io_apic_read(ioapic, 0); raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 - if (apic_id >=3D get_physical_broadcast()) { - printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " - "%d\n", ioapic, apic_id, reg_00.bits.ID); + if (apic_id >=3D broadcast_id) { + pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n", + ioapic, apic_id, reg_00.bits.ID); apic_id =3D reg_00.bits.ID; } =20 @@ -2527,17 +2526,15 @@ static int io_apic_get_unique_id(int ioa */ if (apic->check_apicid_used(&apic_id_map, apic_id)) { =20 - for (i =3D 0; i < get_physical_broadcast(); i++) { + for (i =3D 0; i < broadcast_id; i++) { if (!apic->check_apicid_used(&apic_id_map, i)) break; } =20 - if (i =3D=3D get_physical_broadcast()) + if (i =3D=3D broadcast_id) panic("Max apic_id exceeded!\n"); =20 - printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " - "trying %d\n", ioapic, apic_id, i); - + pr_warn("IOAPIC[%d]: apic_id %d already used, trying %d\n", ioapic, apic= _id, i); apic_id =3D i; } =20 @@ -2567,8 +2564,7 @@ static int io_apic_get_unique_id(int ioa =20 static u8 io_apic_unique_id(int idx, u8 id) { - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && - !APIC_XAPIC(boot_cpu_apic_version)) + if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && !APIC_XAPIC(boo= t_cpu_apic_version)) return io_apic_get_unique_id(idx, id); else return id; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB354C001DB for ; Mon, 7 Aug 2023 13:55:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233748AbjHGNzK (ORCPT ); Mon, 7 Aug 2023 09:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234488AbjHGNwq (ORCPT ); Mon, 7 Aug 2023 09:52:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB4D410EF for ; Mon, 7 Aug 2023 06:52:44 -0700 (PDT) Message-ID: <20230807135026.750360590@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ywrW7M6Fms0CIM+WhzKuJj3dJ+Q03lWwDFSQkWbNJj4=; b=duVsiKR3IhfLqm1YxgowBgn9OsTg7/0Em3YJSm/4NOr/GAa1YAq3Zl62aXNCjUhXG7gXCw 9JkbKk1zt6fH103uC6AeyBWd0ltnnPU5RKtOl87wdUMLN8WQCNccbrXMI2GvXRBCFO1vox QmbRnJ/oEMYVDiefiE7q9G6hMR2zADvgwG/pQZgDT815jTOlk8dv4ZMzCvEWBaYxeIgel8 E9Nl6okjjmNsU59T1njcSoM/ZtI1s4c4t50iH9FUBtif569Si55sE/NUBA0mTy0x0L4TBM Hm1NPILRCRuSXHYfMlcz5/GIdvSAH1pcKhP8XYxBRQM0zH78JjrtW2rMpJzruw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ywrW7M6Fms0CIM+WhzKuJj3dJ+Q03lWwDFSQkWbNJj4=; b=z/LJe82IgSIz5k4djTUhMxGR5alkqU8dX/ygjvlLM9X9uYOcnyFJVM266DrIoMtCxFacUQ /aCl7d38FjGQZODg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 06/53] x86/ioapic: Make io_apic_get_unique_id() simpler References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:42 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No need to go through APIC callbacks. It's already established that this is an ancient APIC. So just copy the present mask and use the direct physid* functions all over the place. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/apic/io_apic.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2498,17 +2498,9 @@ static int io_apic_get_unique_id(int ioa unsigned long flags; int i =3D 0; =20 - /* - * The P4 platform supports up to 256 APIC IDs on two separate APIC - * buses (one for LAPICs, one for IOAPICs), where predecessors only - * supports up to 16 on one shared APIC bus. - * - * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full - * advantage of new APIC bus architecture. - */ - + /* Initialize the ID map */ if (physids_empty(apic_id_map)) - apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); + apic_id_map =3D phys_cpu_present_map; =20 raw_spin_lock_irqsave(&ioapic_lock, flags); reg_00.raw =3D io_apic_read(ioapic, 0); @@ -2520,14 +2512,10 @@ static int io_apic_get_unique_id(int ioa apic_id =3D reg_00.bits.ID; } =20 - /* - * Every APIC in a system must have a unique ID or we get lots of nice - * 'stuck on smp_invalidate_needed IPI wait' messages. - */ - if (apic->check_apicid_used(&apic_id_map, apic_id)) { - + /* Every APIC in a system must have a unique ID */ + if (physid_isset(apic_id, apic_id_map)) { for (i =3D 0; i < broadcast_id; i++) { - if (!apic->check_apicid_used(&apic_id_map, i)) + if (!physid_isset(i, apic_id_map)) break; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA79AC001DB for ; Mon, 7 Aug 2023 13:55:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232283AbjHGNzH (ORCPT ); Mon, 7 Aug 2023 09:55:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234507AbjHGNwx (ORCPT ); Mon, 7 Aug 2023 09:52:53 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E13710D9 for ; Mon, 7 Aug 2023 06:52:46 -0700 (PDT) Message-ID: <20230807135026.802468362@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416364; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rdpVDGyxoao4mcEVei61Te5kVt75qdc74++NqQsV064=; b=xXRePEYimbFtTcQhqTXK7CmDyZdKWOQrW/h5sONM/hXLov0wCscOlYBnEkAw8OF+XwroDf klF+H+9LEF7KgA7AZfnzImbN2ORr7XuAyPHP+k5wl6PtQazASv/VshmfgEhEJfaVNkCzX9 qGu8lhxcr6QYtL9fmxulrueVRd/o+P2j4XYcuwqkmewf1WM8rqQyk0O8+5yFPJwpFk6k2l goPsrNFJp5uSLc4sx/aTi7vbKfCXJe9SYwJR2C6tLurwLpoaAmKH/QzX0SuMXS0dIVSQ50 kjpCCfby08QzkZG2gbdl4TlokyfPia0v01y0p7wiR9l0of1aeL0TAg1VpN9fxQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416364; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rdpVDGyxoao4mcEVei61Te5kVt75qdc74++NqQsV064=; b=yCxcrsAkpce6Ad8kxZ6KgA87XK0sbKAu/OQlXql/iTebm2gQzovKIarKeK3og6kHb9Zb00 bSXWBtH0h+GFrHBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 07/53] x86/ioapic: Simplify setup_ioapic_ids_from_mpc_nocheck() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:44 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No need to go through APIC callbacks. It's already established that this is an ancient APIC. So just copy the present mask and use the direct physid* functions all over the place. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/apic/io_apic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1471,7 +1471,7 @@ static void __init setup_ioapic_ids_from * This is broken; anything with a real cpu count has to * circumvent this idiocy regardless. */ - apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); + phys_id_present_map =3D phys_cpu_present_map; =20 /* * Set the IOAPIC ID to the value stored in the MPC table. @@ -1496,8 +1496,7 @@ static void __init setup_ioapic_ids_from * system must have a unique ID or we get lots of nice * 'stuck on smp_invalidate_needed IPI wait' messages. */ - if (apic->check_apicid_used(&phys_id_present_map, - mpc_ioapic_id(ioapic_idx))) { + if (physid_isset(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { pr_err("BIOS bug, IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); for (i =3D 0; i < broadcast_id; i++) From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 773CDC001DB for ; Mon, 7 Aug 2023 13:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234535AbjHGNx1 (ORCPT ); Mon, 7 Aug 2023 09:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234523AbjHGNwy (ORCPT ); Mon, 7 Aug 2023 09:52:54 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A9E91730 for ; Mon, 7 Aug 2023 06:52:48 -0700 (PDT) Message-ID: <20230807135026.854491808@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pV6oTjHlZpDv1EoB3lKno45EpFKoJahAlGz3jQzkcpE=; b=RYJC16Qg+xko8CIrW97uwJtJjai3Te5eCtMaVLupODScJPGvUnR9g3d/tsF2bK26F8xLZv DsvmHhb7jZotBd1Ex6My1pZS5HGwtDEMnshcdvLqytoswSc9MKgPm5u/cbqYZHVtjZ0T8T c5Zc3QI+2A/5Ris10Z4do2zkj9eoEhnzE5ILMccs2YTw5C+Us+E9g/nelH0X422odp0S+A u6cOn8A2caWEKxNQDoz0C0BKdddbHB+BDtHJlAE+Zf3V4JquWk9E2iEPIa813euSCpGUUy sXyiQr2ss8QE0xOjSxeoLmKF/EKt95qY+/W2yg10fQ/8vnTyZnHBzXMtr1PCIA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pV6oTjHlZpDv1EoB3lKno45EpFKoJahAlGz3jQzkcpE=; b=cdkdbtDQ4oLgW4u1nsn3j+7DcH7Uq1oK/zJW4YGMKdupOouSKUb/OOOJ6F79VQVOJz+B/B F+DRsCqxathE/KCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 08/53] x86/apic: Remove check_apicid_used() and ioapic_phys_id_map() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:45 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No more users. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 3 --- arch/x86/include/asm/mpspec.h | 6 ------ arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 13 ------------- arch/x86/kernel/apic/probe_32.c | 2 -- arch/x86/kernel/apic/x2apic_cluster.c | 2 -- 6 files changed, 28 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -292,9 +292,7 @@ struct apic { int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); bool (*apic_id_registered)(void); =20 - bool (*check_apicid_used)(physid_mask_t *map, u32 apicid); void (*init_apic_ldr)(void); - void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); u32 (*cpu_present_to_apicid)(int mps_cpu); =20 u32 (*get_apic_id)(u32 id); @@ -527,7 +525,6 @@ extern int default_apic_id_valid(u32 api extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); =20 -extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mas= k_t *retmap); extern u32 default_cpu_present_to_apicid(int mps_cpu); =20 #else /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -92,12 +92,6 @@ typedef struct physid_mask physid_mask_t #define physids_empty(map) \ bitmap_empty((map).mask, MAX_LOCAL_APIC) =20 -static inline void physids_promote(unsigned long physids, physid_mask_t *m= ap) -{ - physids_clear(*map); - map->mask[0] =3D physids; -} - static inline void physid_set_mask_of_physid(int physid, physid_mask_t *ma= p) { physids_clear(*map); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -51,8 +51,6 @@ struct apic apic_noop __ro_after_init =3D =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D default_check_apicid_used, - .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -18,17 +18,6 @@ static u32 bigsmp_get_apic_id(u32 x) return (x >> 24) & 0xFF; } =20 -static bool bigsmp_check_apicid_used(physid_mask_t *map, u32 apicid) -{ - return false; -} - -static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask= _t *retmap) -{ - /* For clustered we don't have a good way to do this yet - hack */ - physids_promote(0xFFL, retmap); -} - static void bigsmp_send_IPI_allbutself(int vector) { default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector); @@ -80,8 +69,6 @@ static struct apic apic_bigsmp __ro_afte =20 .disable_esr =3D 1, =20 - .check_apicid_used =3D bigsmp_check_apicid_used, - .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -45,9 +45,7 @@ static struct apic apic_default __ro_aft =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D default_check_apicid_used, .init_apic_ldr =3D default_init_apic_ldr, - .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -232,9 +232,7 @@ static struct apic apic_x2apic_cluster _ =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, .init_apic_ldr =3D init_x2apic_ldr, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D UINT_MAX, From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93D85C001DB for ; Mon, 7 Aug 2023 13:53:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234592AbjHGNxe (ORCPT ); Mon, 7 Aug 2023 09:53:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234479AbjHGNwz (ORCPT ); Mon, 7 Aug 2023 09:52:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35554199C for ; Mon, 7 Aug 2023 06:52:50 -0700 (PDT) Message-ID: <20230807135026.906384570@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/DR2OONcUrrpFOC5EnxrVQq2tzbpo7dJzpul3Y8MqQY=; b=Ggxxph+xB6huRwFVex14SKwImIP+1HUAKvsn/9s/9Rf2zM95rOa8S+fiNCvSVi8jcMMBUe 1aauBPqsooZBq2jNLD3i9kp+okDoQEfCeER8gCzwUTYrMpsX/x4FGcFhGWPMxsaeofBORf 7GGMBFCg2HhHGsNn0cCSfKH80T0FyzVt4NbUhNkFzq76BczCZIoNevj1QLuJI4+tEXHKEi TVc1BorBB+bmVjiLhf3f9euIX5i8QT4sPY5M1nAcrQZuyMvvN7XL8fPCLx2dCfIC2spOJh 1aR52Kffnvd1QG4SR5aKvwI07chg28WbS91eDVHTy5s+PgtTngVWbzoLxHoSKA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/DR2OONcUrrpFOC5EnxrVQq2tzbpo7dJzpul3Y8MqQY=; b=Mounl2QHL3IJulfH/WvCyDPKfqXww4d3rDp0mRc8KCcYVKFNkd/dDT/DynM50UIgX0yJzQ saDKJcW/5b2De6Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 09/53] x86/mpparse: Rename default_find_smp_config() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:47 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPTABLE is not longer the default SMP configuration mechanism. Rename it to mpparse_find_mptable() because that's what it does. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 13 ++++--------- arch/x86/include/asm/x86_init.h | 4 ++-- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/setup.c | 6 ++---- arch/x86/kernel/x86_init.c | 2 +- arch/x86/platform/ce4100/ce4100.c | 2 +- arch/x86/platform/intel-mid/intel-mid.c | 2 +- arch/x86/xen/smp_pv.c | 2 +- 8 files changed, 13 insertions(+), 20 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -56,21 +56,16 @@ static inline void early_get_smp_config( x86_init.mpparse.get_smp_config(1); } =20 -static inline void find_smp_config(void) -{ - x86_init.mpparse.find_smp_config(); -} - #ifdef CONFIG_X86_MPPARSE extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; -extern void default_find_smp_config(void); +extern void mpparse_find_mptable(void); extern void default_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } -#define enable_update_mptable 0 -#define default_find_smp_config x86_init_noop -#define default_get_smp_config x86_init_uint_noop +#define enable_update_mptable (0) +#define mpparse_find_mptable x86_init_noop +#define default_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -15,12 +15,12 @@ struct irq_domain; /** * struct x86_init_mpparse - platform specific mpparse ops * @setup_ioapic_ids: platform specific ioapic id override - * @find_smp_config: find the smp configuration + * @find_mptable: Find MPTABLE early to reserve the memory region * @get_smp_config: get the smp configuration */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); - void (*find_smp_config)(void); + void (*find_mptable)(void); void (*get_smp_config)(unsigned int early); }; =20 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -590,7 +590,7 @@ static int __init smp_scan_config(unsign return ret; } =20 -void __init default_find_smp_config(void) +void __init mpparse_find_mptable(void) { unsigned int address; =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1101,10 +1101,8 @@ void __init setup_arch(char **cmdline_p) high_memory =3D (void *)__va(max_pfn * PAGE_SIZE - 1) + 1; #endif =20 - /* - * Find and reserve possible boot-time SMP configuration: - */ - find_smp_config(); + /* Find and reserve MPTABLE area */ + x86_init.mpparse.find_mptable(); =20 early_alloc_pgt_buf(); =20 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -70,7 +70,7 @@ struct x86_init_ops x86_init __initdata =20 .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, - .find_smp_config =3D default_find_smp_config, + .find_mptable =3D mpparse_find_mptable, .get_smp_config =3D default_get_smp_config, }, =20 --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -138,7 +138,7 @@ void __init x86_ce4100_early_setup(void) x86_init.oem.arch_setup =3D sdv_arch_setup; x86_init.resources.probe_roms =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; =20 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -118,7 +118,7 @@ void __init x86_intel_mid_early_setup(vo machine_ops.emergency_restart =3D intel_mid_reboot; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -455,6 +455,6 @@ void __init xen_smp_init(void) smp_ops =3D xen_smp_ops; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B405EC001DB for ; Mon, 7 Aug 2023 13:53:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234567AbjHGNxb (ORCPT ); Mon, 7 Aug 2023 09:53:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234537AbjHGNwz (ORCPT ); Mon, 7 Aug 2023 09:52:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72EE319B7 for ; Mon, 7 Aug 2023 06:52:51 -0700 (PDT) Message-ID: <20230807135026.958541204@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lXvAKFXjZsZtpNvVsuWPTJGbTaymXF55DtvrpybYokk=; b=l1PZ8I8giV3b+mf4JVnWGkSVb1DnTyMcH4HCqJUibxXXnHCf2E0WsmrRnB+zpXKGx7i6Ms hwRBnofPezpEtZ1ebp0TjO/yKFWvIcTVCohVtwos9iSApAwLtEvoKsK5n4LOmXvaL+mrG7 55mYpHHT11kq5RhnShL9Wt11jawmNg9RCCdR0m5oNkGM8jbqTLgFbAysqA8WaSLDFD3xy6 4JX4DhivQHoCq1Eukpl8SPsGESkAkd0OjBj5QKivEW6QekR9SZh2fbwRJG7VivLiolSYqL 0bt67O62ZW+bqUfPB3rZIBjNlMkeAAUDvHZfkhGCIKwgqhkiCVF7aVKsa4As2A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lXvAKFXjZsZtpNvVsuWPTJGbTaymXF55DtvrpybYokk=; b=8AAFg35e1qoRQxuooevFqDgoPqOO+KTzGdPftEzlqfkvlGO8J/GvJ1y7ebTnEXzOdOs7Nq chnTu+Su1ZUXKqAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 10/53] x86/mpparse: Provide separate early/late callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:49 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The early argument of x86_init::mpparse::get_smp_config() is more than confusing. Provide two callbacks, one for each purpose. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/x86_init.h | 4 ++++ 1 file changed, 4 insertions(+) --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -17,11 +17,15 @@ struct irq_domain; * @setup_ioapic_ids: platform specific ioapic id override * @find_mptable: Find MPTABLE early to reserve the memory region * @get_smp_config: get the smp configuration + * @early_parse_smp_cfg: Parse the SMP configuration data early before ini= tmem_init() + * @parse_smp_cfg: Parse the SMP configuration data */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); void (*find_mptable)(void); void (*get_smp_config)(unsigned int early); + void (*early_parse_smp_cfg)(void); + void (*parse_smp_cfg)(void); }; =20 /** From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC8F5C001DB for ; Mon, 7 Aug 2023 13:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234571AbjHGNxi (ORCPT ); Mon, 7 Aug 2023 09:53:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234548AbjHGNw5 (ORCPT ); Mon, 7 Aug 2023 09:52:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1D6D1BCE for ; Mon, 7 Aug 2023 06:52:52 -0700 (PDT) Message-ID: <20230807135027.012341767@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416371; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C8gfQrn6Fv0quhrh8RYsTvXPC0AFtY95rXW+OtM42Wk=; b=DKmxB+Z4VxY3hYFXe9mL1sA7++zNl5UOjD8pk9tWSjse4jqL55SsQwtNsk9QHAscdsGB/A OPZS0QKCS9AIztKFys5IZEbY4EAEofzGyksYHySiGSFQuf7kHJcd8mCofQujbcIk5QniR9 /OKT5S72akKKvgdGUC7F6WXg0e1RsSBHRXE/N88fvGQxURY8L3845r1QOmJYvoJeKu+GTw QYkSyCt0A2XYl4cBOM/AHyukjw5zm5LoYwUFdFMiU7xdghxaYX22K49cUJl6khFyn9oxgt ZzaKMnH/b8fRQSlFR/xOqjdEJcCf9hGgbnvGmdbADZz3gsNfmMwUIllGLhGkNg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416371; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=C8gfQrn6Fv0quhrh8RYsTvXPC0AFtY95rXW+OtM42Wk=; b=nwkebDq1IoFYG9EoDAFOF+lAlqAORa2af+/vjE/NHeusFrzxdp9TBeeU+AFC9IzAEougkN fwPDyaWA83oIHYDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 11/53] x86/mpparse: Prepare for callback separation References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:50 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation of splitting the get_smp_config() callback, rename default_get_smp_config() to mpparse_get_smp_config() and provide an early and late wrapper. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 12 ++++++++---- arch/x86/kernel/mpparse.c | 12 +++++++++++- arch/x86/kernel/x86_init.c | 2 +- 3 files changed, 20 insertions(+), 6 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -60,12 +60,16 @@ static inline void early_get_smp_config( extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; extern void mpparse_find_mptable(void); -extern void default_get_smp_config(unsigned int early); +extern void mpparse_parse_early_smp_config(void); +extern void mpparse_parse_smp_config(void); +extern void mpparse_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } -#define enable_update_mptable (0) -#define mpparse_find_mptable x86_init_noop -#define default_get_smp_config x86_init_uint_noop +#define enable_update_mptable (0) +#define mpparse_find_mptable x86_init_noop +#define mpparse_parse_early_smp_config x86_init_noop +#define mpparse_parse_smp_config x86_init_noop +#define mpparse_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -476,7 +476,7 @@ static int __init check_physptr(struct m /* * Scan the memory blocks for an SMP configuration block. */ -void __init default_get_smp_config(unsigned int early) +void __init mpparse_get_smp_config(unsigned int early) { struct mpf_intel *mpf; =20 @@ -541,6 +541,16 @@ void __init default_get_smp_config(unsig early_memunmap(mpf, sizeof(*mpf)); } =20 +void __init mpparse_parse_early_smp_config(void) +{ + mpparse_get_smp_config(true); +} + +void __init mpparse_parse_smp_config(void) +{ + mpparse_get_smp_config(false); +} + static void __init smp_reserve_memory(struct mpf_intel *mpf) { memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -71,7 +71,7 @@ struct x86_init_ops x86_init __initdata .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, .find_mptable =3D mpparse_find_mptable, - .get_smp_config =3D default_get_smp_config, + .get_smp_config =3D mpparse_get_smp_config, }, =20 .irqs =3D { From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 549F7C00528 for ; Mon, 7 Aug 2023 13:53:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234498AbjHGNxl (ORCPT ); Mon, 7 Aug 2023 09:53:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234568AbjHGNw7 (ORCPT ); Mon, 7 Aug 2023 09:52:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 971E7F3 for ; Mon, 7 Aug 2023 06:52:54 -0700 (PDT) Message-ID: <20230807135027.064321764@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/LBxxfhEQgbaGsq91nXw+XvYY9V2TrRdpuXMU4IXdUM=; b=o8LQe7Ls4Z+/qGPCnSTzkqJR7EB9PiToMXBVPmICdCqg0/Km0aped2/ubIhsQNkXQl1z9n 1ajBj0Ku4iHL+Skz56EQgDFXxqxz7Ydgs/wKaei/FhaXs4l24iomECpgwygIwsjHvHxjW3 10ICos8H5LMLM1ms0qkEvLp+5Sj+YbCfu8+oGM1XTNTzZR5JCcDDWH9+yqSkp3shtqUO5t 96lJQCb27KgaMJ1Fc2wEUM3RPN4ixeU0IY/AgX+k0J057fgZz+tdA8wJ9NrbvZ3fvAa/E0 ia+/58ca7bfpBHHWvg8oGti2O1fzH+pxBsO8RctGz+fkkUyUaceE/53KMuLltg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/LBxxfhEQgbaGsq91nXw+XvYY9V2TrRdpuXMU4IXdUM=; b=S8EHjFNgdV+eWvx3T6Au9tOnjKenvPyGPuFUOHVr2kVZL2/oAUg4UCd/4JTuaxxtreoGx4 F58d3Bugq9s58xBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 12/53] x86/dtb: Rename x86_dtb_init() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" x86_dtb_init() is a misnomer and it really should be used as a SMP configuration parser which is selected by the platform via x86_init::mpparse:parse_smp_config(). Rename it to x86_dtb_parse_smp_config() in preparation for that. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/prom.h | 4 ++-- arch/x86/kernel/devicetree.c | 2 +- arch/x86/kernel/setup.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) --- a/arch/x86/include/asm/prom.h +++ b/arch/x86/include/asm/prom.h @@ -23,11 +23,11 @@ extern int of_ioapic; extern u64 initial_dtb; extern void add_dtb(u64 data); void x86_of_pci_init(void); -void x86_dtb_init(void); +void x86_dtb_parse_smp_config(void); #else static inline void add_dtb(u64 data) { } static inline void x86_of_pci_init(void) { } -static inline void x86_dtb_init(void) { } +static inline void x86_dtb_parse_smp_config(void) { } #define of_ioapic 0 #endif =20 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -304,7 +304,7 @@ static void __init x86_flattree_get_conf static inline void x86_flattree_get_config(void) { } #endif =20 -void __init x86_dtb_init(void) +void __init x86_dtb_parse_smp_config(void) { x86_flattree_get_config(); =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1260,7 +1260,7 @@ void __init setup_arch(char **cmdline_p) * Read APIC and some other early information from ACPI tables. */ acpi_boot_init(); - x86_dtb_init(); + x86_dtb_parse_smp_config(); =20 /* * get boot-time SMP configuration: From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DFB4C001DB for ; Mon, 7 Aug 2023 13:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234616AbjHGNxr (ORCPT ); Mon, 7 Aug 2023 09:53:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234577AbjHGNxB (ORCPT ); Mon, 7 Aug 2023 09:53:01 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50B51171E for ; Mon, 7 Aug 2023 06:52:55 -0700 (PDT) Message-ID: <20230807135027.116024518@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416374; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VT3e6NN7PgE82Og+WaclHeJcI+6c5zm7tVy4Rda9bOc=; b=nAPyiYOpE3R7FVPD7whSXhVfyWwIyd3HSmO7TchobLaeuBZCnG+k1AguAZRgCms1/gUX1R p7tjfuZrDYwdQodpFLBUB/1Th7SwQg52n2RnKuuxuScd87M2FY4Ah9NV403HMHkK0CXAi/ DCqA9KTwn1gV1a/bswWlK90aJBfCKXLMHKCMq6HZkSlVY0j4DBJ2EVX0BGC8VO6is1Lg49 M827KFJ1cgNxYAlEvYuU/7se7VmSkF+V4MCjkwM0oU6TXUOvWBhik7bvbgeVbAtf8iC/Yo 4yKxZJSdf5lG0k5OlJyhH2dq4ABHmtHXiZHi8yHSG7UkK4KF2VMUueQCermwGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416374; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VT3e6NN7PgE82Og+WaclHeJcI+6c5zm7tVy4Rda9bOc=; b=gdmTjHtSrcED4YAbdTEQuqDd4Roi44XV3/3Rm/+5+I7SnCzPZCsye6Bp9rreOW/GkiRwuq Lgb31IA7CGCb1rCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 13/53] x86/platform/ce4100: Prepare for separate mpparse callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:53 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Select x86_dtb_parse_smp_config() as SMP configuration parser in preparation of splitting up the get_smp_config() callback. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/platform/ce4100/ce4100.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -135,12 +135,14 @@ static void sdv_pci_init(void) */ void __init x86_ce4100_early_setup(void) { - x86_init.oem.arch_setup =3D sdv_arch_setup; - x86_init.resources.probe_roms =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.pci.init =3D ce4100_pci_init; - x86_init.pci.init_irq =3D sdv_pci_init; + x86_init.oem.arch_setup =3D sdv_arch_setup; + x86_init.resources.probe_roms =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D x86_dtb_parse_smp_config; + x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; + x86_init.pci.init =3D ce4100_pci_init; + x86_init.pci.init_irq =3D sdv_pci_init; =20 /* * By default, the reboot method is ACPI which is supported by the From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF3E6C001DB for ; Mon, 7 Aug 2023 13:53:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234522AbjHGNxn (ORCPT ); Mon, 7 Aug 2023 09:53:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234588AbjHGNxD (ORCPT ); Mon, 7 Aug 2023 09:53:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4A60171A for ; Mon, 7 Aug 2023 06:52:57 -0700 (PDT) Message-ID: <20230807135027.168401504@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416375; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LqyaDmi+Gzh0+dg6bnechLN5ICIJ4S0eJD1WXG6PgLM=; b=GNy0Ydiq3sdy/foH0ArUiskmpLF/oKnYPbtHG+9+/Al41Y2Ye6TOp+Seo0bkw+xouZIKDk LVDyvejIilLdHJpXRZ2idjyIXE20qIkcTmnkMpqAQrTNt5u45KQs2a28dxXD8sQN5nIVls djZFQo50WTfuWZriboleD4vQKJdlAoCdUrwMGbuOijP6QkMjt7N4CrXXgVw7DAEbxR31Wa 7x6VOU9zNFkA3nHwR0ehFPtmhxFxdKn/GG0WUU3aD5p8iN1qEzhmaQQsACRyCpZvfL/cfJ mV5hC6Lo5FmV9Ug17ksKV6oDMAh6747L9b5Qb6jZzeErv/o3EsJoeKXYPZlyzw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416375; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LqyaDmi+Gzh0+dg6bnechLN5ICIJ4S0eJD1WXG6PgLM=; b=mHwX04tEOT5rzbHO/pqepUuHDb34gOFsTX7dtlE6XL6/aEaZnDWUR7FIPnGZPYy5dih7Gz JN/UkYlr06kT/OAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 14/53] x86/platform/intel-mid: Prepare for separate mpparse callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:55 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initialize the split SMP configuration callbacks with NOOPs as MID is strictly ACPI only. Signed-off-by: Thomas Gleixner Acked-by: Andy Shevchenko Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/platform/intel-mid/intel-mid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -118,7 +118,9 @@ void __init x86_intel_mid_early_setup(vo machine_ops.emergency_restart =3D intel_mid_reboot; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6B03C001DB for ; Mon, 7 Aug 2023 13:53:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234632AbjHGNxw (ORCPT ); Mon, 7 Aug 2023 09:53:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234628AbjHGNxI (ORCPT ); Mon, 7 Aug 2023 09:53:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EC2C1998 for ; Mon, 7 Aug 2023 06:52:59 -0700 (PDT) Message-ID: <20230807135027.220542701@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416377; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=i7sHYpcfJ8EKrCzslt2cAc24NWY6qek5394P5PZEbDQ=; b=xAQ++Jeb+Bws6TZKoZprgVFN41qjVqyRoZrxNcbKYSE7HCHUH3izQG3H37/Ne7AE4sZnJf 4Ji1ddnHpxaq3LxwaSyZ6oVbxDwjLkLbot99d6K/QnxIFeJ3yjKCFcBpZrRd6TJEKkWIyH LnHp9b5RDo4O/tfbeYI0rqpkZ7noKLrNV66xMHwBZdSmy5Dmz0xEnWtRQekpptE+kuF8p1 i5C5+5ZQilAsSEEJl0ZJnM9pIQ/n4XRbS5xMGfU1/WpMM0FIrqd8Ra7Ij1quzBu36X2R4l ygoUyh41HVQrnBAV5VjZXAezj2GfcY8veyzg+yXUPEg06wdzxqwhzbuy6EP9PA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416377; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=i7sHYpcfJ8EKrCzslt2cAc24NWY6qek5394P5PZEbDQ=; b=J+42HbohHoZY8IBobNxA3UyjtM/YGMN0JHljRLaHwjgARHDCbePa1M9g8a9X9Awe4JKQjt 21fpEsZfZMJH9rBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 15/53] x86/jailhouse: Prepare for separate mpparse callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:56 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide a wrapper around the existing function and fill the new callbacks in. No functional change as the new callbacks are not yet operational. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/jailhouse.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -118,6 +118,11 @@ static void __init jailhouse_get_smp_con } } =20 +static void __init jailhouse_parse_smp_config(void) +{ + jailhouse_get_smp_config(false); +} + static void jailhouse_no_restart(void) { pr_notice("Jailhouse: Restart not supported, halting\n"); @@ -201,21 +206,24 @@ static void __init jailhouse_init_platfo struct setup_data header; void *mapping; =20 - x86_init.irqs.pre_vector_init =3D x86_init_noop; - x86_init.timers.timer_init =3D jailhouse_timer_init; - x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; - x86_init.pci.arch_init =3D jailhouse_pci_arch_init; - - x86_platform.calibrate_cpu =3D jailhouse_get_tsc; - x86_platform.calibrate_tsc =3D jailhouse_get_tsc; - x86_platform.get_wallclock =3D jailhouse_get_wallclock; - x86_platform.legacy.rtc =3D 0; - x86_platform.legacy.warm_reset =3D 0; - x86_platform.legacy.i8042 =3D X86_LEGACY_I8042_PLATFORM_ABSENT; + x86_init.irqs.pre_vector_init =3D x86_init_noop; + x86_init.timers.timer_init =3D jailhouse_timer_init; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D jailhouse_parse_smp_config; + x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; + x86_init.pci.arch_init =3D jailhouse_pci_arch_init; + + x86_platform.calibrate_cpu =3D jailhouse_get_tsc; + x86_platform.calibrate_tsc =3D jailhouse_get_tsc; + x86_platform.get_wallclock =3D jailhouse_get_wallclock; + x86_platform.legacy.rtc =3D 0; + x86_platform.legacy.warm_reset =3D 0; + x86_platform.legacy.i8042 =3D X86_LEGACY_I8042_PLATFORM_ABSENT; =20 - legacy_pic =3D &null_legacy_pic; + legacy_pic =3D &null_legacy_pic; =20 - machine_ops.emergency_restart =3D jailhouse_no_restart; + machine_ops.emergency_restart =3D jailhouse_no_restart; =20 while (pa_data) { mapping =3D early_memremap(pa_data, sizeof(header)); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4BA6C001DB for ; Mon, 7 Aug 2023 13:53:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234650AbjHGNx4 (ORCPT ); Mon, 7 Aug 2023 09:53:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234639AbjHGNxJ (ORCPT ); Mon, 7 Aug 2023 09:53:09 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A0BA19AF for ; Mon, 7 Aug 2023 06:53:00 -0700 (PDT) Message-ID: <20230807135027.272696521@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416379; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EYJQm55oUOskfK42q+cCkqIk4Ng20LK8t+Y3B5NsE1Q=; b=zU/CWefGrrijcHZNe0gp8+zI3xflV8ngWsF8njohR2f4n44hzAZZ83gdmS6ndp4hGx4glT XFvBE3diBtAuFI4fIEA3sYNoOxWEEy3GqImCH0fijuJcHtJ3WmN83k90zlZeJpRJNB0v1o xbklaBa/UbYNa92h3NuvNSiNcAtuQj0cvbgMSqA4Zdtsi8PXT/wUOoL3A+AhjePhMXFIXp wVz3C4V5R/AvkbWAfkSv3hMxiMbUqd2CgB0zgqxkF3JfLuoAR3VMEwBRgQrvio4733aGvP T6tzKGixPwJCoBstE4r/2ppRfjwxZy/UyPZqLwwKXFdCXQ+K/NfiuEPtJ0gMGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416379; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EYJQm55oUOskfK42q+cCkqIk4Ng20LK8t+Y3B5NsE1Q=; b=2AcvcxdJ5xheNZyDGUkC3lOpedA6m5v74DCE56NsaMpqFxzH2sM80u+O4KTMsw8S843rEW iYwf+/1fO8rMOGCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 16/53] x86/xen/smp_pv: Prepare for separate mpparse callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:52:58 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide a wrapper around the existing function and fill the new callbacks in. No functional change as the new callbacks are not yet operational. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/xen/smp_pv.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -185,6 +185,11 @@ static void __init _get_smp_config(unsig smp_found_config =3D 1; } =20 +static void __init xen_pv_smp_config(void) +{ + _get_smp_config(false); +} + static void __init xen_pv_smp_prepare_boot_cpu(void) { BUG_ON(smp_processor_id() !=3D 0); @@ -455,6 +460,8 @@ void __init xen_smp_init(void) smp_ops =3D xen_smp_ops; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D _get_smp_config; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; + x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B99DCC001DB for ; Mon, 7 Aug 2023 13:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234507AbjHGNzO (ORCPT ); Mon, 7 Aug 2023 09:55:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234657AbjHGNxL (ORCPT ); Mon, 7 Aug 2023 09:53:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99E6E10E3 for ; Mon, 7 Aug 2023 06:53:02 -0700 (PDT) Message-ID: <20230807135027.325035194@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416380; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YQj0mbugupK3s4rnQKmheA6BGCf72U3w0+Zs2FhDv6A=; b=ULdCZPdaFlo1JW2L27s8mHzKDfVh2jhr+Gls01doUvEMntO323Nu/G8Cl/BAdNbCMNKRRR /t0ItSKzRMeZevIzvA2pnG1Fdr4eehGlpBDZbXkBdB2jXmM/gW3fCTHbUZ4NgEKMxod+2V /FeHZKdMNugTIX567QSqEMhkhjBGolerHkNXtQO+3pB3voH6AwSWGBRt32dQTZcd/6dyxv aNGrWjjlkPAbiGeQKzewMc9+R6bYJD03seuad1FiIR5xYTriuV53GWOtboXzHTkYymCoAJ yzQ4uhnBGmQ0tDthAMdxE9p8BEr/7egmBW+3MZDOdt3ULmDGmuk/xY5OoSeLqQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416380; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YQj0mbugupK3s4rnQKmheA6BGCf72U3w0+Zs2FhDv6A=; b=QD11Y5qSxj9ajqI/xG8qBcB7MRf+scLbnryYlvCpyD98y4KsLJDEa80APB2QJnyh8WZDGt PEA70GosbDsEiXCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 17/53] x86/mpparse: Switch to new init callbacks References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:00 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that all platforms have the new split SMP configuration callbacks set up, flip the switch and remove the old callback pointer and mop up the platform code. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 9 +-------- arch/x86/include/asm/x86_init.h | 2 -- arch/x86/kernel/jailhouse.c | 8 +------- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/setup.c | 10 +++------- arch/x86/kernel/x86_init.c | 3 ++- arch/x86/platform/ce4100/ce4100.c | 1 - arch/x86/platform/intel-mid/intel-mid.c | 1 - arch/x86/xen/smp_pv.c | 11 +---------- 9 files changed, 9 insertions(+), 38 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -46,14 +46,9 @@ extern int smp_found_config; # define smp_found_config 0 #endif =20 -static inline void get_smp_config(void) -{ - x86_init.mpparse.get_smp_config(0); -} - static inline void early_get_smp_config(void) { - x86_init.mpparse.get_smp_config(1); + x86_init.mpparse.early_parse_smp_cfg(); } =20 #ifdef CONFIG_X86_MPPARSE @@ -62,14 +57,12 @@ extern int enable_update_mptable; extern void mpparse_find_mptable(void); extern void mpparse_parse_early_smp_config(void); extern void mpparse_parse_smp_config(void); -extern void mpparse_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } #define enable_update_mptable (0) #define mpparse_find_mptable x86_init_noop #define mpparse_parse_early_smp_config x86_init_noop #define mpparse_parse_smp_config x86_init_noop -#define mpparse_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -16,14 +16,12 @@ struct irq_domain; * struct x86_init_mpparse - platform specific mpparse ops * @setup_ioapic_ids: platform specific ioapic id override * @find_mptable: Find MPTABLE early to reserve the memory region - * @get_smp_config: get the smp configuration * @early_parse_smp_cfg: Parse the SMP configuration data early before ini= tmem_init() * @parse_smp_cfg: Parse the SMP configuration data */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); void (*find_mptable)(void); - void (*get_smp_config)(unsigned int early); void (*early_parse_smp_cfg)(void); void (*parse_smp_cfg)(void); }; --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -89,7 +89,7 @@ static void __init jailhouse_x2apic_init #endif } =20 -static void __init jailhouse_get_smp_config(unsigned int early) +static void __init jailhouse_parse_smp_config(void) { struct ioapic_domain_cfg ioapic_cfg =3D { .type =3D IOAPIC_DOMAIN_STRICT, @@ -118,11 +118,6 @@ static void __init jailhouse_get_smp_con } } =20 -static void __init jailhouse_parse_smp_config(void) -{ - jailhouse_get_smp_config(false); -} - static void jailhouse_no_restart(void) { pr_notice("Jailhouse: Restart not supported, halting\n"); @@ -211,7 +206,6 @@ static void __init jailhouse_init_platfo x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D jailhouse_parse_smp_config; - x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; x86_init.pci.arch_init =3D jailhouse_pci_arch_init; =20 x86_platform.calibrate_cpu =3D jailhouse_get_tsc; --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -476,7 +476,7 @@ static int __init check_physptr(struct m /* * Scan the memory blocks for an SMP configuration block. */ -void __init mpparse_get_smp_config(unsigned int early) +static __init void mpparse_get_smp_config(unsigned int early) { struct mpf_intel *mpf; =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1257,15 +1257,11 @@ void __init setup_arch(char **cmdline_p) early_quirks(); =20 /* - * Read APIC and some other early information from ACPI tables. + * Parse SMP configuration. Try ACPI first and then the platform + * specific parser. */ acpi_boot_init(); - x86_dtb_parse_smp_config(); - - /* - * get boot-time SMP configuration: - */ - get_smp_config(); + x86_init.mpparse.parse_smp_cfg(); =20 /* * Systems w/o ACPI and mptables might not have it mapped the local --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -71,7 +71,8 @@ struct x86_init_ops x86_init __initdata .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, .find_mptable =3D mpparse_find_mptable, - .get_smp_config =3D mpparse_get_smp_config, + .early_parse_smp_cfg =3D mpparse_parse_early_smp_config, + .parse_smp_cfg =3D mpparse_parse_smp_config, }, =20 .irqs =3D { --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -140,7 +140,6 @@ void __init x86_ce4100_early_setup(void) x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D x86_dtb_parse_smp_config; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; =20 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -121,6 +121,5 @@ void __init x86_intel_mid_early_setup(vo x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -148,14 +148,11 @@ int xen_smp_intr_init_pv(unsigned int cp return rc; } =20 -static void __init _get_smp_config(unsigned int early) +static void __init xen_pv_smp_config(void) { int i, rc; unsigned int subtract =3D 0; =20 - if (early) - return; - num_processors =3D 0; disabled_cpus =3D 0; for (i =3D 0; i < nr_cpu_ids; i++) { @@ -185,11 +182,6 @@ static void __init _get_smp_config(unsig smp_found_config =3D 1; } =20 -static void __init xen_pv_smp_config(void) -{ - _get_smp_config(false); -} - static void __init xen_pv_smp_prepare_boot_cpu(void) { BUG_ON(smp_processor_id() !=3D 0); @@ -463,5 +455,4 @@ void __init xen_smp_init(void) x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; - x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BBF5C001DB for ; Mon, 7 Aug 2023 13:54:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234005AbjHGNyD (ORCPT ); Mon, 7 Aug 2023 09:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234687AbjHGNxR (ORCPT ); Mon, 7 Aug 2023 09:53:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AEFDF3 for ; Mon, 7 Aug 2023 06:53:04 -0700 (PDT) Message-ID: <20230807135027.376971897@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416382; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yHYtAXx6N+Nk90fJ68YHnOml1CTtFncFuulQcHEIemo=; b=sUlBhXS3CeJIVrozDtyIqT0AiVrVCCwyVOZPaJcE5XbABJz6THG5116OY0/t4X0AAlVVo5 7NhxRlcpmwm2Ahm3z/odYBqqxJrwFoU4lgchBEKzhevXi/UVEisYcJkIyEmX2Ew9sukaQH 30/TMsqtsImsY8I40f4jIpH84OaqVggDb12Tf7SJECueCNwknE8CeWc/uycb2vb2koU8dT xqC17cTFcsA20QdRUEBqGRcDUCvQ4oTHAJEjJJBfTAKadit20UMxdQhH9VFdr7tJotJFin D6B5W1xqulHftJ9ArZkel4r9m8SAIOSXORvrqdv0b8dxYluopJaroGWHUQlrpA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416382; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yHYtAXx6N+Nk90fJ68YHnOml1CTtFncFuulQcHEIemo=; b=Q97rvNeZksJfDAPWmSUaS97IrlyN0EWGYpWrZNFUZyZQIiBf6fQ3z6AEMJ488VMB8r0YTX 9X+BYZJ88LHtpUDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 18/53] x86/mm/numa: Move early mptable evaluation into common code References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:01 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no reason to have the early mptable evaluation conditionally invoked only from the AMD numa topology code. Make it explicit and invoke it from setup_arch() right after the corresponding ACPI init call. Remove the pointless wrapper and invoke x86_init::mpparse::early_parse_smp_config() directly. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 5 ----- arch/x86/kernel/setup.c | 2 ++ arch/x86/mm/amdtopology.c | 7 ------- 3 files changed, 2 insertions(+), 12 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -46,11 +46,6 @@ extern int smp_found_config; # define smp_found_config 0 #endif =20 -static inline void early_get_smp_config(void) -{ - x86_init.mpparse.early_parse_smp_cfg(); -} - #ifdef CONFIG_X86_MPPARSE extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1217,7 +1217,9 @@ void __init setup_arch(char **cmdline_p) =20 early_platform_quirks(); =20 + /* Some platforms need the APIC registered for NUMA configuration */ early_acpi_boot_init(); + x86_init.mpparse.early_parse_smp_cfg(); =20 initmem_init(); dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT); --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -161,13 +161,6 @@ int __init amd_numa_init(void) */ cores =3D topology_get_domain_size(TOPO_CORE_DOMAIN); =20 - /* - * Scan MPTABLE to map the local APIC and ensure that the boot CPU - * APIC ID is valid. This is required because on pre ACPI/SRAT - * systems IO-APICs are mapped before the boot CPU. - */ - early_get_smp_config(); - apicid =3D boot_cpu_physical_apicid; if (apicid > 0) pr_info("BSP APIC ID: %02x\n", apicid); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D7CC001DB for ; Mon, 7 Aug 2023 13:54:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233714AbjHGNyA (ORCPT ); Mon, 7 Aug 2023 09:54:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234680AbjHGNxQ (ORCPT ); Mon, 7 Aug 2023 09:53:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B34F10DD for ; Mon, 7 Aug 2023 06:53:05 -0700 (PDT) Message-ID: <20230807135027.429700142@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416383; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yol4ZyfHQSxZQJA77CTzCpYOMt3ZEt27rTf+TDR+avM=; b=Vcymf213KGOEpIrOA4jXGVCsKG7I2hk4jsVwuktIERBGHdS3xzlk58vrIzz6xaznsIPYmr s7/v+xs96j1roErVFshAqkagIW5A0hXF7NgrpRnBaItT3PnOPllEJM1aHX/tjn3z0Tfm8P kJmidB66Sd8NKH4y3y6+IK6K2AN317Hjx2VyEuRchYrJr0uKafen63AEj6yfhhpUme+GSj FsYSe6YpRYJFB9HeoKI6BWD87ns/BTUHQc9KrxJlpeBZc2xHqrn/f/iw4R/kUNEHEbFCcF 3JJ+MwYEfpjynCO4ohUgYd8ghmM+XBtt6CHaCapxNJ58d0k8Vy1Vm6jDR2mX7A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416383; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yol4ZyfHQSxZQJA77CTzCpYOMt3ZEt27rTf+TDR+avM=; b=CdhPAx1GgB/JPzjcNuuXv7IFLrdX3A2r3dSOnRGFhC9mLFT7F9xrDrvuH+044l2/OjjW0L Aky9N38LTxewZJDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 19/53] x86/mpparse: Remove the physid_t bitmap wrapper References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:03 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" physid_t is a wrapper around bitmap. Just remove the onion layer and use bitmap functionality directly. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 32 +++++++++----------------------- arch/x86/kernel/apic/apic.c | 11 +++++------ arch/x86/kernel/apic/apic_common.c | 12 +----------- arch/x86/kernel/apic/io_apic.c | 24 ++++++++++++------------ arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/smpboot.c | 8 +++----- 6 files changed, 30 insertions(+), 58 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -2,6 +2,7 @@ #ifndef _ASM_X86_MPSPEC_H #define _ASM_X86_MPSPEC_H =20 +#include =20 #include #include @@ -62,32 +63,17 @@ static inline void e820__memblock_alloc_ =20 int generic_processor_info(int apicid); =20 -#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) +extern DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 -struct physid_mask { - unsigned long mask[PHYSID_ARRAY_SIZE]; -}; - -typedef struct physid_mask physid_mask_t; - -#define physid_set(physid, map) set_bit(physid, (map).mask) -#define physid_isset(physid, map) test_bit(physid, (map).mask) - -#define physids_clear(map) \ - bitmap_zero((map).mask, MAX_LOCAL_APIC) - -#define physids_empty(map) \ - bitmap_empty((map).mask, MAX_LOCAL_APIC) - -static inline void physid_set_mask_of_physid(int physid, physid_mask_t *ma= p) +static inline void reset_phys_cpu_present_map(u32 apicid) { - physids_clear(*map); - physid_set(physid, *map); + bitmap_zero(phys_cpu_present_map, MAX_LOCAL_APIC); + set_bit(apicid, phys_cpu_present_map); } =20 -#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] =3D ~0UL} } -#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] =3D 0UL} } - -extern physid_mask_t phys_cpu_present_map; +static inline void copy_phys_cpu_present_map(unsigned long *dst) +{ + bitmap_copy(dst, phys_cpu_present_map, MAX_LOCAL_APIC); +} =20 #endif /* _ASM_X86_MPSPEC_H */ --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -77,10 +78,8 @@ EXPORT_SYMBOL_GPL(boot_cpu_physical_apic =20 u8 boot_cpu_apic_version __ro_after_init; =20 -/* - * Bitmask of physically existing CPUs: - */ -physid_mask_t phys_cpu_present_map; +/* Bitmap of physically present CPUs. */ +DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 /* * Processor to be disabled specified by kernel parameter @@ -2387,7 +2386,7 @@ static void cpu_update_apic(int cpu, u32 early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif set_cpu_possible(cpu, true); - physid_set(apicid, phys_cpu_present_map); + set_bit(apicid, phys_cpu_present_map); set_cpu_present(cpu, true); num_processors++; =20 @@ -2489,7 +2488,7 @@ static void __init apic_bsp_up_setup(voi #ifdef CONFIG_X86_64 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); #endif - physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map= ); + reset_phys_cpu_present_map(boot_cpu_physical_apicid); } =20 /** --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -18,16 +18,6 @@ u32 apic_flat_calc_apicid(unsigned int c return 1U << cpu; } =20 -bool default_check_apicid_used(physid_mask_t *map, u32 apicid) -{ - return physid_isset(apicid, *map); -} - -void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *re= tmap) -{ - *retmap =3D *phys_map; -} - u32 default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) @@ -39,7 +29,7 @@ EXPORT_SYMBOL_GPL(default_cpu_present_to =20 bool default_apic_id_registered(void) { - return physid_isset(read_apic_id(), phys_cpu_present_map); + return test_bit(read_apic_id(), phys_cpu_present_map); } =20 /* --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1460,7 +1460,7 @@ void restore_boot_irq_mode(void) */ static void __init setup_ioapic_ids_from_mpc_nocheck(void) { - physid_mask_t phys_id_present_map; + DECLARE_BITMAP(phys_id_present_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned char old_id; @@ -1471,7 +1471,7 @@ static void __init setup_ioapic_ids_from * This is broken; anything with a real cpu count has to * circumvent this idiocy regardless. */ - phys_id_present_map =3D phys_cpu_present_map; + copy_phys_cpu_present_map(phys_id_present_map); =20 /* * Set the IOAPIC ID to the value stored in the MPC table. @@ -1496,21 +1496,21 @@ static void __init setup_ioapic_ids_from * system must have a unique ID or we get lots of nice * 'stuck on smp_invalidate_needed IPI wait' messages. */ - if (physid_isset(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { + if (test_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { pr_err("BIOS bug, IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); for (i =3D 0; i < broadcast_id; i++) - if (!physid_isset(i, phys_id_present_map)) + if (!test_bit(i, phys_id_present_map)) break; if (i >=3D broadcast_id) panic("Max APIC ID exceeded!\n"); pr_err("... fixing up to %d. (tell your hw vendor)\n", i); - physid_set(i, phys_id_present_map); + set_bit(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", mpc_ioapic_id(ioapic_idx)); - physid_set(mpc_ioapic_id(ioapic_idx), phys_id_present_map); + set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } =20 /* @@ -2491,15 +2491,15 @@ unsigned int arch_dynirq_lower_bound(uns #ifdef CONFIG_X86_32 static int io_apic_get_unique_id(int ioapic, int apic_id) { - static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; + static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; =20 /* Initialize the ID map */ - if (physids_empty(apic_id_map)) - apic_id_map =3D phys_cpu_present_map; + if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC)) + copy_phys_cpu_present_map(apic_id_map); =20 raw_spin_lock_irqsave(&ioapic_lock, flags); reg_00.raw =3D io_apic_read(ioapic, 0); @@ -2512,9 +2512,9 @@ static int io_apic_get_unique_id(int ioa } =20 /* Every APIC in a system must have a unique ID */ - if (physid_isset(apic_id, apic_id_map)) { + if (test_bit(apic_id, apic_id_map)) { for (i =3D 0; i < broadcast_id; i++) { - if (!physid_isset(i, apic_id_map)) + if (!test_bit(i, apic_id_map)) break; } =20 @@ -2525,7 +2525,7 @@ static int io_apic_get_unique_id(int ioa apic_id =3D i; } =20 - physid_set(apic_id, apic_id_map); + set_bit(apic_id, apic_id_map); =20 if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -63,7 +63,6 @@ void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 bool default_apic_id_registered(void); -bool default_check_apicid_used(physid_mask_t *map, u32 apicid); =20 #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1081,7 +1081,7 @@ int native_kick_ap(unsigned int cpu, str =20 pr_debug("++++++++++++++++++++=3D_---CPU UP %u\n", cpu); =20 - if (apicid =3D=3D BAD_APICID || !physid_isset(apicid, phys_cpu_present_ma= p) || + if (apicid =3D=3D BAD_APICID || !test_bit(apicid, phys_cpu_present_map) || !apic_id_valid(apicid)) { pr_err("%s: bad cpu %d\n", __func__, cpu); return -EINVAL; @@ -1156,10 +1156,8 @@ static __init void disable_smp(void) init_cpu_present(cpumask_of(0)); init_cpu_possible(cpumask_of(0)); =20 - if (smp_found_config) - physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_ma= p); - else - physid_set_mask_of_physid(0, &phys_cpu_present_map); + reset_phys_cpu_present_map(smp_found_config ? boot_cpu_physical_apicid : = 0); + cpumask_set_cpu(0, topology_sibling_cpumask(0)); cpumask_set_cpu(0, topology_core_cpumask(0)); cpumask_set_cpu(0, topology_die_cpumask(0)); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83C1CC001DB for ; Mon, 7 Aug 2023 13:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234667AbjHGNyF (ORCPT ); Mon, 7 Aug 2023 09:54:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234705AbjHGNxV (ORCPT ); Mon, 7 Aug 2023 09:53:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29CD1171A for ; Mon, 7 Aug 2023 06:53:06 -0700 (PDT) Message-ID: <20230807135027.482353656@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416385; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XKmrv7R2S+3/o3K90lEiBlMfc0sBkVkBuauG2ySKEQU=; b=t2Q/sQf8+jndQxri+6gDM4FNwZyTbhsbph88I18heS+1YqxAUUQuzAPNcTa8LQccL6EJFk AJDol1MAUHiV6nUM4Ran7vEn2IIMquqArvEirZ5m1Wddweu6qtT+aX3zYNn6mTKjcxmXMK yL9cqvxIn2sAhAxuB7NMux0VHSS6lMBtpyIGlJ+oXCAk8Qu3qqTne+v34pbkW9tqEZw6QC rkviZ0wJg5hPArDhQpKT/xsyEfWkmyoipvGJHLkA6VnG3LD5AaKR5uphDMNlj7S581j3At /+RNrRRfwayck3xrpjbR7Gmj/v1D7jhyJUj6ACXmNh4QXwwVHtQ+yrOd3heUxQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416385; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XKmrv7R2S+3/o3K90lEiBlMfc0sBkVkBuauG2ySKEQU=; b=3Kz8NwHkNQb02kCYlq8YOxE3JO0uetfk7uxR6i+UkScPTEQfaJyg95SmkuzknRBxhQmJHL IT/1HSuXrUDPbIAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 20/53] x86/apic: Remove the pointless writeback of boot_cpu_physical_apicid References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:04 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is absolutely no point to write the APIC ID which was read from the local APIC earlier, back into the local APIC for the 64-bit UP case. Remove that along with the apic callback which is solely there for this pointless exercise. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 3 --- arch/x86/kernel/apic/apic_flat_64.c | 7 ------- arch/x86/kernel/apic/apic_numachip.c | 12 ------------ arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 6 ------ arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 7 ------- 10 files changed, 45 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -296,7 +296,6 @@ struct apic { u32 (*cpu_present_to_apicid)(int mps_cpu); =20 u32 (*get_apic_id)(u32 id); - u32 (*set_apic_id)(u32 apicid); =20 /* wakeup_secondary_cpu */ int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2474,9 +2474,6 @@ EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid =20 static void __init apic_bsp_up_setup(void) { -#ifdef CONFIG_X86_64 - apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); -#endif reset_phys_cpu_present_map(boot_cpu_physical_apicid); } =20 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -61,11 +61,6 @@ static u32 flat_get_apic_id(u32 x) return (x >> 24) & 0xFF; } =20 -static u32 set_apic_id(u32 id) -{ - return (id & 0xFF) << 24; -} - static int flat_probe(void) { return 1; @@ -87,7 +82,6 @@ static struct apic apic_flat __ro_after_ =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, =20 @@ -156,7 +150,6 @@ static struct apic apic_physflat __ro_af =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -38,11 +38,6 @@ static u32 numachip1_get_apic_id(u32 x) return id; } =20 -static u32 numachip1_set_apic_id(u32 id) -{ - return (id & 0xff) << 24; -} - static u32 numachip2_get_apic_id(u32 x) { u64 mcfg; @@ -51,11 +46,6 @@ static u32 numachip2_get_apic_id(u32 x) return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); } =20 -static u32 numachip2_set_apic_id(u32 id) -{ - return id << 24; -} - static void numachip1_apic_icr_write(int apicid, unsigned int val) { write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); @@ -226,7 +216,6 @@ static const struct apic apic_numachip1 =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip1_get_apic_id, - .set_apic_id =3D numachip1_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 @@ -262,7 +251,6 @@ static const struct apic apic_numachip2 =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip2_get_apic_id, - .set_apic_id =3D numachip2_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -73,7 +73,6 @@ static struct apic apic_bigsmp __ro_afte =20 .max_apic_id =3D 0xFE, .get_apic_id =3D bigsmp_get_apic_id, - .set_apic_id =3D NULL, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -16,7 +16,6 @@ /* X2APIC */ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); u32 x2apic_get_apic_id(u32 id); -u32 x2apic_set_apic_id(u32 id); =20 void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -238,7 +238,6 @@ static struct apic apic_x2apic_cluster _ .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D x2apic_set_apic_id, =20 .calc_dest_apicid =3D x2apic_calc_apicid, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -129,11 +129,6 @@ u32 x2apic_get_apic_id(u32 id) return id; } =20 -u32 x2apic_set_apic_id(u32 id) -{ - return id; -} - static struct apic apic_x2apic_phys __ro_after_init =3D { =20 .name =3D "physical x2apic", @@ -150,7 +145,6 @@ static struct apic apic_x2apic_phys __ro .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D x2apic_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -746,11 +746,6 @@ static void uv_send_IPI_all(int vector) uv_send_IPI_mask(cpu_online_mask, vector); } =20 -static u32 set_apic_id(u32 id) -{ - return id; -} - static int uv_probe(void) { return apic =3D=3D &apic_x2apic_uv_x; @@ -771,7 +766,6 @@ static struct apic apic_x2apic_uv_x __ro =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -33,12 +33,6 @@ static unsigned int xen_io_apic_read(uns return 0xfd; } =20 -static u32 xen_set_apic_id(u32 x) -{ - WARN_ON(1); - return x; -} - static u32 xen_get_apic_id(u32 x) { return ((x)>>24) & 0xFFu; @@ -131,7 +125,6 @@ static struct apic xen_pv_apic __ro_afte =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D xen_get_apic_id, - .set_apic_id =3D xen_set_apic_id, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC857C00528 for ; Mon, 7 Aug 2023 13:54:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234670AbjHGNyI (ORCPT ); Mon, 7 Aug 2023 09:54:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234709AbjHGNxV (ORCPT ); Mon, 7 Aug 2023 09:53:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51A7310EF for ; Mon, 7 Aug 2023 06:53:08 -0700 (PDT) Message-ID: <20230807135027.534633642@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416386; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=X3MHNyfBXHRhCX+hsuUai8tmF+yG5iARhPCZvhjm+2M=; b=DXXMbB2Ho7x5WE9SUSWUdchy2gfXzWq0UFOCFSaDvrDoTN2KL57RtE5fjtCI11M3E7jC3g soyHA2R3toj+lboJxDLPjyXRtxJF08H8lDWGlGExuAb22DdZaVI23TiEmablAYUhnQHTFM aMeslJnt1Jx9y9rB9BC4wZp6bvEuTxZlQ4avYoDQhAwzwBlv3v5y6wDs9KYG6S/bSLbNM9 ZYsZdAfXr9yqbj3qM4xbJB/5R8cJb6LIFjmzxtJZ7gmnsndtoiaGdpWcB+RU/h9pVjBXlG j/aR6ykPmdJErusxeHiPiXHZoJH27MskEf8G3MB72OqH5rUitJCYW6tHII09CQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416386; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=X3MHNyfBXHRhCX+hsuUai8tmF+yG5iARhPCZvhjm+2M=; b=3SCvDxL2pthhEffENN4YrI6PMPhCiJmnKafwaOimCLKSKOTr+6Rzcf5jftcH2d0qi7fZ2Y YRNhFQ1RUweR4BAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 21/53] x86/apic: Remove yet another dubious callback References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:06 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Paranoia is not wrong, but having an APIC callback which is in most implementations a complete NOOP and in one actually looking whether the APICID of an upcoming CPU has been registered. The same APICID which was used to bring the CPU out of wait for startup. That's paranoia for the paranoia sake. Remove the voodoo. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 3 --- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/local.h | 2 -- arch/x86/kernel/apic/probe_32.c | 1 - 6 files changed, 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -290,7 +290,6 @@ struct apic { /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); - bool (*apic_id_registered)(void); =20 void (*init_apic_ldr)(void); u32 (*cpu_present_to_apicid)(int mps_cpu); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1538,9 +1538,6 @@ static void setup_local_APIC(void) apic_write(APIC_ESR, 0); } #endif - /* Validate that the APIC is registered if required */ - BUG_ON(apic->apic_id_registered && !apic->apic_id_registered()); - /* * Intel recommends to set DFR, LDR and TPR before enabling * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -27,11 +27,6 @@ u32 default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); =20 -bool default_apic_id_registered(void) -{ - return test_bit(read_apic_id(), phys_cpu_present_map); -} - /* * Set up the logical destination ID when the APIC operates in logical * destination mode. --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -70,7 +70,6 @@ static struct apic apic_flat __ro_after_ .name =3D "flat", .probe =3D flat_probe, .acpi_madt_oem_check =3D flat_acpi_madt_oem_check, - .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, @@ -139,7 +138,6 @@ static struct apic apic_physflat __ro_af .name =3D "physical flat", .probe =3D physflat_probe, .acpi_madt_oem_check =3D physflat_acpi_madt_oem_check, - .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -61,8 +61,6 @@ void default_send_IPI_allbutself(int vec void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 -bool default_apic_id_registered(void); - #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -38,7 +38,6 @@ static struct apic apic_default __ro_aft =20 .name =3D "default", .probe =3D probe_default, - .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2816CC00528 for ; Mon, 7 Aug 2023 13:54:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234675AbjHGNyL (ORCPT ); Mon, 7 Aug 2023 09:54:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234483AbjHGNxW (ORCPT ); Mon, 7 Aug 2023 09:53:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABD9E1711 for ; Mon, 7 Aug 2023 06:53:09 -0700 (PDT) Message-ID: <20230807135027.588808550@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IrlwyG1bzr7R52EqtilduQSm4PCjRDmOOCFPZIpHccM=; b=CuctpTbiRz/wJD5qxPJyWEZjXhE/AiIO/3JAvaUWdaR3Zx4gwPXvjNJhJ3LX6bS1X4fnBo pybUVpXMVOESSDu4FTLEv+0QgK/dCVfNtpcbzmoE4/wfTaC/s4c0KFrh+Coc2x9mudfRWI sqtOpLTaUajy8wIfNRvC7lKMRjpjKBzKldxJZKTsO76l4kVjWd87hzIDW70zvKkQ8i68lN IIVxYZRX8khwnqjWXGrjkMdJeooZWXZlAkCQZSJtquJ5dSyWYyONxblEexDyGlD009I81K EG45MK9MOpMQYOwaDfW33o5713X38mChqkh9qqMP1VzaqT+T4J/QsjIa0myqgA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IrlwyG1bzr7R52EqtilduQSm4PCjRDmOOCFPZIpHccM=; b=nzYIVBJXi35UKPVRUwOmLmZ4kSEOI3s1SERwuMB5niQ8qYLIBLW5qSWLjh8wg8VKjIRX4b f1X9qRA09Xsiw4DA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 22/53] x86/apic: Use a proper define for invalid ACPI CPU ID References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:07 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ACPI ID for CPUs is preset with U32_MAX which is completely non obvious. Use a proper define for it. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/kernel/apic/apic.c | 2 +- arch/x86/xen/enlighten_hvm.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -46,6 +46,8 @@ extern void x86_32_probe_apic(void); static inline void x86_32_probe_apic(void) { } #endif =20 +#define CPU_ACPIID_INVALID U32_MAX + #ifdef CONFIG_X86_LOCAL_APIC =20 extern int apic_verbosity; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -111,7 +111,7 @@ static inline bool apic_accessible(void) * Map cpu index to physical APIC ID */ DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); =20 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -168,7 +168,7 @@ static int xen_cpu_up_prepare_hvm(unsign */ xen_uninit_lock_cpu(cpu); =20 - if (cpu_acpi_id(cpu) !=3D U32_MAX) + if (cpu_acpi_id(cpu) !=3D CPU_ACPIID_INVALID) per_cpu(xen_vcpu_id, cpu) =3D cpu_acpi_id(cpu); else per_cpu(xen_vcpu_id, cpu) =3D cpu; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA833C001DB for ; Mon, 7 Aug 2023 13:54:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbjHGNyS (ORCPT ); Mon, 7 Aug 2023 09:54:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234513AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D7291724 for ; Mon, 7 Aug 2023 06:53:11 -0700 (PDT) Message-ID: <20230807135027.640774399@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416390; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gEhZQItEgYbVrFDRBJAD0RQQEUzfvs5vg3RCb3nTKps=; b=gI9afqNLKqN8rRWmcY8aiUriptc+lxJJ9MO3o4cNPjeqADsrGBk4ycNnw8wKVe7AJ+ajXt 2iRzkNTnd9KPi90Ro0ZVYuAeMYR7zFEb2YkA057Vgu3qyI1wweZsXhMoJULmlKJG+tnHjF BO+kpmcE0/9kF8EePik2Zv87Vx8IfpEScuboJ6Qi1zbqhqAKWbHvfZ662fNefWzVM3yNW+ JjZuUG+o8gnAZBDmuXpWKOVjTQhEV9aiAHDw2wyAXnirp1k0VSeuqyMn/YvksV4XOnxk3V UpSO0o2JhoSXzy8xzQNcyWboVuSVHhtniiMMFDJWSuqTNgaBoP8g7hfiOYWBHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416390; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gEhZQItEgYbVrFDRBJAD0RQQEUzfvs5vg3RCb3nTKps=; b=0ZhSjBb1mY7ZtLFtG8ub4Ntpeh/Bzya8cwOIHZVrb5/SOV9gWUGx6huUEHcXVGwfivmA0K vbs2UkCYkJYLdzDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 23/53] x86/cpu/topology: Move registration out of APIC code References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:09 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The APIC/CPU registration sits in the middle of the APIC code. In fact this is a topology evaluation function and has nothing to do with the inner workings of the local APIC. Move it out into a file which reflects what this is about. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 2=20 arch/x86/kernel/apic/apic.c | 185 ------------------------------------= ----- arch/x86/kernel/cpu/Makefile | 12 +- arch/x86/kernel/cpu/topology.c | 184 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 195 insertions(+), 188 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -171,6 +171,8 @@ extern bool apic_needs_pit(void); =20 extern void apic_send_IPI_allbutself(unsigned int vector); =20 +extern void topology_register_boot_apic(u32 apic_id); + #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } #define local_apic_timer_c2_ok 1 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -68,26 +68,12 @@ =20 #include "local.h" =20 -unsigned int num_processors; - -unsigned disabled_cpus; - /* Processor that is doing the boot up */ u32 boot_cpu_physical_apicid __ro_after_init =3D BAD_APICID; EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); =20 u8 boot_cpu_apic_version __ro_after_init; =20 -/* Bitmap of physically present CPUs. */ -DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); - -/* - * Processor to be disabled specified by kernel parameter - * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to - * avoid undefined behaviour caused by sending INIT from AP to BSP. - */ -static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; - /* * This variable controls which CPUs receive external NMIs. By default, * external NMIs are delivered only to the BSP. @@ -107,14 +93,6 @@ static inline bool apic_accessible(void) return x2apic_mode || apic_mmio_base; } =20 -/* - * Map cpu index to physical APIC ID - */ -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); - #ifdef CONFIG_X86_32 /* Local APIC was disabled by the BIOS and enabled by the kernel */ static int enabled_via_apicbase __ro_after_init; @@ -1676,8 +1654,6 @@ void apic_ap_setup(void) end_local_APIC_setup(); } =20 -static __init void cpu_set_boot_apic(void); - static __init void apic_read_boot_cpu_id(bool x2apic) { /* @@ -1692,7 +1668,8 @@ static __init void apic_read_boot_cpu_id boot_cpu_physical_apicid =3D read_apic_id(); boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } - cpu_set_boot_apic(); + topology_register_boot_apic(boot_cpu_physical_apicid); + x86_32_probe_bigsmp_early(); } =20 #ifdef CONFIG_X86_X2APIC @@ -2291,155 +2268,6 @@ void disconnect_bsp_APIC(int virt_wire_s apic_write(APIC_LVT1, value); } =20 -/* - * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated - * contiguously, it equals to current allocated max logical CPU ID plus 1. - * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, - * so the maximum of nr_logical_cpuids is nr_cpu_ids. - * - * NOTE: Reserve 0 for BSP. - */ -static int nr_logical_cpuids =3D 1; - -/* - * Used to store mapping between logical CPU IDs and APIC IDs. - */ -u32 cpuid_to_apicid[] =3D { [0 ... NR_CPUS - 1] =3D BAD_APICID, }; - -bool arch_match_cpu_phys_id(int cpu, u64 phys_id) -{ - return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; -} - -#ifdef CONFIG_SMP -static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) -{ - /* Isolate the SMT bit(s) in the APICID and check for 0 */ - u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; - - if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) - cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); -} - -/* - * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid - * during early boot. Initialize the primary thread mask before SMP - * bringup. - */ -static int __init smp_init_primary_thread_mask(void) -{ - unsigned int cpu; - - /* - * XEN/PV provides either none or useless topology information. - * Pretend that all vCPUs are primary threads. - */ - if (xen_pv_domain()) { - cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); - return 0; - } - - for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) - cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); - return 0; -} -early_initcall(smp_init_primary_thread_mask); -#else -static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } -#endif - -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(int apicid) -{ - int i; - - /* - * cpuid <-> apicid mapping is persistent, so when a cpu is up, - * check if the kernel has allocated a cpuid for it. - */ - for (i =3D 0; i < nr_logical_cpuids; i++) { - if (cpuid_to_apicid[i] =3D=3D apicid) - return i; - } - - /* Allocate a new cpuid. */ - if (nr_logical_cpuids >=3D nr_cpu_ids) { - WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " - "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apicid); - return -EINVAL; - } - - cpuid_to_apicid[nr_logical_cpuids] =3D apicid; - return nr_logical_cpuids++; -} - -static void cpu_update_apic(int cpu, u32 apicid) -{ -#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; -#endif - set_cpu_possible(cpu, true); - set_bit(apicid, phys_cpu_present_map); - set_cpu_present(cpu, true); - num_processors++; - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apicid); -} - -static __init void cpu_set_boot_apic(void) -{ - cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; - cpu_update_apic(0, boot_cpu_physical_apicid); - x86_32_probe_bigsmp_early(); -} - -int generic_processor_info(int apicid) -{ - int cpu, max =3D nr_cpu_ids; - - /* The boot CPU must be set before MADT/MPTABLE parsing happens */ - if (cpuid_to_apicid[0] =3D=3D BAD_APICID) - panic("Boot CPU APIC not registered yet\n"); - - if (apicid =3D=3D boot_cpu_physical_apicid) - return 0; - - if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -EINVAL; - } - - cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - - cpu_update_apic(cpu, apicid); - return cpu; -} - - void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { @@ -2828,15 +2656,6 @@ static int __init lapic_insert_resource( */ late_initcall(lapic_insert_resource); =20 -static int __init apic_set_disabled_cpu_apicid(char *arg) -{ - if (!arg || !get_option(&arg, &disabled_cpu_apicid)) - return -EINVAL; - - return 0; -} -early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); - static int __init apic_set_extnmi(char *arg) { if (!arg) --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -26,14 +26,16 @@ obj-y +=3D bugs.o obj-y +=3D aperfmperf.o obj-y +=3D cpuid-deps.o obj-y +=3D umwait.o +obj-y +=3D capflags.o powerflags.o =20 -obj-$(CONFIG_PROC_FS) +=3D proc.o -obj-y +=3D capflags.o powerflags.o +obj-$(CONFIG_X86_LOCAL_APIC) +=3D topology.o =20 -obj-$(CONFIG_IA32_FEAT_CTL) +=3D feat_ctl.o +obj-$(CONFIG_PROC_FS) +=3D proc.o + +obj-$(CONFIG_IA32_FEAT_CTL) +=3D feat_ctl.o ifdef CONFIG_CPU_SUP_INTEL -obj-y +=3D intel.o intel_pconfig.o tsx.o -obj-$(CONFIG_PM) +=3D intel_epb.o +obj-y +=3D intel.o intel_pconfig.o tsx.o +obj-$(CONFIG_PM) +=3D intel_epb.o endif obj-$(CONFIG_CPU_SUP_AMD) +=3D amd.o obj-$(CONFIG_CPU_SUP_HYGON) +=3D hygon.o --- /dev/null +++ b/arch/x86/kernel/cpu/topology.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +#include + +#include +#include +#include + +/* + * Map cpu index to physical APIC ID + */ +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); +EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); +EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); + +/* Bitmap of physically present CPUs. */ +DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC) __read_mostly; + +/* Used for CPU number allocation and parallel CPU bringup */ +u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; + +/* + * Processor to be disabled specified by kernel parameter + * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to + * avoid undefined behaviour caused by sending INIT from AP to BSP. + */ +static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; + +unsigned int num_processors; +unsigned disabled_cpus; + +/* + * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated + * contiguously, it equals to current allocated max logical CPU ID plus 1. + * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, + * so the maximum of nr_logical_cpuids is nr_cpu_ids. + * + * NOTE: Reserve 0 for BSP. + */ +static int nr_logical_cpuids =3D 1; + +bool arch_match_cpu_phys_id(int cpu, u64 phys_id) +{ + return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; +} + +#ifdef CONFIG_SMP +static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) +{ + /* Isolate the SMT bit(s) in the APICID and check for 0 */ + u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; + + if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) + cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); +} + +/* + * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid + * during early boot. Initialize the primary thread mask before SMP + * bringup. + */ +static int __init smp_init_primary_thread_mask(void) +{ + unsigned int cpu; + + /* + * XEN/PV provides either none or useless topology information. + * Pretend that all vCPUs are primary threads. + */ + if (xen_pv_domain()) { + cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); + return 0; + } + + for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) + cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); + return 0; +} +early_initcall(smp_init_primary_thread_mask); +#else +static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } +#endif + +/* + * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds + * and cpuid_to_apicid[] synchronized. + */ +static int allocate_logical_cpuid(int apicid) +{ + int i; + + /* + * cpuid <-> apicid mapping is persistent, so when a cpu is up, + * check if the kernel has allocated a cpuid for it. + */ + for (i =3D 0; i < nr_logical_cpuids; i++) { + if (cpuid_to_apicid[i] =3D=3D apicid) + return i; + } + + /* Allocate a new cpuid. */ + if (nr_logical_cpuids >=3D nr_cpu_ids) { + WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " + "Processor %d/0x%x and the rest are ignored.\n", + nr_cpu_ids, nr_logical_cpuids, apicid); + return -EINVAL; + } + + cpuid_to_apicid[nr_logical_cpuids] =3D apicid; + return nr_logical_cpuids++; +} + +static void cpu_update_apic(int cpu, u32 apicid) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; +#endif + set_cpu_possible(cpu, true); + set_bit(apicid, phys_cpu_present_map); + set_cpu_present(cpu, true); + num_processors++; + + if (system_state !=3D SYSTEM_BOOTING) + cpu_mark_primary_thread(cpu, apicid); +} + +void __init topology_register_boot_apic(u32 apic_id) +{ + cpuid_to_apicid[0] =3D apic_id; + cpu_update_apic(0, apic_id); +} + +int generic_processor_info(int apicid) +{ + int cpu, max =3D nr_cpu_ids; + + /* The boot CPU must be set before MADT/MPTABLE parsing happens */ + if (cpuid_to_apicid[0] =3D=3D BAD_APICID) + panic("Boot CPU APIC not registered yet\n"); + + if (apicid =3D=3D boot_cpu_physical_apicid) + return 0; + + if (disabled_cpu_apicid =3D=3D apicid) { + int thiscpu =3D num_processors + disabled_cpus; + + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); + + disabled_cpus++; + return -ENODEV; + } + + if (num_processors >=3D nr_cpu_ids) { + int thiscpu =3D max + disabled_cpus; + + pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " + "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); + + disabled_cpus++; + return -EINVAL; + } + + cpu =3D allocate_logical_cpuid(apicid); + if (cpu < 0) { + disabled_cpus++; + return -EINVAL; + } + + cpu_update_apic(cpu, apicid); + return cpu; +} + +static int __init apic_set_disabled_cpu_apicid(char *arg) +{ + if (!arg || !get_option(&arg, &disabled_cpu_apicid)) + return -EINVAL; + + return 0; +} +early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A808C00528 for ; Mon, 7 Aug 2023 13:54:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232086AbjHGNyP (ORCPT ); Mon, 7 Aug 2023 09:54:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234510AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DED4AE79 for ; Mon, 7 Aug 2023 06:53:12 -0700 (PDT) Message-ID: <20230807135027.692922999@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416391; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IqAKXGpiL7mvQVclSEowAMUpcYUdp0UmfO0umAl+WIU=; b=xvqD84j5Lo6sV4+Tev8QdMaXG0YVemHJ0oscuIqKtuxRAs9qkCJldpu6sl72q+/53WEhQ7 zo+RW7FYAs6nbmz8Lbe6KiIg0PlpcM4o1HATGBL/4UrsqSSjVOC7eQSZjD6YE2cCbOXn4l No/snYuXiWNHT8T0wpotpYRpenw7oCEZ4v+bO6ucc/xqsLLvuuKM37+/3xXZO6/PxECiRv pxTwTQV4csd1X/CjlJqVdePVWx13gx1lD3aB+Xfmbakl+WWe1hovb0yPhnxwvTt0o8iRqS kjlel56JzvCxquTXXu4NeyYab+2Kzg4Rx40ChrXH9oLxrzHlmAwXQIRT/Q3NRA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416391; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IqAKXGpiL7mvQVclSEowAMUpcYUdp0UmfO0umAl+WIU=; b=b3w1iUWC31HmC3cDjgcLS5OUz9y5vPc8OerZFlz8Qk3jROwpXKhvJrMe2VKrflYuoWBfSN mkwrldqL2VuQ+5Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 24/53] x86/cpu/topology: Provide separate APIC registration functions References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:11 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" generic_processor_info() aside of being a complete misnomer is used for both early boot registration and ACPI CPU hotplug. While it's arguable that this can share some code, it results in code which is hard to understand and kept around post init for no real reason. Also the call sites do lots of manual fiddling in topology related variables instead of having proper interfaces for the purpose which handle the topology internals correctly. Provide topology_register_apic(), topology_hotplug_apic() and topology_hot_unplug_apic() which have the extra magic of the call sites incorporated and for now are wrappers around generic_processor_info(). Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 3=20 arch/x86/kernel/cpu/topology.c | 113 ++++++++++++++++++++++++++++++------ 2 files changed, 98 insertions(+), 18 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -171,7 +171,10 @@ extern bool apic_needs_pit(void); =20 extern void apic_send_IPI_allbutself(unsigned int vector); =20 +extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); extern void topology_register_boot_apic(u32 apic_id); +extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); +extern void topology_hotunplug_apic(unsigned int cpu); =20 #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -79,32 +79,38 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(int apicid) +static int topo_lookup_cpuid(u32 apic_id) { int i; =20 - /* - * cpuid <-> apicid mapping is persistent, so when a cpu is up, - * check if the kernel has allocated a cpuid for it. - */ + /* CPU# to APICID mapping is persistent once it is established */ for (i =3D 0; i < nr_logical_cpuids; i++) { - if (cpuid_to_apicid[i] =3D=3D apicid) + if (cpuid_to_apicid[i] =3D=3D apic_id) return i; } + return -ENODEV; +} + +/* + * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds + * and cpuid_to_apicid[] synchronized. + */ +static int allocate_logical_cpuid(u32 apic_id) +{ + int cpu =3D topo_lookup_cpuid(apic_id); + + if (cpu >=3D 0) + return cpu; =20 /* Allocate a new cpuid. */ if (nr_logical_cpuids >=3D nr_cpu_ids) { WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apicid); + nr_cpu_ids, nr_logical_cpuids, apic_id); return -EINVAL; } =20 - cpuid_to_apicid[nr_logical_cpuids] =3D apicid; + cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; return nr_logical_cpuids++; } =20 @@ -122,12 +128,6 @@ static void cpu_update_apic(int cpu, u32 cpu_mark_primary_thread(cpu, apicid); } =20 -void __init topology_register_boot_apic(u32 apic_id) -{ - cpuid_to_apicid[0] =3D apic_id; - cpu_update_apic(0, apic_id); -} - int generic_processor_info(int apicid) { int cpu, max =3D nr_cpu_ids; @@ -169,6 +169,83 @@ int generic_processor_info(int apicid) return cpu; } =20 +/** + * topology_register_apic - Register an APIC in early topology maps + * @apic_id: The APIC ID to set up + * @acpi_id: The ACPI ID associated to the APIC + * @present: True if the corresponding CPU is present + */ +void __init topology_register_apic(u32 apic_id, u32 acpi_id, bool present) +{ + int cpu; + + if (apic_id >=3D MAX_LOCAL_APIC) { + pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); + return; + } + + if (!present) { + disabled_cpus++; + return; + } + + cpu =3D generic_processor_info(apic_id); + if (cpu >=3D 0) + early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; +} + +/** + * topology_register_boot_apic - Register the boot CPU APIC + * @apic_id: The APIC ID to set up + * + * Separate so CPU #0 can be assigned + */ +void __init topology_register_boot_apic(u32 apic_id) +{ + cpuid_to_apicid[0] =3D apic_id; + cpu_update_apic(0, apic_id); +} + +#ifdef CONFIG_ACPI_HOTPLUG_CPU +/** + * topology_hotplug_apic - Handle a physical hotplugged APIC after boot + * @apic_id: The APIC ID to set up + * @acpi_id: The ACPI ID associated to the APIC + */ +int topology_hotplug_apic(u32 apic_id, u32 acpi_id) +{ + int cpu; + + if (apic_id >=3D MAX_LOCAL_APIC) + return -EINVAL; + + cpu =3D topo_lookup_cpuid(apic_id); + if (cpu < 0) { + cpu =3D generic_processor_info(apic_id); + if (cpu >=3D 0) + per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + } + return cpu; +} + +/** + * topology_hotunplug_apic - Remove a physical hotplugged APIC after boot + * @cpu: The CPU number for which the APIC ID is removed + */ +void topology_hotunplug_apic(unsigned int cpu) +{ + u32 apic_id =3D cpuid_to_apicid[cpu]; + + if (apic_id =3D=3D BAD_APICID) + return; + + per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; + clear_bit(apic_id, phys_cpu_present_map); + set_cpu_present(cpu, false); + num_processors--; +} +#endif + static int __init apic_set_disabled_cpu_apicid(char *arg) { if (!arg || !get_option(&arg, &disabled_cpu_apicid)) From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42AD5C001DB for ; Mon, 7 Aug 2023 13:54:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbjHGNyX (ORCPT ); Mon, 7 Aug 2023 09:54:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234517AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63BB7172B for ; Mon, 7 Aug 2023 06:53:14 -0700 (PDT) Message-ID: <20230807135027.744726431@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nG+YvBEV0fbKDlHuwzPcSCnQUfwAu0UNTIPK/22bMkQ=; b=TIA7UnzXh5zAohfK/vOwilNrmoWIvemhbXWA/KYSdF9V3RTTmCXVv3M2fYDDQPfR8Y+M8s CqQduP/tMOQyyQPqjZn4Nq24EqGkLMQTq7c5UTTGz2mXr4IUwGie5TOxCexoZg4xQvXbKM 1/JLm8buKdY0VQnCQJSgVr5z+UwhyqF1Q6+IN+da2qn0BCZDXB7ltScy4M5fe6FV5PqgUR p+8/k6S+uq1ep4AupOSfVXg+vLSVUOMVfa0MgH2jV55MtYIWaVxYr9LnNmDag7Pg3qjKoU h7XEcITOB6vQA0Ty/W8qgWP4nr5X6SI5C85xOl3ZZhXOK1/FdQTg1hh+pKOixQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nG+YvBEV0fbKDlHuwzPcSCnQUfwAu0UNTIPK/22bMkQ=; b=LP35Q1XLE/S/6GG5Syf7Rfdt6aZGERw1YkhtUDdwa4aHeUmoSwiFYSDb3Q7noWmzA8n9MF UUL8rxvt1EJFPWBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 25/53] x86/acpi: Use new APIC registration functions References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:12 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the new topology registration functions and make the early boot code path __init. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/acpi/boot.c | 44 +++++++--------------------------------= ----- 1 file changed, 7 insertions(+), 37 deletions(-) --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -159,33 +159,9 @@ static int __init acpi_parse_madt(struct return 0; } =20 -/** - * acpi_register_lapic - register a local apic and generates a logic cpu n= umber - * @id: local apic id to register - * @acpiid: ACPI id to register - * @enabled: this cpu is enabled or not - * - * Returns the logic cpu number which maps to the local apic - */ -static int acpi_register_lapic(int id, u32 acpiid, u8 enabled) +static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) { - int cpu; - - if (id >=3D MAX_LOCAL_APIC) { - pr_info("skipped apicid that is too big\n"); - return -EINVAL; - } - - if (!enabled) { - ++disabled_cpus; - return -EINVAL; - } - - cpu =3D generic_processor_info(id); - if (cpu >=3D 0) - early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpiid; - - return cpu; + topology_register_apic(apic_id, acpi_id, present); } =20 static bool __init acpi_is_processor_usable(u32 lapic_flags) @@ -827,12 +803,10 @@ static int acpi_map_cpu2node(acpi_handle return 0; } =20 -int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 acpi_id, - int *pcpu) +int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 acpi_id, int= *pcpu) { - int cpu; + int cpu =3D topology_hotplug_apic(physid, acpi_id); =20 - cpu =3D acpi_register_lapic(physid, acpi_id, ACPI_MADT_ENABLED); if (cpu < 0) { pr_info("Unable to map lapic to logical cpu number\n"); return cpu; @@ -851,15 +825,11 @@ int acpi_unmap_cpu(int cpu) #ifdef CONFIG_ACPI_NUMA set_apicid_to_node(per_cpu(x86_cpu_to_apicid, cpu), NUMA_NO_NODE); #endif - - per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; - set_cpu_present(cpu, false); - num_processors--; - - return (0); + topology_hotunplug_apic(cpu); + return 0; } EXPORT_SYMBOL(acpi_unmap_cpu); -#endif /* CONFIG_ACPI_HOTPLUG_CPU */ +#endif /* CONFIG_ACPI_HOTPLUG_CPU */ =20 int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base) { From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B675BC00528 for ; Mon, 7 Aug 2023 13:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234513AbjHGNyU (ORCPT ); Mon, 7 Aug 2023 09:54:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234514AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8AF01730 for ; Mon, 7 Aug 2023 06:53:15 -0700 (PDT) Message-ID: <20230807135027.796685292@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416394; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8e5qBi4unbK4L9kV01zqCd39sEuWF2ZwMPDC4Zm+oQs=; b=Is6BpuQgQgj9xzGXJxqihTeaMeVw8uEILDbIHbeElhwkCzwWmpo/8LYQofgt/TOawXtJ0G EeoUXs4J5UD7JuuSjkeK0lc/58+35RjlW4XREky0zjiTFe/JcXU7hWyCUTehB+3NRBrm7O 89Jvaxxv3VcqbDBLVrOO522hqfCTWIKErctq39DniQPTgLVcIiRXQfWl47tu2bSPEPU+GC UCDlQsOU2Z9MRAV4VxvVSxoTH2Lyf9hesO64BvEovW33KanWUSfb7BgMqrsK6DKciMnDF+ qqzA7pyRUSyo5Y8vv9amX4X4J/IK83+UvzntsajQNyyC/vi+VAtzHk3h+ZorPQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416394; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8e5qBi4unbK4L9kV01zqCd39sEuWF2ZwMPDC4Zm+oQs=; b=ey+nGSKuhNoQUjZQeNNDsLjkZN7xbQMRrS8kscyyAcKgy4BRjwR4DF4xkX8z0+Joc7kL4u ab7Nt8aToFkDpbDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 26/53] x86/jailhouse: Use new APIC registration function References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:14 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/jailhouse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -102,7 +102,7 @@ static void __init jailhouse_parse_smp_c register_lapic_address(0xfee00000); =20 for (cpu =3D 0; cpu < setup_data.v1.num_cpus; cpu++) - generic_processor_info(setup_data.v1.cpu_ids[cpu]); + topology_register_apic(setup_data.v1.cpu_ids[cpu], CPU_ACPIID_INVALID, t= rue); =20 smp_found_config =3D 1; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE22C00528 for ; Mon, 7 Aug 2023 13:54:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232882AbjHGNy1 (ORCPT ); Mon, 7 Aug 2023 09:54:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234519AbjHGNxY (ORCPT ); Mon, 7 Aug 2023 09:53:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92997199B for ; Mon, 7 Aug 2023 06:53:17 -0700 (PDT) Message-ID: <20230807135027.848546733@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416396; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JDi87pLR5a8qAf6RSOGJA9lNdy/Pfs6qvOHQvJ93Uhk=; b=YHMlPjfwlSWB+MqCo5PLl5iYmiuKmuIwNBeJ25V3URVpA/YrgQ9jmn0bHqcND5N8eUp/Qu 7JiFexoliy01Ti+FUZhtsT+dIXw9KhjS+/UOtm3JKx278JzpNtCWDPbjQjIz491iB4Wn63 kYcKQX7Gjr8/xgVxqQ3oWJVWUGHJKP40dpoRBzsKtn8vejklPRLbLwH38iABGUqt0ex0Lx 8TGIWDHMoS3g7iuEQyoNW0wK5NYum9Too9rc9I4c/XBNIfmFgRTXsvBlSEF4BEKhbRfNkj eNEV5kGqm0yTTSzv9amGBda1znVVZp5RJUoGM21X6P1enICNujy5DazraZEYiA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416396; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JDi87pLR5a8qAf6RSOGJA9lNdy/Pfs6qvOHQvJ93Uhk=; b=LrQJoHRjAJkn+L3kxPGDC2//khzseVUhnrqk+FQYBcL2T+jocUme7FbolPq83dMgmSyP0S EYw2LuJ0IIa0gpDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 27/53] x86/of: Use new APIC registration functions References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:15 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/devicetree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -136,7 +136,7 @@ static void __init dtb_cpu_setup(void) pr_warn("%pOF: missing local APIC ID\n", dn); continue; } - generic_processor_info(apic_id); + topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); } } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B0BAC41513 for ; Mon, 7 Aug 2023 13:54:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234548AbjHGNyb (ORCPT ); Mon, 7 Aug 2023 09:54:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234536AbjHGNx1 (ORCPT ); Mon, 7 Aug 2023 09:53:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3419E92 for ; Mon, 7 Aug 2023 06:53:19 -0700 (PDT) Message-ID: <20230807135027.900644907@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416397; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Fs46OBe57ed0poZNxJMiXrzfary3Rr7oc4qtsgbrZ88=; b=E3PhyayB0rz1Jvqgj8eCacG0GKqZgtdcsSRnrUvhwGg5GrFidqGHXLk42wNvc9rt7DQPkm woXfN+3t5KyGhNa5uQZ490XFzyTQ5xdC7F5KEAtIEC7tYhBo0WQwrydCtE4PcpRZ/Bcq56 SC/ksjaH4I+GQ7goNa9qjiVnP1ebO1j2B1M22963EZm6WsX4zbjDfj/07NuLGLHZH068h7 qqyw5EhQMdeS/e5DU1Q16L0tUFhk+tS6EL1JinTPXgIYj+J1gh0wKNyLj7029/LDRyRN1M vCPhBLdQqAfX+Ysmx1o4lk4XwLDDVjmY04YQjvy3mebD46SaYoo8HWd+E/YwTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416397; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Fs46OBe57ed0poZNxJMiXrzfary3Rr7oc4qtsgbrZ88=; b=8WKUlQ12W3KaxWZMVFzvM843Twl4ANWZZTcDYhUYDA7sM6BB/6G1iGABZh8ySwfVb/yQjI DKO+q5q6M6uUKfBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 28/53] x86/mpparse: Use new APIC registration function References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:17 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Aside of switching over to the new interface, record the number of registered CPUs locally, which allows to make num_processors and disabled_cpus confined to the topology code. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/mpspec.h | 2 -- arch/x86/kernel/cpu/topology.c | 2 +- arch/x86/kernel/mpparse.c | 21 ++++++++++----------- 3 files changed, 11 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -61,8 +61,6 @@ static inline void e820__memblock_alloc_ #define mpparse_parse_smp_config x86_init_noop #endif =20 -int generic_processor_info(int apicid); - extern DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 static inline void reset_phys_cpu_present_map(u32 apicid) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -128,7 +128,7 @@ static void cpu_update_apic(int cpu, u32 cpu_mark_primary_thread(cpu, apicid); } =20 -int generic_processor_info(int apicid) +static int generic_processor_info(int apicid) { int cpu, max =3D nr_cpu_ids; =20 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -36,6 +36,8 @@ * Checksum an MP configuration block. */ =20 +static unsigned int num_procs __initdata; + static int __init mpf_checksum(unsigned char *mp, int len) { int sum =3D 0; @@ -48,21 +50,18 @@ static int __init mpf_checksum(unsigned =20 static void __init MP_processor_info(struct mpc_cpu *m) { - int apicid; char *bootup_cpu =3D ""; =20 - if (!(m->cpuflag & CPU_ENABLED)) { - disabled_cpus++; - return; - } + topology_register_apic(m->apicid, CPU_ACPIID_INVALID, m->cpuflag & CPU_EN= ABLED); =20 - apicid =3D m->apicid; + if (!(m->cpuflag & CPU_ENABLED)) + return; =20 if (m->cpuflag & CPU_BOOTPROCESSOR) bootup_cpu =3D " (Bootup-CPU)"; =20 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); - generic_processor_info(apicid); + num_procs++; } =20 #ifdef CONFIG_X86_IO_APIC @@ -239,9 +238,9 @@ static int __init smp_read_mpc(struct mp } } =20 - if (!num_processors) + if (!num_procs && !acpi_lapic) pr_err("MPTABLE: no processors registered!\n"); - return num_processors; + return num_procs || acpi_lapic; } =20 #ifdef CONFIG_X86_IO_APIC @@ -532,8 +531,8 @@ static __init void mpparse_get_smp_confi } else BUG(); =20 - if (!early) - pr_info("Processors: %d\n", num_processors); + if (!early && !acpi_lapic) + pr_info("Processors: %d\n", num_procs); /* * Only use the first configuration found. */ From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7397EC04A94 for ; Mon, 7 Aug 2023 13:54:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234593AbjHGNyd (ORCPT ); Mon, 7 Aug 2023 09:54:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234542AbjHGNx2 (ORCPT ); Mon, 7 Aug 2023 09:53:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C34FA19AF for ; Mon, 7 Aug 2023 06:53:20 -0700 (PDT) Message-ID: <20230807135027.952716842@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416399; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vSSLVehnXeqS3aVj1Xv9tp4/rOAt2y9JlTCXEhijejo=; b=3JHKTqT/JB1OCS3rE+TjyX4ojVXKcl3pi5D+1q0Hxzz2cHQn6xiu8bYejUmq6MWVHzVJnK WDnG2Px15NK3s+Tda5aCc069U/CtWD0vtJ61ODL1WNuvCCvbN2jziGxilWWhLrpSkhNF4t bez/EVljFOELvX7KfsCnTs55VfvsY5QO/W+F31/j77FPWa7p8qc0r3PEut5L0LJIZbUNit QiJii7bO65YWFV20+w3KglFpULbf+h9uYPpnJ/RGm6UdAecKn2EzhT/NLfWkvzsQY+Vd7D iB/ylLGEIdxUw2GkmHeUI/C450YN0n9FxKzqHIoYT7J/o+CsBM8u6CGRrZ1aUg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416399; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vSSLVehnXeqS3aVj1Xv9tp4/rOAt2y9JlTCXEhijejo=; b=HpF6jWC3yZXhuGINlovj1jL1sdISUapsfIv1P+MYPN22W8hGyIXv8FqV6QkUR39npPxKxd 3FAC6hYBCT90JECw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 29/53] x86/acpi: Dont invoke topology_register_apic() for XEN PV References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:18 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MADT table for XEN/PV dom0 is not really useful and registering the APICs is momentarily a pointless exercise because XENPV does not use an APIC at all. It overrides the x86_init.mpparse.parse_smp_config() callback, resets num_processors and counts how many of them are provided by the hypervisor. This is in the way of cleaning up the APIC registration. Prevent MADT registration for XEN/PV temporarily until the rework is completed and XEN/PV can use the MADT again. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/acpi/boot.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -23,6 +23,8 @@ #include #include =20 +#include + #include #include #include @@ -161,7 +163,8 @@ static int __init acpi_parse_madt(struct =20 static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) { - topology_register_apic(apic_id, acpi_id, present); + if (!xen_pv_domain()) + topology_register_apic(apic_id, acpi_id, present); } =20 static bool __init acpi_is_processor_usable(u32 lapic_flags) @@ -1070,7 +1073,8 @@ static int __init early_acpi_parse_madt_ return count; } =20 - register_lapic_address(acpi_lapic_addr); + if (!xen_pv_domain()) + register_lapic_address(acpi_lapic_addr); =20 return count; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEB57C04A6A for ; Mon, 7 Aug 2023 13:54:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232231AbjHGNyg (ORCPT ); Mon, 7 Aug 2023 09:54:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234552AbjHGNx2 (ORCPT ); Mon, 7 Aug 2023 09:53:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B5E210D9 for ; Mon, 7 Aug 2023 06:53:22 -0700 (PDT) Message-ID: <20230807135028.004788526@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416401; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SKlzH88G4hUFDWBSbGuVUg+96Wfddo4akvXYLyLOQ0U=; b=vrJ4kiRElUPDhd5ikOKv+S14H4YOQL8Bp8OblgGZVQMv3oy1scK69+GIg1Cd0QmFtSkBe/ NhyxK6A2SLwbZ6O1bGmvjMKjcoV4pqXkY0ChqTjKARMu2S/1sp2TXquw8zpIbT4dE6BvvK 2okS/+bAHAHxo7JSmFdLqS+g9nl55jYhaJdN71Qg4pHuQy0fGlBweyDCQCidaWGkH9pbq8 IXUrHy8AhByBSJgX5cPfJtz0XflZYcyFYFE4TYa2H9t6x00swfYPNU6m+u5ZDft/CT8Xui c9zkphgAlQBCmXFtfYBx5Be86huRP+ifA45K3+lCKAz/lf5+piIDM0BGla9pig== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416401; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SKlzH88G4hUFDWBSbGuVUg+96Wfddo4akvXYLyLOQ0U=; b=vGkLYQFg9IyCb4CuMg3u0ak1In3y9Aw8zkFF315GdSQ+L2R/cmHuKyVVCQTOg2aGZXPirl hUVUl5QtH1GZHdCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 30/53] x86/xen/smp_pv: Register fake APICs References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:20 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" XENPV does not use the APIC. It's just piggy packing on the infrastructure and fiddles with global variables as it sees fit. These global variables are going away, so let XENPV register pseudo APIC IDs to keep the accounting correct and keep up the illusion that XEN/PV is something sane. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/xen/smp_pv.c | 35 +++++++++-------------------------- 1 file changed, 9 insertions(+), 26 deletions(-) --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -29,6 +29,7 @@ #include #include #include +#include #include =20 #include @@ -150,34 +151,16 @@ int xen_smp_intr_init_pv(unsigned int cp =20 static void __init xen_pv_smp_config(void) { - int i, rc; - unsigned int subtract =3D 0; + u32 apicid =3D 0; + int i; =20 - num_processors =3D 0; - disabled_cpus =3D 0; - for (i =3D 0; i < nr_cpu_ids; i++) { - rc =3D HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL); - if (rc >=3D 0) { - num_processors++; - set_cpu_possible(i, true); - } else { - set_cpu_possible(i, false); - set_cpu_present(i, false); - subtract++; - } + topology_register_boot_apic(apicid++); + + for (i =3D 1; i < nr_cpu_ids; i++) { + if (HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL) < 0) + break; + topology_register_apic(apicid++, CPU_ACPIID_INVALID, true); } -#ifdef CONFIG_HOTPLUG_CPU - /* This is akin to using 'nr_cpus' on the Linux command line. - * Which is OK as when we use 'dom0_max_vcpus=3DX' we can only - * have up to X, while nr_cpu_ids is greater than X. This - * normally is not a problem, except when CPU hotplugging - * is involved and then there might be more than X CPUs - * in the guest - which will not work as there is no - * hypercall to expand the max number of VCPUs an already - * running guest has. So cap it up to X. */ - if (subtract) - set_nr_cpu_ids(nr_cpu_ids - subtract); -#endif /* Pretend to be a proper enumerated system */ smp_found_config =3D 1; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C42C001DB for ; Mon, 7 Aug 2023 13:54:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234568AbjHGNyj (ORCPT ); Mon, 7 Aug 2023 09:54:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234562AbjHGNx3 (ORCPT ); Mon, 7 Aug 2023 09:53:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00CD81990 for ; Mon, 7 Aug 2023 06:53:23 -0700 (PDT) Message-ID: <20230807135028.056840782@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5w2v+DcqfW564+MRIqjj5F099T2Sc0fxjubzsntwRSI=; b=Ye75ISXdxPbTL8S+YKYpZdMBn3JzPrxTwIfg+KtJEc/n820rVbvU189YqDKA2DreJllQ7r Or2LfuwWyD30SbikpTo5xBuwJ2zVOoWoOwBUfHdLlw+RZIyHQDE13/Q4bafGsGNgxGEN0b /oF4PMRuSHvrjxet/P74SFObjGC/i+AtuCXyf4z6RDc0oqEsU+izFurSjfV9eZPHG6cvci Iy66N8WGLO46cdWfkDO4HPy1zOCvDi8gjFFCan4g9b/RRuUhcSGiyL6ipkZRfuHVIQ0TU6 Ri7aP2/f8E/tAW2uxrEFjv6t/sK7clzTf6bHt3wHFoRRdJBNCgXbUhrh5/TknA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5w2v+DcqfW564+MRIqjj5F099T2Sc0fxjubzsntwRSI=; b=Q/565WFP7XeevqcsudIPUkk5Tgiw2my4lE/gwp5m71VBbidnJngr1JqNfin+IU3+ZnbcLN YhyRi4Q/UGP03tCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 31/53] x86/cpu/topology: Confine topology information References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:22 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that all external fiddling with num_processors and disabled_cpus is gone, move the last user prefill_possible_map() into the topology code too and remove the global visibility of these variables. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/smp.h | 3 - arch/x86/kernel/apic/apic.c | 1=20 arch/x86/kernel/cpu/topology.c | 76 +++++++++++++++++++++++++++++++++++- arch/x86/kernel/smpboot.c | 72 -------------------------------= --- 4 files changed, 74 insertions(+), 78 deletions(-) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -9,7 +9,6 @@ #include =20 extern int smp_num_siblings; -extern unsigned int num_processors; =20 DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); @@ -178,8 +177,6 @@ static inline struct cpumask *cpu_llc_sh } #endif /* CONFIG_SMP */ =20 -extern unsigned disabled_cpus; - #ifdef CONFIG_DEBUG_NMI_SELFTEST extern void nmi_selftest(void); #else --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2054,7 +2054,6 @@ void __init init_apic_mappings(void) pr_info("APIC: disable apic facility\n"); apic_disable(); } - num_processors =3D 1; } } =20 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -29,8 +29,8 @@ u32 cpuid_to_apicid[] __read_mostly =3D { */ static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; =20 -unsigned int num_processors; -unsigned disabled_cpus; +static unsigned int num_processors; +static unsigned int disabled_cpus; =20 /* * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated @@ -169,6 +169,71 @@ static int generic_processor_info(int ap return cpu; } =20 +static int __initdata setup_possible_cpus =3D -1; + +/* + * cpu_possible_mask should be static, it cannot change as cpu's + * are onlined, or offlined. The reason is per-cpu data-structures + * are allocated by some modules at init time, and don't expect to + * do this dynamically on cpu arrival/departure. + * cpu_present_mask on the other hand can change dynamically. + * In case when cpu_hotplug is not compiled, then we resort to current + * behaviour, which is cpu_possible =3D=3D cpu_present. + * - Ashok Raj + * + * Three ways to find out the number of additional hotplug CPUs: + * - If the BIOS specified disabled CPUs in ACPI/mptables use that. + * - The user can overwrite it with possible_cpus=3DNUM + * - Otherwise don't reserve additional CPUs. + * We do this because additional CPUs waste a lot of memory. + * -AK + */ +__init void prefill_possible_map(void) +{ + int i, possible; + + i =3D setup_max_cpus ?: 1; + if (setup_possible_cpus =3D=3D -1) { + possible =3D num_processors; +#ifdef CONFIG_HOTPLUG_CPU + if (setup_max_cpus) + possible +=3D disabled_cpus; +#else + if (possible > i) + possible =3D i; +#endif + } else + possible =3D setup_possible_cpus; + + total_cpus =3D max_t(int, possible, num_processors + disabled_cpus); + + /* nr_cpu_ids could be reduced via nr_cpus=3D */ + if (possible > nr_cpu_ids) { + pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", + possible, nr_cpu_ids); + possible =3D nr_cpu_ids; + } + +#ifdef CONFIG_HOTPLUG_CPU + if (!setup_max_cpus) +#endif + if (possible > i) { + pr_warn("%d Processors exceeds max_cpus limit of %u\n", + possible, setup_max_cpus); + possible =3D i; + } + + set_nr_cpu_ids(possible); + + pr_info("Allowing %d CPUs, %d hotplug CPUs\n", + possible, max_t(int, possible - num_processors, 0)); + + reset_cpu_possible_mask(); + + for (i =3D 0; i < possible; i++) + set_cpu_possible(i, true); +} + /** * topology_register_apic - Register an APIC in early topology maps * @apic_id: The APIC ID to set up @@ -246,6 +311,13 @@ void topology_hotunplug_apic(unsigned in } #endif =20 +static int __init _setup_possible_cpus(char *str) +{ + get_option(&str, &setup_possible_cpus); + return 0; +} +early_param("possible_cpus", _setup_possible_cpus); + static int __init apic_set_disabled_cpu_apicid(char *arg) { if (!arg || !get_option(&arg, &disabled_cpu_apicid)) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1327,78 +1327,6 @@ void __init native_smp_cpus_done(unsigne cache_aps_init(); } =20 -static int __initdata setup_possible_cpus =3D -1; -static int __init _setup_possible_cpus(char *str) -{ - get_option(&str, &setup_possible_cpus); - return 0; -} -early_param("possible_cpus", _setup_possible_cpus); - - -/* - * cpu_possible_mask should be static, it cannot change as cpu's - * are onlined, or offlined. The reason is per-cpu data-structures - * are allocated by some modules at init time, and don't expect to - * do this dynamically on cpu arrival/departure. - * cpu_present_mask on the other hand can change dynamically. - * In case when cpu_hotplug is not compiled, then we resort to current - * behaviour, which is cpu_possible =3D=3D cpu_present. - * - Ashok Raj - * - * Three ways to find out the number of additional hotplug CPUs: - * - If the BIOS specified disabled CPUs in ACPI/mptables use that. - * - The user can overwrite it with possible_cpus=3DNUM - * - Otherwise don't reserve additional CPUs. - * We do this because additional CPUs waste a lot of memory. - * -AK - */ -__init void prefill_possible_map(void) -{ - int i, possible; - - i =3D setup_max_cpus ?: 1; - if (setup_possible_cpus =3D=3D -1) { - possible =3D num_processors; -#ifdef CONFIG_HOTPLUG_CPU - if (setup_max_cpus) - possible +=3D disabled_cpus; -#else - if (possible > i) - possible =3D i; -#endif - } else - possible =3D setup_possible_cpus; - - total_cpus =3D max_t(int, possible, num_processors + disabled_cpus); - - /* nr_cpu_ids could be reduced via nr_cpus=3D */ - if (possible > nr_cpu_ids) { - pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", - possible, nr_cpu_ids); - possible =3D nr_cpu_ids; - } - -#ifdef CONFIG_HOTPLUG_CPU - if (!setup_max_cpus) -#endif - if (possible > i) { - pr_warn("%d Processors exceeds max_cpus limit of %u\n", - possible, setup_max_cpus); - possible =3D i; - } - - set_nr_cpu_ids(possible); - - pr_info("Allowing %d CPUs, %d hotplug CPUs\n", - possible, max_t(int, possible - num_processors, 0)); - - reset_cpu_possible_mask(); - - for (i =3D 0; i < possible; i++) - set_cpu_possible(i, true); -} - /* correctly size the local cpu masks */ void __init setup_cpu_local_masks(void) { From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCACAC001DB for ; Mon, 7 Aug 2023 13:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234610AbjHGNym (ORCPT ); Mon, 7 Aug 2023 09:54:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234537AbjHGNxc (ORCPT ); Mon, 7 Aug 2023 09:53:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83EC710DB for ; Mon, 7 Aug 2023 06:53:25 -0700 (PDT) Message-ID: <20230807135028.108994145@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O0KDW/sYTBHvu9oVtl0ZsFwyd9vxUlUG4W0MOjFJymI=; b=t3Hs084e3DoW05cKYoExyL5JqxGOQGeY6g/3Npa24OxX90/jIAWvoJp2VZtl/PzH60CFM4 AWoC3TVzfhyTs/Zl1hICLPVl4bwsA3H5hSed5QJUj3vioP5D3t3yaUfCwgOe306cCLDIX2 lwUy7n+PMbEIRaugop6WVeJyUN5CADV7tSscsT/eT5dMnVkt0iFJIq4qh0o7GG8YsjFv+q WYOPA+5tp5qsIwDJLc+SZMDSPGYLnXDWvgLZ/rWNbwFXnAcFkn1elRVd2MYvmIxXYHagfP OEc+/6TetFXtuGlhnMsIwQt3p5cCK+zxUiKKqMNpVqu9r/nD1UeZukD+9klNMA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O0KDW/sYTBHvu9oVtl0ZsFwyd9vxUlUG4W0MOjFJymI=; b=Kea/zMbKfuGzr86Q6qS2z1eetowyMK2zJNpkKtEP9NI/IRd7eQqlClwf5OTXTDdRM1Op7L 8tpp/zPts7qcGDCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 32/53] x86/cpu/topology: Simplify APIC registration References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:23 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Having the same check whether the number of assigned CPUs has reached the nr_cpu_ids limit twice in the same code path is pointless. Repeating the information that CPUs are ignored over and over is also pointless noise. Remove the redundant check and reduce the noise by using a pr_warn_once(). Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -102,14 +102,6 @@ static int allocate_logical_cpuid(u32 ap if (cpu >=3D 0) return cpu; =20 - /* Allocate a new cpuid. */ - if (nr_logical_cpuids >=3D nr_cpu_ids) { - WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " - "Processor %d/0x%x and the rest are ignored.\n", - nr_cpu_ids, nr_logical_cpuids, apic_id); - return -EINVAL; - } - cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; return nr_logical_cpuids++; } @@ -130,7 +122,7 @@ static void cpu_update_apic(int cpu, u32 =20 static int generic_processor_info(int apicid) { - int cpu, max =3D nr_cpu_ids; + int cpu; =20 /* The boot CPU must be set before MADT/MPTABLE parsing happens */ if (cpuid_to_apicid[0] =3D=3D BAD_APICID) @@ -150,21 +142,12 @@ static int generic_processor_info(int ap } =20 if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - + pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); disabled_cpus++; - return -EINVAL; + return -ENOSPC; } =20 cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - cpu_update_apic(cpu, apicid); return cpu; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A8AC001DB for ; Mon, 7 Aug 2023 13:54:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234528AbjHGNyq (ORCPT ); Mon, 7 Aug 2023 09:54:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234589AbjHGNxe (ORCPT ); Mon, 7 Aug 2023 09:53:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F57919B5 for ; Mon, 7 Aug 2023 06:53:27 -0700 (PDT) Message-ID: <20230807135028.161442319@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v+176pp9ACIIPvLc6LDktKyoU9X9mReBTN4+zBUGjJ0=; b=3MJAVBOyeqWg+qSoumYYElftm3Sj3O9raM/01lyZenNB8+4NpMSykM4UoZv0bN8RFX/a1M vweOBTgXt91vD5pnnUGl7araPthxkzw7/oGD4Ti41s/GH5eIGNPWE/9FY9NZAuaQcCQCdY 4XQWDmzjoqdo65zJrueUdBi2iBJRghqjsXNR0ybbDFBk36zyYRHAd21Bj4wX2IswkpKhKE SmSk4Wm++OlNU0Ci48xXcuMcQHyCafLbqHeyID1vmlOXbeIUDGncRvikpwnTSD0agD3KYs G2Wtm39HEQokotO2z5usTSVgH581qGkNffIeFieYsDqC/sytBpNc8vQaKDvr1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v+176pp9ACIIPvLc6LDktKyoU9X9mReBTN4+zBUGjJ0=; b=/YrelmPGc4/3kKdLXjSqR4pk8rqpMbhIIEJ3nii5pjz+WTr7GDQKm2bRKegxKj29p2zFT5 ZY6bN47weaoxzkAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 33/53] x86/cpu/topology: Use a data structure for topology info References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:25 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Put the processor accounting into a data structure, which will gain more topology related information in the next steps, and sanitize the accounting. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 59 ++++++++++++++++++++----------------= ----- 1 file changed, 29 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -23,25 +23,24 @@ DECLARE_BITMAP(phys_cpu_present_map, MAX u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; =20 /* + * Keep track of assigned, disabled and rejected CPUs. Present assigned + * with 1 as CPU #0 is reserved for the boot CPU. + */ +struct { + unsigned int nr_assigned_cpus; + unsigned int nr_disabled_cpus; + unsigned int nr_rejected_cpus; +} topo_info __read_mostly =3D { + .nr_assigned_cpus =3D 1, +}; + +/* * Processor to be disabled specified by kernel parameter * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to * avoid undefined behaviour caused by sending INIT from AP to BSP. */ static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; =20 -static unsigned int num_processors; -static unsigned int disabled_cpus; - -/* - * The number of allocated logical CPU IDs. Since logical CPU IDs are allo= cated - * contiguously, it equals to current allocated max logical CPU ID plus 1. - * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, - * so the maximum of nr_logical_cpuids is nr_cpu_ids. - * - * NOTE: Reserve 0 for BSP. - */ -static int nr_logical_cpuids =3D 1; - bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -75,7 +74,7 @@ static int __init smp_init_primary_threa return 0; } =20 - for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) + for (cpu =3D 0; cpu < topo_info.nr_assigned_cpus; cpu++) cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); return 0; } @@ -89,7 +88,7 @@ static int topo_lookup_cpuid(u32 apic_id int i; =20 /* CPU# to APICID mapping is persistent once it is established */ - for (i =3D 0; i < nr_logical_cpuids; i++) { + for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { if (cpuid_to_apicid[i] =3D=3D apic_id) return i; } @@ -107,22 +106,21 @@ static int allocate_logical_cpuid(u32 ap if (cpu >=3D 0) return cpu; =20 - cpuid_to_apicid[nr_logical_cpuids] =3D apic_id; - return nr_logical_cpuids++; + return topo_info.nr_assigned_cpus++; } =20 -static void cpu_update_apic(int cpu, u32 apicid) +static void cpu_update_apic(unsigned int cpu, u32 apic_id) { #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; #endif + cpuid_to_apicid[cpu] =3D apic_id; set_cpu_possible(cpu, true); - set_bit(apicid, phys_cpu_present_map); + set_bit(apic_id, phys_cpu_present_map); set_cpu_present(cpu, true); - num_processors++; =20 if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apicid); + cpu_mark_primary_thread(cpu, apic_id); } =20 static int generic_processor_info(int apicid) @@ -137,18 +135,18 @@ static int generic_processor_info(int ap return 0; =20 if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; + int thiscpu =3D topo_info.nr_assigned_cpus + topo_info.nr_disabled_cpus; =20 pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", thiscpu, apicid); =20 - disabled_cpus++; + topo_info.nr_rejected_cpus++; return -ENODEV; } =20 - if (num_processors >=3D nr_cpu_ids) { + if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) { pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); - disabled_cpus++; + topo_info.nr_rejected_cpus++; return -ENOSPC; } =20 @@ -178,14 +176,16 @@ static int __initdata setup_possible_cpu */ __init void prefill_possible_map(void) { + unsigned int num_processors =3D topo_info.nr_assigned_cpus; + unsigned int disabled_cpus =3D topo_info.nr_disabled_cpus; int i, possible; =20 i =3D setup_max_cpus ?: 1; if (setup_possible_cpus =3D=3D -1) { - possible =3D num_processors; + possible =3D topo_info.nr_assigned_cpus; #ifdef CONFIG_HOTPLUG_CPU if (setup_max_cpus) - possible +=3D disabled_cpus; + possible +=3D num_processors; #else if (possible > i) possible =3D i; @@ -238,7 +238,7 @@ void __init topology_register_apic(u32 a } =20 if (!present) { - disabled_cpus++; + topo_info.nr_disabled_cpus++; return; } =20 @@ -295,7 +295,6 @@ void topology_hotunplug_apic(unsigned in per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; clear_bit(apic_id, phys_cpu_present_map); set_cpu_present(cpu, false); - num_processors--; } #endif From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84ADBC04A6A for ; Mon, 7 Aug 2023 13:54:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbjHGNyt (ORCPT ); Mon, 7 Aug 2023 09:54:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234596AbjHGNxk (ORCPT ); Mon, 7 Aug 2023 09:53:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CED561703 for ; Mon, 7 Aug 2023 06:53:28 -0700 (PDT) Message-ID: <20230807135028.217017488@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416407; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yTx1K1TOgVQKpA16O0I6vT9VzfdHaMEzdywPzDbFuOw=; b=1WEqWUxRklJni9r/WJ5i62dKJgjJrRVTauTMWkeUrcmaMzCnOyozSrIq3E0nTa5V2PUSQv Yx2Ar7qZ2UAENEFcYO5Y9YQAdVQdbM+VhSgGg1/kzbr6Y0v/ATFnTPVEEnFM7ZR2M2D0jl 9Q1LuETfQUK9Z7Jhock90JOkTBVIWtjPE4NcsxdT+nzC+UBZbVJ5Ch4RuwOI+x+lQVqnT0 Wdfn27PEnJORrkqPRfLlg/u28peJ7E9Xxtv5a+Lh4wyuUVQ3DpXJUukKUu+WfS9Q7JuU/i Q4Nop8ha0qreLWjo9M1QHcA34BwG63GpdvA8NEBjtZrQnxWtnk4Msau42/Kd8g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416407; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yTx1K1TOgVQKpA16O0I6vT9VzfdHaMEzdywPzDbFuOw=; b=7RtmB+XTjyJwlP4WRawDg3RmJTpeBvMUSdrIKC6b+z8/BwacVTc1qY73W6C5VjhXZdTScj LzRQsTbxaoGgHgCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 34/53] x86/smpboot: Make error message actually useful References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:26 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" "smpboot: native_kick_ap: bad cpu 33" is absolutely useless information. Replace it with something meaningful which allows to decode the failure condition. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/smpboot.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1081,9 +1081,13 @@ int native_kick_ap(unsigned int cpu, str =20 pr_debug("++++++++++++++++++++=3D_---CPU UP %u\n", cpu); =20 - if (apicid =3D=3D BAD_APICID || !test_bit(apicid, phys_cpu_present_map) || - !apic_id_valid(apicid)) { - pr_err("%s: bad cpu %d\n", __func__, cpu); + if (apicid =3D=3D BAD_APICID || !apic_id_valid(apicid)) { + pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); + return -EINVAL; + } + + if (!test_bit(apicid, phys_cpu_present_map)) { + pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apic= id); return -EINVAL; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EDD4C001DB for ; Mon, 7 Aug 2023 13:54:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232311AbjHGNyv (ORCPT ); Mon, 7 Aug 2023 09:54:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234599AbjHGNxk (ORCPT ); Mon, 7 Aug 2023 09:53:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BE391BCB for ; Mon, 7 Aug 2023 06:53:30 -0700 (PDT) Message-ID: <20230807135028.272781311@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2y86e1A51xAdlHDuJ9fUEP1blarkIhmxyqQLfQd+Qgs=; b=LJCjhhlilULYNiC9ZXNNGMtCE0SZcQiH/MEYuQaWfRqWhLRpDbhwWOLk08s8YvXW2Zycyk 5/y/rcsz5pGZwGI4RfzwkyG9HsVMcj8lVotz7HmCfOed+wDQZ92UkQxEJrJE+ngP2lamEe RfdxCOHIbT00kvt9N90zYPh38xDziVMck/7GpH8F6AlfOfoBtfFqlP1jgkx65mtea7c9UW cunzKO8HhUSRUey9foL+MTw8Ovn91sYodrb10oPgONfjIT7wXju0A2i6Uu3v3U6UWwW4h4 xMj3iY2hJ4PEMuf5d4qjExYGg2x917tjQSIy0WjeGTTix63Wbd8DPyTHj/H74w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2y86e1A51xAdlHDuJ9fUEP1blarkIhmxyqQLfQd+Qgs=; b=WycnduVW4XP6LfEpzuiNRYbGW8ilR801BFVYjDXAHrck+yUJwntFbihj0CvogBjVfIB3GQ bGXzIJE+isimZCDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 35/53] x86/cpu/topology: Sanitize the APIC admission logic References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:28 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the actually required content of generic_processor_id() into the call sites and use common helper functions for them. This separates the early boot registration and the ACPI hotplug mechanism completely which allows further cleanups and improvements. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 160 +++++++++++++++++------------------- 1 file changed, 78 insertions(+), 82 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -30,8 +30,10 @@ struct { unsigned int nr_assigned_cpus; unsigned int nr_disabled_cpus; unsigned int nr_rejected_cpus; + u32 boot_cpu_apic_id; } topo_info __read_mostly =3D { .nr_assigned_cpus =3D 1, + .boot_cpu_apic_id =3D BAD_APICID, }; =20 /* @@ -78,78 +80,6 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -static int topo_lookup_cpuid(u32 apic_id) -{ - int i; - - /* CPU# to APICID mapping is persistent once it is established */ - for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { - if (cpuid_to_apicid[i] =3D=3D apic_id) - return i; - } - return -ENODEV; -} - -/* - * Should use this API to allocate logical CPU IDs to keep nr_logical_cpui= ds - * and cpuid_to_apicid[] synchronized. - */ -static int allocate_logical_cpuid(u32 apic_id) -{ - int cpu =3D topo_lookup_cpuid(apic_id); - - if (cpu >=3D 0) - return cpu; - - return topo_info.nr_assigned_cpus++; -} - -static void cpu_update_apic(unsigned int cpu, u32 apic_id) -{ -#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) - early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; -#endif - cpuid_to_apicid[cpu] =3D apic_id; - set_cpu_possible(cpu, true); - set_bit(apic_id, phys_cpu_present_map); - set_cpu_present(cpu, true); - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apic_id); -} - -static int generic_processor_info(int apicid) -{ - int cpu; - - /* The boot CPU must be set before MADT/MPTABLE parsing happens */ - if (cpuid_to_apicid[0] =3D=3D BAD_APICID) - panic("Boot CPU APIC not registered yet\n"); - - if (apicid =3D=3D boot_cpu_physical_apicid) - return 0; - - if (disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D topo_info.nr_assigned_cpus + topo_info.nr_disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - topo_info.nr_rejected_cpus++; - return -ENODEV; - } - - if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) { - pr_warn_once("APIC: CPU limit of %d reached. Ignoring further CPUs\n", n= r_cpu_ids); - topo_info.nr_rejected_cpus++; - return -ENOSPC; - } - - cpu =3D allocate_logical_cpuid(apicid); - cpu_update_apic(cpu, apicid); - return cpu; -} - static int __initdata setup_possible_cpus =3D -1; =20 /* @@ -217,6 +147,43 @@ static int __initdata setup_possible_cpu set_cpu_possible(i, true); } =20 +static int topo_lookup_cpuid(u32 apic_id) +{ + int i; + + /* CPU# to APICID mapping is persistent once it is established */ + for (i =3D 0; i < topo_info.nr_assigned_cpus; i++) { + if (cpuid_to_apicid[i] =3D=3D apic_id) + return i; + } + return -ENODEV; +} + +static int topo_assign_cpunr(u32 apic_id) +{ + int cpu =3D topo_lookup_cpuid(apic_id); + + if (cpu >=3D 0) + return cpu; + + return topo_info.nr_assigned_cpus++; +} + +static void topo_set_cpuids(unsigned int cpu, u32 apic_id, u32 acpi_id) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) + early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; + early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; +#endif + cpuid_to_apicid[cpu] =3D apic_id; + + set_cpu_possible(cpu, true); + set_cpu_present(cpu, true); + + if (system_state !=3D SYSTEM_BOOTING) + cpu_mark_primary_thread(cpu, apic_id); +} + /** * topology_register_apic - Register an APIC in early topology maps * @apic_id: The APIC ID to set up @@ -229,17 +196,41 @@ void __init topology_register_apic(u32 a =20 if (apic_id >=3D MAX_LOCAL_APIC) { pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); + topo_info.nr_rejected_cpus++; return; } =20 - if (!present) { - topo_info.nr_disabled_cpus++; + /* CPU numbers exhausted? */ + if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) { + pr_warn_once("CPU limit of %d reached. Ignoring further CPUs\n", nr_cpu_= ids); + topo_info.nr_rejected_cpus++; return; } =20 - cpu =3D generic_processor_info(apic_id); - if (cpu >=3D 0) - early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + if (disabled_cpu_apicid =3D=3D apic_id) { + pr_info("Disabling CPU as requested via 'disable_cpu_apicid=3D0x%x'.\n",= apic_id); + topo_info.nr_rejected_cpus++; + return; + } + + if (present) { + /* + * Prevent double registration, which is valid in case of + * the boot CPU APIC because that is registered before the + * enumeration of the APICs via firmware parsers or VM + * guest mechanisms. + */ + if (test_and_set_bit(apic_id, phys_cpu_present_map)) + return; + + if (apic_id =3D=3D topo_info.boot_cpu_apic_id) + cpu =3D 0; + else + cpu =3D topo_assign_cpunr(apic_id); + topo_set_cpuids(cpu, apic_id, acpi_id); + } else { + topo_info.nr_disabled_cpus++; + } } =20 /** @@ -250,8 +241,10 @@ void __init topology_register_apic(u32 a */ void __init topology_register_boot_apic(u32 apic_id) { - cpuid_to_apicid[0] =3D apic_id; - cpu_update_apic(0, apic_id); + WARN_ON_ONCE(topo_info.boot_cpu_apic_id !=3D BAD_APICID); + + topo_info.boot_cpu_apic_id =3D apic_id; + topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); } =20 #ifdef CONFIG_ACPI_HOTPLUG_CPU @@ -269,10 +262,13 @@ int topology_hotplug_apic(u32 apic_id, u =20 cpu =3D topo_lookup_cpuid(apic_id); if (cpu < 0) { - cpu =3D generic_processor_info(apic_id); - if (cpu >=3D 0) - per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; + if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) + return -ENOSPC; + + cpu =3D topo_assign_cpunr(apic_id); } + set_bit(apic_id, phys_cpu_present_map); + topo_set_cpuids(cpu, apic_id, acpi_id); return cpu; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73865C001DB for ; Mon, 7 Aug 2023 13:54:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234511AbjHGNyz (ORCPT ); Mon, 7 Aug 2023 09:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234627AbjHGNxv (ORCPT ); Mon, 7 Aug 2023 09:53:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F5E01BE3 for ; Mon, 7 Aug 2023 06:53:32 -0700 (PDT) Message-ID: <20230807135028.328142041@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416410; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Zpdb7SGU6c8Ds83Kh6nglp1WOfJEA2K/h0y4EGVH3ck=; b=3zhhsKnjn1f06wB/Iddtt1yQ5sVtATuFc8l884JKT56Urekwm7qaex2ODQnyN7WGEt64DU L5dT2rAVBEsLfkEL0EEq6RjJ+ShazPtlMS5pDLzS1zjcp+ZbnbOzh9SKUxS5K/3m+8+qLu 2wjCrF/tL5GHm8/QJdVSZFY2Xq0az/xSCVWA6GBVr/+8EQT5F2AAPdsn4wMPj2e2Mp2aey Ys2Sjc/WI7C3RK3NMVDbD9+xW1LGPIuVAFlqGbCdSHgn1vIy99ol9yEto++xbOAysRcm5s oVbDKBcbrkPVzs8I8bshalr41oGfOcjikfnSvLwadFvf0w1yYMo7EwhmPaTjfA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416410; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Zpdb7SGU6c8Ds83Kh6nglp1WOfJEA2K/h0y4EGVH3ck=; b=bF90uPgwmU54yr4dJrHdYygvIBfMHG6REh98tNXOnnQQZjK1XiMOPwJ/MoqRYgbnrEqwJE xLGhx3MhWqDp1VAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 36/53] x86/cpu/topology: Rework possible CPU management References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:30 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Managing possible CPUs is an unreadable and uncomprehensible maze. Aside of that it's backwards because it applies command line limits after registering all APICs. Rewrite it so that it: - Applies the command line limits upfront so that only the allowed amount of APIC IDs can be registered. - Applies eventual late restrictions in an understandable way - Uses simple min_t() calculations which are trivial to follow. - Provides a separate function for resetting to UP mode late in the bringup process. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/apic.h | 5 + arch/x86/include/asm/topology.h | 4=20 arch/x86/kernel/cpu/topology.c | 176 ++++++++++++++++++++++++-----------= ----- arch/x86/kernel/setup.c | 9 -- arch/x86/kernel/smpboot.c | 6 - 5 files changed, 120 insertions(+), 80 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -175,6 +175,9 @@ extern void topology_register_apic(u32 a extern void topology_register_boot_apic(u32 apic_id); extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); extern void topology_hotunplug_apic(unsigned int cpu); +extern void topology_apply_cmdline_limits_early(void); +extern void topology_init_possible_cpus(void); +extern void topology_reset_possible_cpus_up(void); =20 #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } @@ -190,6 +193,8 @@ static inline void apic_intr_mode_init(v static inline void lapic_assign_system_vectors(void) { } static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } static inline bool apic_needs_pit(void) { return true; } +static inline void topology_apply_cmdline_limits_early(void) { } +static inline void topology_init_possible_cpus(void) { } #endif /* !CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_X2APIC --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -190,6 +190,9 @@ static inline bool topology_is_primary_t { return cpumask_test_cpu(cpu, cpu_primary_thread_mask); } + +void topology_apply_cmdline_limits_early(void); + #else /* CONFIG_SMP */ #define topology_max_packages() (1) static inline int @@ -202,6 +205,7 @@ static inline int topology_max_smt_threa static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } static inline bool topology_smt_supported(void) { return false; } static inline unsigned int topology_amd_nodes_per_pkg(void) { return 0; }; +static inline void topology_apply_cmdline_limits_early(void) { } #endif /* !CONFIG_SMP */ =20 static inline void arch_fix_phys_package_id(int num, u32 slot) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include #include =20 @@ -85,73 +86,6 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 -static int __initdata setup_possible_cpus =3D -1; - -/* - * cpu_possible_mask should be static, it cannot change as cpu's - * are onlined, or offlined. The reason is per-cpu data-structures - * are allocated by some modules at init time, and don't expect to - * do this dynamically on cpu arrival/departure. - * cpu_present_mask on the other hand can change dynamically. - * In case when cpu_hotplug is not compiled, then we resort to current - * behaviour, which is cpu_possible =3D=3D cpu_present. - * - Ashok Raj - * - * Three ways to find out the number of additional hotplug CPUs: - * - If the BIOS specified disabled CPUs in ACPI/mptables use that. - * - The user can overwrite it with possible_cpus=3DNUM - * - Otherwise don't reserve additional CPUs. - * We do this because additional CPUs waste a lot of memory. - * -AK - */ -__init void prefill_possible_map(void) -{ - unsigned int num_processors =3D topo_info.nr_assigned_cpus; - unsigned int disabled_cpus =3D topo_info.nr_disabled_cpus; - int i, possible; - - i =3D setup_max_cpus ?: 1; - if (setup_possible_cpus =3D=3D -1) { - possible =3D topo_info.nr_assigned_cpus; -#ifdef CONFIG_HOTPLUG_CPU - if (setup_max_cpus) - possible +=3D num_processors; -#else - if (possible > i) - possible =3D i; -#endif - } else - possible =3D setup_possible_cpus; - - total_cpus =3D max_t(int, possible, num_processors + disabled_cpus); - - /* nr_cpu_ids could be reduced via nr_cpus=3D */ - if (possible > nr_cpu_ids) { - pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", - possible, nr_cpu_ids); - possible =3D nr_cpu_ids; - } - -#ifdef CONFIG_HOTPLUG_CPU - if (!setup_max_cpus) -#endif - if (possible > i) { - pr_warn("%d Processors exceeds max_cpus limit of %u\n", - possible, setup_max_cpus); - possible =3D i; - } - - set_nr_cpu_ids(possible); - - pr_info("Allowing %d CPUs, %d hotplug CPUs\n", - possible, max_t(int, possible - num_processors, 0)); - - reset_cpu_possible_mask(); - - for (i =3D 0; i < possible; i++) - set_cpu_possible(i, true); -} - static int topo_lookup_cpuid(u32 apic_id) { int i; @@ -294,12 +228,114 @@ void topology_hotunplug_apic(unsigned in } #endif =20 -static int __init _setup_possible_cpus(char *str) +#ifdef CONFIG_SMP +static unsigned int max_possible_cpus __initdata =3D NR_CPUS; + +/** + * topology_apply_cmdline_limits_early - Apply topology command line limit= s early + * + * Ensure that command line limits are in effect before firmware parsing + * takes place. + */ +void __init topology_apply_cmdline_limits_early(void) +{ + unsigned int possible =3D nr_cpu_ids; + + /* 'maxcpus=3D0' 'nosmp' 'nolapic' 'disableapic' 'noapic' */ + if (!setup_max_cpus || ioapic_is_disabled || apic_is_disabled) + possible =3D 1; + + /* 'possible_cpus=3DN' */ + possible =3D min_t(unsigned int, max_possible_cpus, possible); + + if (possible < nr_cpu_ids) { + pr_info("Limiting to %u possible CPUs\n", possible); + set_nr_cpu_ids(possible); + } +} + +static __init bool restrict_to_up(void) +{ + if (!smp_found_config || ioapic_is_disabled) + return true; + /* + * XEN PV is special as it does not advertise the local APIC + * properly, but provides a fake topology for it so that the + * infrastructure works. So don't apply the restrictions vs. APIC + * here. + */ + if (xen_pv_domain()) + return false; + + return apic_is_disabled; +} + +void __init topology_init_possible_cpus(void) +{ + unsigned int assigned =3D topo_info.nr_assigned_cpus; + unsigned int disabled =3D topo_info.nr_disabled_cpus; + unsigned int total =3D assigned + disabled; + unsigned int cpu, allowed =3D 1; + + if (!restrict_to_up()) { + if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { + disabled +=3D assigned - nr_cpu_ids; + assigned =3D nr_cpu_ids; + } + allowed =3D min_t(unsigned int, total, nr_cpu_ids); + } + + if (total > allowed) + pr_warn("%u possible CPUs exceed the limit of %u\n", total, allowed); + + assigned =3D min_t(unsigned int, allowed, assigned); + disabled =3D allowed - assigned; + + topo_info.nr_assigned_cpus =3D assigned; + topo_info.nr_disabled_cpus =3D disabled; + + total_cpus =3D allowed; + set_nr_cpu_ids(allowed); + + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); + if (topo_info.nr_rejected_cpus) + pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); + + init_cpu_present(cpumask_of(0)); + init_cpu_possible(cpumask_of(0)); + + for (cpu =3D 0; cpu < allowed; cpu++) { + u32 apicid =3D cpuid_to_apicid[cpu]; + + set_cpu_possible(cpu, true); + + if (apicid =3D=3D BAD_APICID) + continue; + + set_cpu_present(cpu, test_bit(apicid, phys_cpu_present_map)); + } +} + +/* + * Late SMP disable after sizing CPU masks when APIC/IOAPIC setup failed. + */ +void __init topology_reset_possible_cpus_up(void) { - get_option(&str, &setup_possible_cpus); + init_cpu_present(cpumask_of(0)); + init_cpu_possible(cpumask_of(0)); + + bitmap_zero(phys_cpu_present_map, MAX_LOCAL_APIC); + if (topo_info.boot_cpu_apic_id !=3D BAD_APICID) + set_bit(topo_info.boot_cpu_apic_id, phys_cpu_present_map); +} + +static int __init setup_possible_cpus(char *str) +{ + get_option(&str, &max_possible_cpus); return 0; } -early_param("possible_cpus", _setup_possible_cpus); +early_param("possible_cpus", setup_possible_cpus); +#endif =20 static int __init apic_set_disabled_cpu_apicid(char *arg) { --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1258,6 +1258,8 @@ void __init setup_arch(char **cmdline_p) =20 early_quirks(); =20 + topology_apply_cmdline_limits_early(); + /* * Parse SMP configuration. Try ACPI first and then the platform * specific parser. @@ -1265,13 +1267,10 @@ void __init setup_arch(char **cmdline_p) acpi_boot_init(); x86_init.mpparse.parse_smp_cfg(); =20 - /* - * Systems w/o ACPI and mptables might not have it mapped the local - * APIC yet, but prefill_possible_map() might need to access it. - */ + /* Last opportunity to detect and map the local APIC */ init_apic_mappings(); =20 - prefill_possible_map(); + topology_init_possible_cpus(); =20 init_cpu_to_node(); init_gi_nodes(); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1156,11 +1156,7 @@ static __init void disable_smp(void) pr_info("SMP disabled\n"); =20 disable_ioapic_support(); - - init_cpu_present(cpumask_of(0)); - init_cpu_possible(cpumask_of(0)); - - reset_phys_cpu_present_map(smp_found_config ? boot_cpu_physical_apicid : = 0); + topology_reset_possible_cpus_up(); =20 cpumask_set_cpu(0, topology_sibling_cpumask(0)); cpumask_set_cpu(0, topology_core_cpumask(0)); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5302C001DB for ; Mon, 7 Aug 2023 13:55:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233393AbjHGNzB (ORCPT ); Mon, 7 Aug 2023 09:55:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234644AbjHGNx4 (ORCPT ); Mon, 7 Aug 2023 09:53:56 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BCF11701 for ; Mon, 7 Aug 2023 06:53:34 -0700 (PDT) Message-ID: <20230807135028.381851690@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416412; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O995zamcyhYTuo3Kkhh4AKJfSIZvbOUniiR7OEFHzns=; b=ooWbvL8Y/LXoIpW3N8w2RajZ1Ijs3j/JUqufRAvJufCPk2pM2E8FLvXynkMXHkFrmL72l0 qAMj1K/Pof4iUjSLtyU0r8jmkyTlsIZ7m1LJLqXJRSAPx0uhyUZvWeUzhR0ptdNLAuXYn5 dK+4XtfeVhj462IKUeBO5e6SuX2E+fQwMDf/sGWdwWcPYeMCDyFZ+3A1eEuYZ78hAyQwVn m96VSTnxhMK4Jx+kM/3ZDnT6TZiIA+mB84m0A2VLDSA7oKmuyihcJB7StIJLtPBM//1OZs 9S+AGObmbV001hSU+ea/E4+TaTpYjp9NfdlKKv9ls8JWRxKK5UvDHrEv+YpRTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416412; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=O995zamcyhYTuo3Kkhh4AKJfSIZvbOUniiR7OEFHzns=; b=DuyhtTc3TpwI0l+Eq/NYUaYB1q5S0VHEyVu4XhTDe2yY2AbAPjoQRWG8Jmo+9krVhSTd1U FU/wqnoUMI5V6/AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 37/53] x86/cpu: Detect real BSP on crash kernels References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:31 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When a kdump kernel is started from a crashing CPU then there is no guarantee that this CPU is the real boot CPU (BSP). If the kdump kernel tries to online the BSP then the INIT sequence will reset the machine. There is a command line option to prevent this, but in case of nested kdump kernels this is wrong. But that command line option is not required at all because the real BSP has the lowest local APIC ID in the system. That was not always true, but support for the only known system which was different (Voyager) got removed long ago. Detect whether the boot CPU APIC ID is the lowest APIC ID in the system. If the lowest registered APIC ID is not the boot CPU APIC ID, then remove it from the present bitmap and let the possible map initialization ignore it. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- Documentation/admin-guide/kdump/kdump.rst | 7 -- Documentation/admin-guide/kernel-parameters.txt | 9 --- arch/x86/kernel/cpu/topology.c | 59 +++++++++++++++----= ----- 3 files changed, 39 insertions(+), 36 deletions(-) --- a/Documentation/admin-guide/kdump/kdump.rst +++ b/Documentation/admin-guide/kdump/kdump.rst @@ -191,9 +191,7 @@ Dump-capture kernel config options (Arch CPU is enough for kdump kernel to dump vmcore on most of systems. =20 However, you can also specify nr_cpus=3DX to enable multiple processors - in kdump kernel. In this case, "disable_cpu_apicid=3D" is needed to - tell kdump kernel which cpu is 1st kernel's BSP. Please refer to - admin-guide/kernel-parameters.txt for more details. + in kdump kernel. =20 With CONFIG_SMP=3Dn, the above things are not related. =20 @@ -485,8 +483,7 @@ loading dump-capture kernel. to use multi-thread programs with it, such as parallel dump feature of makedumpfile. Otherwise, the multi-thread program may have a great performance degradation. To enable multi-cpu support, you should bring u= p an - SMP dump-capture kernel and specify maxcpus/nr_cpus, disable_cpu_apicid= =3D[X] - options while loading it. + SMP dump-capture kernel and specify maxcpus/nr_cpus options while loadin= g it. =20 * For s390x there are two kdump modes: If a ELF header is specified with the elfcorehdr=3D kernel parameter, it is used by the kdump kernel as it --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1071,15 +1071,6 @@ Disable TLBIE instruction. Currently does not work with KVM, with HASH MMU, or with coherent accelerators. =20 - disable_cpu_apicid=3D [X86,APIC,SMP] - Format: - The number of initial APIC ID for the - corresponding CPU to be disabled at boot, - mostly used for the kdump 2nd kernel to - disable BSP to wake up multiple CPUs without - causing system reset or hang due to sending - INIT from AP to BSP. - disable_ddw [PPC/PSERIES] Disable Dynamic DMA Window support. Use this to workaround buggy firmware. --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -32,18 +32,13 @@ struct { unsigned int nr_disabled_cpus; unsigned int nr_rejected_cpus; u32 boot_cpu_apic_id; + u32 real_bsp_apic_id; } topo_info __read_mostly =3D { .nr_assigned_cpus =3D 1, .boot_cpu_apic_id =3D BAD_APICID, + .real_bsp_apic_id =3D BAD_APICID, }; =20 -/* - * Processor to be disabled specified by kernel parameter - * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to - * avoid undefined behaviour caused by sending INIT from AP to BSP. - */ -static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; - bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -146,12 +141,6 @@ void __init topology_register_apic(u32 a return; } =20 - if (disabled_cpu_apicid =3D=3D apic_id) { - pr_info("Disabling CPU as requested via 'disable_cpu_apicid=3D0x%x'.\n",= apic_id); - topo_info.nr_rejected_cpus++; - return; - } - if (present) { /* * Prevent double registration, which is valid in case of @@ -270,6 +259,30 @@ static __init bool restrict_to_up(void) return apic_is_disabled; } =20 +static __init void check_for_kdump_kernel(void) +{ + u32 bsp_apicid; + + /* + * There is no real good way to detect whether this a kdump() + * kernel, but except on the Voyager SMP monstrosity which is not + * longer supported, the real BSP has always the lowest numbered + * APIC ID. If a crash happened on an AP, which then ends up as + * boot CPU in the kdump() kernel, then sending INIT to the real + * BSP would reset the whole system. + */ + bsp_apicid =3D find_first_bit(phys_cpu_present_map, MAX_LOCAL_APIC); + if (bsp_apicid =3D=3D topo_info.boot_cpu_apic_id) + return; + + pr_warn("Boot CPU APIC ID not the lowest APIC ID: %x > %x\n", + topo_info.boot_cpu_apic_id, bsp_apicid); + pr_warn("Crash kernel detected. Disabling real BSP to prevent machine INI= T\n"); + + topo_info.real_bsp_apic_id =3D bsp_apicid; + clear_bit(bsp_apicid, phys_cpu_present_map); +} + void __init topology_init_possible_cpus(void) { unsigned int assigned =3D topo_info.nr_assigned_cpus; @@ -278,6 +291,9 @@ void __init topology_init_possible_cpus( unsigned int cpu, allowed =3D 1; =20 if (!restrict_to_up()) { + if (total > 1) + check_for_kdump_kernel(); + if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { disabled +=3D assigned - nr_cpu_ids; assigned =3D nr_cpu_ids; @@ -308,6 +324,14 @@ void __init topology_init_possible_cpus( for (cpu =3D 0; cpu < allowed; cpu++) { u32 apicid =3D cpuid_to_apicid[cpu]; =20 + /* + * In case of a kdump() kernel, don't mark the real BSP in + * the present and possible maps. Sending INIT to it resets + * the machine. + */ + if (apicid !=3D BAD_APICID && apicid =3D=3D topo_info.real_bsp_apic_id) + continue; + set_cpu_possible(cpu, true); =20 if (apicid =3D=3D BAD_APICID) @@ -337,12 +361,3 @@ static int __init setup_possible_cpus(ch } early_param("possible_cpus", setup_possible_cpus); #endif - -static int __init apic_set_disabled_cpu_apicid(char *arg) -{ - if (!arg || !get_option(&arg, &disabled_cpu_apicid)) - return -EINVAL; - - return 0; -} -early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC83C00528 for ; Mon, 7 Aug 2023 13:55:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233166AbjHGNzV (ORCPT ); Mon, 7 Aug 2023 09:55:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234523AbjHGNx5 (ORCPT ); Mon, 7 Aug 2023 09:53:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4772B1FC8 for ; Mon, 7 Aug 2023 06:53:35 -0700 (PDT) Message-ID: <20230807135028.433963067@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416413; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ItRqIV1rXpKFl7HGEZSaspnnBvb0OflCybv79tP0/ws=; b=eu9j6DQBjz4P89PvAEyCXsuLWYGIwX3vPS/CxmgpYI/XyU9kxJobcUIy5PF0/bmPP4uVBo MNk6gZFhhBRvEqLqSyQHHup7QzmnPwtcgMvpsbJ8OnCxePgFK6b9lWU926352O9P3pZI0I Dkl05Z3I1YlgJdKfynferXvjovUR6imnXxXOcCgCcCK60ugPnVcpUb08j7edGeG1gGzgOu ahD10ga6svYYj5DsGEEJLGpUvZhJnr2SKkg6a5dHs5tLZoZE+8F3puKgja1wyPKbzLpQeA pFouLnYwCL6L10CZuuT2kc11Xzkq26nPXQofQ2E4KZoGjYz49CsAYgU44ry/Fg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416413; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ItRqIV1rXpKFl7HGEZSaspnnBvb0OflCybv79tP0/ws=; b=zo1phJpb/gek4xNYSVXfBdKy/rsQvx8FyDQj9tGI8n3+YOFgCB+qDumRt/Mpx/IcBu7wo9 AQ+tiYAJv8mMgBDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 38/53] x86/topology: Add a mechanism to track topology via APIC IDs References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:33 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Topology on X86 is determined by the registered APIC IDs and the segmentation information retrieved from CPUID. Depending on the granularity of the provided CPUID information the most fine grained scheme looks like this according to Intel terminology: [PKG][DIE][TILE][MODULE][CORE][THREAD] Not enumerated domain levels consume 0 bits in the APIC ID. This allows to provide a consistent view at the topology and determine other information precisely like the number of cores in a package on hybrid systems, where the existing assumption that number or cores =3D=3D number of threads / thr= eads per core does not hold. Provide per domain level bitmaps which record the APIC ID split into the domain levels to make later evaluation of domain level specific information simple. This allows to calculate e.g. the logical IDs without any further extra logic. Contrary to the existing registration mechanism this records disabled CPUs, which are subject to later hotplug as well. That's useful for boot time sizing of package or die dependent allocations without using heuristics. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/debugfs.c | 8 ---- arch/x86/kernel/cpu/topology.c | 68 ++++++++++++++++++++++++++++++++++++= +++-- arch/x86/kernel/cpu/topology.h | 2 + 3 files changed, 67 insertions(+), 11 deletions(-) --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -48,14 +48,6 @@ static const struct file_operations dfs_ =20 static int dom_debug_show(struct seq_file *m, void *p) { - static const char *domain_names[TOPO_ROOT_DOMAIN] =3D { - [TOPO_SMT_DOMAIN] =3D "Thread", - [TOPO_CORE_DOMAIN] =3D "Core", - [TOPO_MODULE_DOMAIN] =3D "Module", - [TOPO_TILE_DOMAIN] =3D "Tile", - [TOPO_DIE_DOMAIN] =3D "Die", - [TOPO_PKG_DOMAIN] =3D "Package", - }; unsigned int dom, nthreads =3D 1; =20 for (dom =3D 0; dom < TOPO_ROOT_DOMAIN; dom++) { --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -1,5 +1,27 @@ // SPDX-License-Identifier: GPL-2.0-only - +/* + * CPU/APIC topology + * + * The APIC IDs describe the system topology in multiple domain levels. + * The CPUID topology parser provides the information which part of the + * APIC ID is associated to the individual levels: + * + * [ROOT][PACKAGE][DIE][TILE][MODULE][CORE][THREAD] + * + * The root space contains the package (socket) IDs. + * + * Not enumerated levels consume 0 bits space, but conceptually they are + * always represented. If e.g. only CORE and THREAD levels are enumerated + * then the DIE, MODULE and TILE have the same physical ID as the PACKAGE. + * + * If SMT is not supported, then the THREAD domain is still used. It then + * has the same physical ID as the CORE domain and is the only child of + * the core domain. + * + * This allows a unified view on the system independent of the enumerated + * domain levels without requiring any conditionals in the code. + */ +#define pr_fmt(fmt) "CPU topo: " fmt #include =20 #include @@ -9,6 +31,8 @@ #include #include =20 +#include "cpu.h" + /* * Map cpu index to physical APIC ID */ @@ -23,6 +47,9 @@ DECLARE_BITMAP(phys_cpu_present_map, MAX /* Used for CPU number allocation and parallel CPU bringup */ u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; =20 +/* Bitmaps to mark registered APICs at each topology domain */ +static struct { DECLARE_BITMAP(map, MAX_LOCAL_APIC); } apic_maps[TOPO_MAX_= DOMAIN] __ro_after_init; + /* * Keep track of assigned, disabled and rejected CPUs. Present assigned * with 1 as CPU #0 is reserved for the boot CPU. @@ -39,6 +66,18 @@ struct { .real_bsp_apic_id =3D BAD_APICID, }; =20 +const char *domain_names[TOPO_MAX_DOMAIN] =3D { + [TOPO_SMT_DOMAIN] =3D "Thread", + [TOPO_CORE_DOMAIN] =3D "Core", + [TOPO_MODULE_DOMAIN] =3D "Module", + [TOPO_TILE_DOMAIN] =3D "Tile", + [TOPO_DIE_DOMAIN] =3D "Die", + [TOPO_PKG_DOMAIN] =3D "Package", + [TOPO_ROOT_DOMAIN] =3D "Root", +}; + +#define domain_weight(_dom) bitmap_weight(apic_maps[_dom].map, MAX_LOCAL_A= PIC) + bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; @@ -81,6 +120,17 @@ early_initcall(smp_init_primary_thread_m static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif =20 +/* + * Convert the APIC ID to a domain level ID by masking out the low bits + * including the domain level @dom. + */ +static inline u32 topo_apicid(u32 apicid, enum x86_topology_domains dom) +{ + if (dom =3D=3D TOPO_SMT_DOMAIN) + return apicid; + return apicid & (UINT_MAX << x86_topo_system.dom_shifts[dom - 1]); +} + static int topo_lookup_cpuid(u32 apic_id) { int i; @@ -126,7 +176,7 @@ static void topo_set_cpuids(unsigned int */ void __init topology_register_apic(u32 apic_id, u32 acpi_id, bool present) { - int cpu; + int cpu, dom; =20 if (apic_id >=3D MAX_LOCAL_APIC) { pr_err_once("APIC ID %x exceeds kernel limit of: %x\n", apic_id, MAX_LOC= AL_APIC - 1); @@ -159,6 +209,10 @@ void __init topology_register_apic(u32 a } else { topo_info.nr_disabled_cpus++; } + + /* Register present and possible CPUs in the domain maps */ + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_ROOT_DOMAIN; dom++) + set_bit(topo_apicid(apic_id, dom), apic_maps[dom].map); } =20 /** @@ -281,6 +335,11 @@ static __init void check_for_kdump_kerne =20 topo_info.real_bsp_apic_id =3D bsp_apicid; clear_bit(bsp_apicid, phys_cpu_present_map); + /* + * Remove it from the SMT level, but no propagation as that would + * corrupt the data set. + */ + clear_bit(bsp_apicid, apic_maps[TOPO_SMT_DOMAIN].map); } =20 void __init topology_init_possible_cpus(void) @@ -288,7 +347,7 @@ void __init topology_init_possible_cpus( unsigned int assigned =3D topo_info.nr_assigned_cpus; unsigned int disabled =3D topo_info.nr_disabled_cpus; unsigned int total =3D assigned + disabled; - unsigned int cpu, allowed =3D 1; + unsigned int cpu, dom, allowed =3D 1; =20 if (!restrict_to_up()) { if (total > 1) @@ -318,6 +377,9 @@ void __init topology_init_possible_cpus( if (topo_info.nr_rejected_cpus) pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); =20 + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_ROOT_DOMAIN; dom++) + pr_info("%-10s: %5u\n", domain_names[dom], domain_weight(dom)); + init_cpu_present(cpumask_of(0)); init_cpu_possible(cpumask_of(0)); =20 --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -48,4 +48,6 @@ static inline void topology_update_dom(s tscan->dom_ncpus[dom] =3D ncpus; } =20 +extern const char *domain_names[TOPO_MAX_DOMAIN]; + #endif /* ARCH_X86_TOPOLOGY_H */ From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37FFEC41513 for ; Mon, 7 Aug 2023 13:55:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234654AbjHGNz3 (ORCPT ); Mon, 7 Aug 2023 09:55:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234676AbjHGNyN (ORCPT ); Mon, 7 Aug 2023 09:54:13 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15D3B1FF9 for ; Mon, 7 Aug 2023 06:53:37 -0700 (PDT) Message-ID: <20230807135028.486658473@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ayByDUJuswmwRg+JdkqaUgq40LVH8XzK6wjgNRkT7J0=; b=V7FUOYfCvGD/WjL1hz+d+jUBSXqy1DJhVjHBHvlzWOx49ih7b+z8Pe3Z5+uLkAELFVl/aR VLKGsCcHj34BJlnqR5RDMZ1G2mHnq1aXUy77opzwjEHaEZmtgJSHnmPhVV91PDEk5Osb7X jVvDcPmKMcXpoByMER5MJm/invKurM1RilwsHT4VeAZwf0ivX23u+nmuOLqTgqx8hfe44a ZbmxmVPuA8S4dsg1AwZz4njC5k+jn2ZXXhJbkaYgoQxh4PiWVL6eZKOlGJBn3uZubIOITV eoasm/VSvYTd2og0tWmh7RsW0pN495wgIiogjUx/RoS5OAwfUBXiHIMdCNfsFA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ayByDUJuswmwRg+JdkqaUgq40LVH8XzK6wjgNRkT7J0=; b=Xs3/S9inXz+zznJfqErs4MVyDfMdQjvATNjIst7qOCoxxN5ZOTE9gFe1rO+DqQWh+O9/zy gWZ28HkVx5sWbfDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 39/53] x86/cpu/topology: Reject unknown APIC IDs on ACPI hotplug References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:34 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The topology bitmaps track all possible APIC IDs which have been registered during enumeration. As sizing and further topology information is going to be derived from these bitmaps, reject attempts to hotplug an APIC ID which was not registered during enumeration. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -237,6 +237,10 @@ int topology_hotplug_apic(u32 apic_id, u if (apic_id >=3D MAX_LOCAL_APIC) return -EINVAL; =20 + /* Reject if the APIC ID was not registered during enumeration. */ + if (!test_bit(apic_id, apic_maps[TOPO_SMT_DOMAIN].map)) + return -ENODEV; + cpu =3D topo_lookup_cpuid(apic_id); if (cpu < 0) { if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD510C001DB for ; Mon, 7 Aug 2023 13:55:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234659AbjHGNzd (ORCPT ); Mon, 7 Aug 2023 09:55:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234689AbjHGNyZ (ORCPT ); Mon, 7 Aug 2023 09:54:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B114210C for ; Mon, 7 Aug 2023 06:53:38 -0700 (PDT) Message-ID: <20230807135028.538458200@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lEJAM6lSEYnamHvy/pM3gmY344lRoNlxzC3YlBMWnmA=; b=ETtcYkCFrSbFl0znfhjYUotU5DP8+kA+1D4ue1kZJamGsOntPw2n8RS/1U4jA4nvldKqlz NzCli0ZDDmh9ksl03VtpnZCBoQAKG6F/F8XwWOL32hm4QP1ClWXslbDtI559xXBv0BOZ8p HTIyFj5SNGQY0KtHfjHwFEZP0Q0DR30ykm1eaVZ2iqjfmdAdy+VsRrYeWXDok5gCHoXi4Y HCJIRYcXiyqn7Z1aDeAzZEkA/1cfeyr29j/H3kmMg5lFKp2zRPKGMukU1nAwaQ1KW/jBF+ rW2HlA7oz3SqrQPjDCGp+qNlt0ysSUMtUjhtT2dRxirgWEIeMXAr9SODu0jhEg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lEJAM6lSEYnamHvy/pM3gmY344lRoNlxzC3YlBMWnmA=; b=NSuebcMVp9x5AsXQoWpMIxO89mNbQXxraBRBoC3sF3EUEebdEi5yMQl8LiWzPYIJndMHey xeyJZANDEw66CZAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 40/53] x86/cpu/topology: Assign hotpluggable CPUIDs during init References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:36 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no point in assigning the CPU numbers during ACPI physical hotplug. The number of possible hotplug CPUs is known when the possible map is initialized, so the CPU numbers can be associated to the registered non-present APIC IDs right there. This allows to put more code into the __init section and makes the related data __ro_after_init. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -45,7 +45,7 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_a DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC) __read_mostly; =20 /* Used for CPU number allocation and parallel CPU bringup */ -u32 cpuid_to_apicid[] __read_mostly =3D { [0 ... NR_CPUS - 1] =3D BAD_APIC= ID, }; +u32 cpuid_to_apicid[] __ro_after_init =3D { [0 ... NR_CPUS - 1] =3D BAD_AP= ICID, }; =20 /* Bitmaps to mark registered APICs at each topology domain */ static struct { DECLARE_BITMAP(map, MAX_LOCAL_APIC); } apic_maps[TOPO_MAX_= DOMAIN] __ro_after_init; @@ -60,7 +60,7 @@ struct { unsigned int nr_rejected_cpus; u32 boot_cpu_apic_id; u32 real_bsp_apic_id; -} topo_info __read_mostly =3D { +} topo_info __ro_after_init =3D { .nr_assigned_cpus =3D 1, .boot_cpu_apic_id =3D BAD_APICID, .real_bsp_apic_id =3D BAD_APICID, @@ -143,7 +143,7 @@ static int topo_lookup_cpuid(u32 apic_id return -ENODEV; } =20 -static int topo_assign_cpunr(u32 apic_id) +static __init int topo_assign_cpunr(u32 apic_id) { int cpu =3D topo_lookup_cpuid(apic_id); =20 @@ -159,8 +159,6 @@ static void topo_set_cpuids(unsigned int early_per_cpu(x86_cpu_to_apicid, cpu) =3D apic_id; early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpi_id; #endif - cpuid_to_apicid[cpu] =3D apic_id; - set_cpu_possible(cpu, true); set_cpu_present(cpu, true); =20 @@ -205,6 +203,8 @@ void __init topology_register_apic(u32 a cpu =3D 0; else cpu =3D topo_assign_cpunr(apic_id); + + cpuid_to_apicid[cpu] =3D apic_id; topo_set_cpuids(cpu, apic_id, acpi_id); } else { topo_info.nr_disabled_cpus++; @@ -247,12 +247,9 @@ int topology_hotplug_apic(u32 apic_id, u return -ENODEV; =20 cpu =3D topo_lookup_cpuid(apic_id); - if (cpu < 0) { - if (topo_info.nr_assigned_cpus >=3D nr_cpu_ids) - return -ENOSPC; + if (cpu < 0) + return -ENOSPC; =20 - cpu =3D topo_assign_cpunr(apic_id); - } set_bit(apic_id, phys_cpu_present_map); topo_set_cpuids(cpu, apic_id, acpi_id); return cpu; @@ -352,6 +349,7 @@ void __init topology_init_possible_cpus( unsigned int disabled =3D topo_info.nr_disabled_cpus; unsigned int total =3D assigned + disabled; unsigned int cpu, dom, allowed =3D 1; + u32 apicid; =20 if (!restrict_to_up()) { if (total > 1) @@ -386,8 +384,16 @@ void __init topology_init_possible_cpus( init_cpu_present(cpumask_of(0)); init_cpu_possible(cpumask_of(0)); =20 + for (apicid =3D 0; disabled; disabled--, apicid++) { + apicid =3D find_next_andnot_bit(apic_maps[TOPO_SMT_DOMAIN].map, phys_cpu= _present_map, + MAX_LOCAL_APIC, apicid); + if (apicid >=3D MAX_LOCAL_APIC) + break; + cpuid_to_apicid[topo_info.nr_assigned_cpus++] =3D apicid; + } + for (cpu =3D 0; cpu < allowed; cpu++) { - u32 apicid =3D cpuid_to_apicid[cpu]; + apicid =3D cpuid_to_apicid[cpu]; =20 /* * In case of a kdump() kernel, don't mark the real BSP in From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 930C3C001DB for ; Mon, 7 Aug 2023 13:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234689AbjHGNzp (ORCPT ); Mon, 7 Aug 2023 09:55:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234700AbjHGNyj (ORCPT ); Mon, 7 Aug 2023 09:54:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEF32136 for ; Mon, 7 Aug 2023 06:53:40 -0700 (PDT) Message-ID: <20230807135028.590964892@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416418; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=o9SLDTJj0ahrwCVinyEBp+cl3PdBP7t2Ahe9Zy+O4Hg=; b=qxJvIkaob+sckp0E/Da7Q7nfjiLdwKRN313sR467mp0de3ZCApwTHm16s7a3z5aRCxal1g 3kP3eHzRW1I/0VO2eRYYlsGpMTctiBssw6PNIPNzJaRPef2xoixxzRRF4pWff84MQbiV37 QKEYHo0CWE1HKAonM5dEbii6DS5gYUmLg+EHT0wAkgOa5hh47EL1Mn47LOVL6s/xKQK/ow d0a2HBYxeFa/WuzGMQwU3imkV8gM6LSTj/yzRIEAlreID2OpLzUeJ2l+RQGGIIz0qf6gcW wjmeShMeLOwedLmc2TPFdRDNzVTdWqPHqhRcOH7L3t3Sz4nSZO+AKatinqnF5A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416418; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=o9SLDTJj0ahrwCVinyEBp+cl3PdBP7t2Ahe9Zy+O4Hg=; b=1oHVvXW3zugTioz7NcC7YLqdyBQOGBYt7nb34N5AFkST+ZYjs85CN3l8F3biTdkhWKuf+r /a432DbYL5kUfxBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 41/53] x86/xen/smp_pv: Count number of vCPUs early References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:37 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" XEN/PV has a completely broken vCPU enumeration scheme, which just works by chance and provides zero topology information. Each vCPU ends up being a single core package. Dom0 provides MADT which can be used for topology information, but that table is the unmodified host table, which means that there can be more CPUs registered than the number of vCPUs XEN provides for the dom0 guest. DomU does not have ACPI and both rely on counting the possible vCPUs via an hypercall. To prepare for using CPUID topology information either via MADT or via fake APIC IDs count the number of possible CPUs during early boot and adjust nr_cpu_ids() accordingly. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/xen/enlighten_pv.c | 3 +++ arch/x86/xen/smp.h | 2 ++ arch/x86/xen/smp_pv.c | 14 ++++++++++++++ 3 files changed, 19 insertions(+) --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -189,6 +189,9 @@ static void __init xen_pv_init_platform( xen_set_mtrr_data(); else mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); + + /* Adjust nr_cpu_ids before "enumeration" happens */ + xen_smp_count_cpus(); } =20 static void __init xen_pv_guest_late_init(void) --- a/arch/x86/xen/smp.h +++ b/arch/x86/xen/smp.h @@ -19,6 +19,7 @@ extern void xen_smp_intr_free(unsigned i int xen_smp_intr_init_pv(unsigned int cpu); void xen_smp_intr_free_pv(unsigned int cpu); =20 +void xen_smp_count_cpus(void); void xen_smp_cpus_done(unsigned int max_cpus); =20 void xen_smp_send_reschedule(int cpu); @@ -44,6 +45,7 @@ static inline int xen_smp_intr_init_pv(u return 0; } static inline void xen_smp_intr_free_pv(unsigned int cpu) {} +static inline void xen_smp_count_cpus(void) { } #endif /* CONFIG_SMP */ =20 #endif --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -411,6 +411,20 @@ static irqreturn_t xen_irq_work_interrup return IRQ_HANDLED; } =20 +void __init xen_smp_count_cpus(void) +{ + unsigned int cpus; + + for (cpus =3D 0; cpus < nr_cpu_ids; cpus++) { + if (HYPERVISOR_vcpu_op(VCPUOP_is_up, cpus, NULL) < 0) + break; + } + + pr_info("Xen PV: Detected %u vCPUS\n", cpus); + if (cpus < nr_cpu_ids) + set_nr_cpu_ids(cpus); +} + static const struct smp_ops xen_smp_ops __initconst =3D { .smp_prepare_boot_cpu =3D xen_pv_smp_prepare_boot_cpu, .smp_prepare_cpus =3D xen_pv_smp_prepare_cpus, From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C33C001DB for ; Mon, 7 Aug 2023 13:55:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234703AbjHGNzx (ORCPT ); Mon, 7 Aug 2023 09:55:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234621AbjHGNyq (ORCPT ); Mon, 7 Aug 2023 09:54:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A990F2680 for ; Mon, 7 Aug 2023 06:53:41 -0700 (PDT) Message-ID: <20230807135028.642879580@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1jDy+E2RKdGXAnT2Cl62jdceXo6yFfKHSHoyZ7qBNXo=; b=Vqgls1KGgbThxa0cPzIzq7xxMdV//XuJ2bdtGlIcyPSeyOdL0fiEtz9nLblciUvbK29I5o qIB5Ijrp5Hfc5mSScEKaxKMNsqVpI/klhiVZS9W2IhBzBlYbHBrmK4UJFv9gTEJavG+gKi Gkibr+qE+rPnZ2wN8yP8Wy/b2ZOPOlhPMHjZehLvrJFBCJSDGKgk+Gae9YSDDTFZz5Ciyp ecYZhOFCOsLhAAUQcn/utmg+jd6YMzXsSbZiyf7Eq0QXVvw8NRBKO/cVplbSEFhqxzzPRg 6bsGI2j0aXC9jj+GJP1wjonFe0pNsp7gcV9plD5lEJCQFnKwe8jPsQ+rVvAvZw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1jDy+E2RKdGXAnT2Cl62jdceXo6yFfKHSHoyZ7qBNXo=; b=R2Nshg6rJNPWAunJZisyc2+a4VAL3Urp50ajDxoRPL7hMZe7RYJsfKdfPhAu828SU7qWDm qe03HyqNRkviv1Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 42/53] x86/cpu/topology: Let XEN/PV use topology from CPUID/MADT References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:39 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It turns out that XEN/PV Dom0 has halfways usable CPUID/MADT enumeration except that it cannot deal with CPUs which are enumerated as disabled in MADT. DomU has no MADT and provides at least rudimentary topology information in CPUID leaves 1 and 4. For both it's important that there are not more possible Linux CPUs than vCPUs provided by the hypervisor. As this is ensured by counting the vCPUs before enumeration happens: - lift the restrictions in the CPUID evaluation and the MADT parser - Utilize MADT registration for Dom0 - Keep the fake APIC ID registration for DomU - Fix the XEN APIC fake so the readout of the local APIC ID works for Dom0 via the hypercall and for DomU by returning the registered fake APIC IDs. With that the XEN/PV fake approximates usefulness. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/acpi/boot.c | 25 ++++++++----------------- arch/x86/kernel/cpu/topology_common.c | 2 +- arch/x86/xen/apic.c | 14 +++++++------- arch/x86/xen/smp_pv.c | 13 ++++++++----- 4 files changed, 24 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -23,8 +23,6 @@ #include #include =20 -#include - #include #include #include @@ -161,12 +159,6 @@ static int __init acpi_parse_madt(struct return 0; } =20 -static __init void acpi_register_lapic(u32 apic_id, u32 acpi_id, bool pres= ent) -{ - if (!xen_pv_domain()) - topology_register_apic(apic_id, acpi_id, present); -} - static bool __init acpi_is_processor_usable(u32 lapic_flags) { if (lapic_flags & ACPI_MADT_ENABLED) @@ -220,7 +212,7 @@ acpi_parse_x2apic(union acpi_subtable_he return 0; } =20 - acpi_register_lapic(apic_id, processor->uid, enabled); + topology_register_apic(apic_id, processor->uid, enabled); #else pr_warn("x2apic entry ignored\n"); #endif @@ -255,9 +247,9 @@ acpi_parse_lapic(union acpi_subtable_hea * to not preallocating memory for all NR_CPUS * when we use CPU hotplug. */ - acpi_register_lapic(processor->id, /* APIC ID */ - processor->processor_id, /* ACPI ID */ - processor->lapic_flags & ACPI_MADT_ENABLED); + topology_register_apic(processor->id, /* APIC ID */ + processor->processor_id, /* ACPI ID */ + processor->lapic_flags & ACPI_MADT_ENABLED); =20 return 0; } @@ -274,9 +266,9 @@ acpi_parse_sapic(union acpi_subtable_hea =20 acpi_table_print_madt_entry(&header->common); =20 - acpi_register_lapic((processor->id << 8) | processor->eid,/* APIC ID */ - processor->processor_id, /* ACPI ID */ - processor->lapic_flags & ACPI_MADT_ENABLED); + topology_register_apic((processor->id << 8) | processor->eid,/* APIC ID */ + processor->processor_id, /* ACPI ID */ + processor->lapic_flags & ACPI_MADT_ENABLED); =20 return 0; } @@ -1073,8 +1065,7 @@ static int __init early_acpi_parse_madt_ return count; } =20 - if (!xen_pv_domain()) - register_lapic_address(acpi_lapic_addr); + register_lapic_address(acpi_lapic_addr); =20 return count; } --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -77,7 +77,7 @@ static bool fake_topology(struct topo_sc topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); topology_set_dom(tscan, TOPO_CORE_DOMAIN, 0, 1); =20 - return tscan->c->cpuid_level < 1 || xen_pv_domain(); + return tscan->c->cpuid_level < 1; } =20 static void parse_topology(struct topo_scan *tscan, bool early) --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -43,20 +43,20 @@ static u32 xen_apic_read(u32 reg) struct xen_platform_op op =3D { .cmd =3D XENPF_get_cpuinfo, .interface_version =3D XENPF_INTERFACE_VERSION, - .u.pcpu_info.xen_cpuid =3D 0, }; - int ret; - - /* Shouldn't need this as APIC is turned off for PV, and we only - * get called on the bootup processor. But just in case. */ - if (!xen_initial_domain() || smp_processor_id()) - return 0; + int ret, cpu; =20 if (reg =3D=3D APIC_LVR) return 0x14; if (reg !=3D APIC_ID) return 0; =20 + cpu =3D smp_processor_id(); + if (!xen_initial_domain()) + return cpu ? cpuid_to_apicid[cpu] << 24 : 0; + + op.u.pcpu_info.xen_cpuid =3D cpu; + ret =3D HYPERVISOR_platform_op(&op); if (ret) op.u.pcpu_info.apic_id =3D BAD_APICID; --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -156,11 +156,9 @@ static void __init xen_pv_smp_config(voi =20 topology_register_boot_apic(apicid++); =20 - for (i =3D 1; i < nr_cpu_ids; i++) { - if (HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL) < 0) - break; + for (i =3D 1; i < nr_cpu_ids; i++) topology_register_apic(apicid++, CPU_ACPIID_INVALID, true); - } + /* Pretend to be a proper enumerated system */ smp_found_config =3D 1; } @@ -451,5 +449,10 @@ void __init xen_smp_init(void) /* Avoid searching for BIOS MP tables */ x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; - x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; + + /* XEN/PV Dom0 has halfways sane topology information via CPUID/MADT */ + if (xen_initial_domain()) + x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; + else + x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC87C00528 for ; Mon, 7 Aug 2023 13:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230362AbjHGNz6 (ORCPT ); Mon, 7 Aug 2023 09:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234544AbjHGNzT (ORCPT ); Mon, 7 Aug 2023 09:55:19 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98DFF10E3 for ; Mon, 7 Aug 2023 06:53:43 -0700 (PDT) Message-ID: <20230807135028.694974099@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416421; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=7pZN2wRws/1IZkNi6hXUXLawLjjwV44InwLkIYNDOuw=; b=2mw72FWrc0idRnHzvMe8/X4LsPpLCPwygEv/0OKcAVurlrb4+ukYHUGXOBU8EW/+BMW+Gb Bv59bQ0wzKvSm49dXBpvfz4OK723779CPX367rYdZVlkNz3Gi+H3340HlzLABla4/ArZBk g/zoAEhAssfdisfuDJapW+2DZ82ZfeVEFo98GLf3k31GTEEZn0HK/lBFCgJvDZaHRKfnl4 A+hlXOh2TUk05YkNl1AbgqmYwhdNPH6C2Tt/IOsPKO2RlA4H1DmO3Z5Fmazvzawj4xu9om f91UAbYJM6uwPQ8PUYfE0V3LXlc7jMEED2+Uk5OWricpjZnprrx+I8V0zsEyIw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416421; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=7pZN2wRws/1IZkNi6hXUXLawLjjwV44InwLkIYNDOuw=; b=DTr/niTPD2pvoxAbObUK/syBaYz6EX5Ffp0Ny5cE9Kq/ltVESzRKNS4v0EwUCUps/UTlsf nVICwqivMIBiehAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 43/53] x86/cpu/topology: Use topology bitmaps for sizing References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:40 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that all possible APIC IDs are tracked in the topology bitmaps, its trivial to retrieve the real information from there. This gets rid of the guesstimates for the maximal packages and dies per package as the actual numbers can be determined before a single AP has been brought up. The number of SMT threads can now be determined correctly from the bitmaps in all situations. Up to now a system which has SMT disabled in the BIOS will still claim that it is SMT capable, because the lowest APIC ID bit is reserved for that and CPUID leaf 0xb/0x1f still enumerates the SMT domain accordingly. By calculating the bitmap weights of the SMT and the CORE domain and setting them into relation the SMT disabled in BIOS situation reports correctly that the system is not SMT capable. It also handles the situation correctly when a hybrid systems boot CPU does not have SMT as it takes the SMT capability of the APs fully into account. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/smp.h | 3 +-- arch/x86/include/asm/topology.h | 23 ++++++++++++----------- arch/x86/kernel/cpu/common.c | 9 ++++++--- arch/x86/kernel/cpu/debugfs.c | 2 +- arch/x86/kernel/cpu/topology.c | 16 +++++++++++++++- arch/x86/kernel/cpu/topology_common.c | 24 ------------------------ arch/x86/kernel/smpboot.c | 16 ---------------- arch/x86/xen/smp.c | 2 -- 8 files changed, 35 insertions(+), 60 deletions(-) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -8,7 +8,7 @@ #include #include =20 -extern int smp_num_siblings; +extern unsigned int smp_num_siblings; =20 DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); @@ -109,7 +109,6 @@ void cpu_disable_common(void); void native_smp_prepare_boot_cpu(void); void smp_prepare_cpus_common(void); void native_smp_prepare_cpus(unsigned int max_cpus); -void calculate_max_logical_packages(void); void native_smp_cpus_done(unsigned int max_cpus); int common_cpu_up(unsigned int cpunum, struct task_struct *tidle); int native_kick_ap(unsigned int cpu, struct task_struct *tidle); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -143,7 +143,18 @@ extern const struct cpumask *cpu_cluster =20 #define topology_amd_node_id(cpu) (cpu_data(cpu).topo.amd_node_id) =20 -extern unsigned int __max_die_per_package; +extern unsigned int __max_dies_per_package; +extern unsigned int __max_logical_packages; + +static inline unsigned int topology_max_packages(void) +{ + return __max_logical_packages; +} + +static inline unsigned int topology_max_die_per_package(void) +{ + return __max_dies_per_package; +} =20 #ifdef CONFIG_SMP #define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) @@ -152,14 +163,6 @@ extern unsigned int __max_die_per_packag #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) #define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) =20 -extern unsigned int __max_logical_packages; -#define topology_max_packages() (__max_logical_packages) - -static inline int topology_max_die_per_package(void) -{ - return __max_die_per_package; -} - extern int __max_smt_threads; =20 static inline int topology_max_smt_threads(void) @@ -194,13 +197,11 @@ static inline bool topology_is_primary_t void topology_apply_cmdline_limits_early(void); =20 #else /* CONFIG_SMP */ -#define topology_max_packages() (1) static inline int topology_update_package_map(unsigned int apicid, unsigned int cpu) { retur= n 0; } static inline int topology_update_die_map(unsigned int dieid, unsigned int cpu) { return 0; } static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } -static inline int topology_max_die_per_package(void) { return 1; } static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } static inline bool topology_smt_supported(void) { return false; } --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -72,11 +72,14 @@ u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ -int smp_num_siblings =3D 1; +unsigned int smp_num_siblings __ro_after_init =3D 1; EXPORT_SYMBOL(smp_num_siblings); =20 -unsigned int __max_die_per_package __read_mostly =3D 1; -EXPORT_SYMBOL(__max_die_per_package); +unsigned int __max_dies_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_dies_per_package); + +unsigned int __max_logical_packages __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_logical_packages); =20 static struct ppin_info { int feature; --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -29,7 +29,7 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); seq_printf(m, "max_cores: %u\n", c->x86_max_cores); - seq_printf(m, "max_die_per_pkg: %u\n", __max_die_per_package); + seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); return 0; } --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -347,8 +347,8 @@ void __init topology_init_possible_cpus( { unsigned int assigned =3D topo_info.nr_assigned_cpus; unsigned int disabled =3D topo_info.nr_disabled_cpus; + unsigned int cnta, cntb, cpu, dom, allowed =3D 1; unsigned int total =3D assigned + disabled; - unsigned int cpu, dom, allowed =3D 1; u32 apicid; =20 if (!restrict_to_up()) { @@ -374,6 +374,20 @@ void __init topology_init_possible_cpus( total_cpus =3D allowed; set_nr_cpu_ids(allowed); =20 + cnta =3D domain_weight(TOPO_PKG_DOMAIN); + cntb =3D domain_weight(TOPO_DIE_DOMAIN); + __max_logical_packages =3D cnta; + __max_dies_per_package =3D 1U << (get_count_order(cntb) - get_count_order= (cnta)); + + pr_info("Max. logical packages: %3u\n", cnta); + pr_info("Max. logical dies: %3u\n", cntb); + pr_info("Max. dies per package: %3u\n", __max_dies_per_package); + + cnta =3D domain_weight(TOPO_CORE_DOMAIN); + cntb =3D domain_weight(TOPO_SMT_DOMAIN); + smp_num_siblings =3D 1U << (get_count_order(cntb) - get_count_order(cnta)= ); + pr_info("Max. threads per core: %3u\n", smp_num_siblings); + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -193,16 +193,6 @@ void cpu_parse_topology(struct cpuinfo_x tscan.dom_shifts[dom], x86_topo_system.dom_shifts[dom]); } =20 - /* Bug compatible with the existing parsers */ - if (tscan.dom_ncpus[TOPO_SMT_DOMAIN] > smp_num_siblings) { - if (system_state =3D=3D SYSTEM_BOOTING) { - pr_warn_once("CPU%d: SMT detected and enabled late\n", cpu); - smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; - } else { - pr_warn_once("CPU%d: SMT detected after init. Too late!\n", cpu); - } - } - topo_set_ids(&tscan); topo_set_max_cores(&tscan); } @@ -229,20 +219,6 @@ void __init cpu_init_topology(struct cpu topo_set_max_cores(&tscan); =20 /* - * Bug compatible with the existing code. If the boot CPU does not - * have SMT this ends up with one sibling. This needs way deeper - * changes further down the road to get it right during early boot. - */ - smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; - - /* - * Neither it's clear whether there are as many dies as the APIC - * space indicating die level is. But assume that the actual number - * of CPUs gives a proper indication for now to stay bug compatible. - */ - __max_die_per_package =3D tscan.dom_ncpus[TOPO_DIE_DOMAIN] / - tscan.dom_ncpus[TOPO_DIE_DOMAIN - 1]; - /* * AMD systems have Nodes per package which cannot be mapped to * APIC ID (yet). */ --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -138,8 +138,6 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct .phys_die_id =3D U32_MAX, }; =20 -unsigned int __max_logical_packages __read_mostly; -EXPORT_SYMBOL(__max_logical_packages); static unsigned int logical_packages __read_mostly; static unsigned int logical_die __read_mostly; =20 @@ -1303,24 +1301,10 @@ void __init native_smp_prepare_boot_cpu( native_pv_lock_init(); } =20 -void __init calculate_max_logical_packages(void) -{ - int ncpus; - - /* - * Today neither Intel nor AMD support heterogeneous systems so - * extrapolate the boot cpu's data to all packages. - */ - ncpus =3D cpu_data(0).booted_cores * topology_max_smt_threads(); - __max_logical_packages =3D DIV_ROUND_UP(total_cpus, ncpus); - pr_info("Max logical packages: %u\n", __max_logical_packages); -} - void __init native_smp_cpus_done(unsigned int max_cpus) { pr_debug("Boot done\n"); =20 - calculate_max_logical_packages(); build_sched_topology(); nmi_selftest(); impress_friends(); --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -123,8 +123,6 @@ void __init xen_smp_cpus_done(unsigned i { if (xen_hvm_domain()) native_smp_cpus_done(max_cpus); - else - calculate_max_logical_packages(); } =20 void xen_smp_send_reschedule(int cpu) From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27B4EC001DB for ; Mon, 7 Aug 2023 13:56:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbjHGN4B (ORCPT ); Mon, 7 Aug 2023 09:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234551AbjHGNz1 (ORCPT ); Mon, 7 Aug 2023 09:55:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47D1326BE for ; Mon, 7 Aug 2023 06:53:45 -0700 (PDT) Message-ID: <20230807135028.747059118@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HA0GkWkS8cpM1N2spYIG0KC2cT4EUF8chsnc8hqXNxI=; b=mbcBIdnUQxSlwmQa6B+H/Gxl393lPsdfzT7tBvYwR3Pn3VJf+tNWgt85zxFZlKT+UExE60 ASDnC02eCyZYX7oG5pFGosDAY7wgWYXqfo7i9s4IXwE7UN8vUEKjyg70NMAgWSck1bK9Vp sq8DFONe71gmmM6A6utJkBgjTFWyvu/Y94S+hHnZVWQbEUIe2n89QtOy3IG1YHv/g6OYwt Y0Daaj5eXg7Ztf98SmbUplU62i50xj7dd1bVbHmJcYXAVc7vmzhkSvTsB20gGfqqrGaq4y 2dlTvsOe9Pi5x41DNKPfgkdFBAyGsl69fcCLCbKMt+PpcIcoisLs+YTvzKenHA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HA0GkWkS8cpM1N2spYIG0KC2cT4EUF8chsnc8hqXNxI=; b=cMZSsmtB0P6xqMZ/ZMF9HG3Kk7dfRR61Hvfa0iJr5FHBerw5WEqBc+hBW+SJbcqeNUvqIs VSi+KA69RHL6wTCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 44/53] x86/cpu/topology: Mop up primary thread mask handling References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:42 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The early initcall to initialize the primary thread mask is not longer required because topology_init_possible_cpus() can mark primary threads correctly when initializing the possible and present map as the number of SMT threads is already determined correctly. The XENPV workaround is not longer required because XENPV now registers fake APIC IDs which will just work like any other enumeration. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -92,30 +92,6 @@ static void cpu_mark_primary_thread(unsi if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } - -/* - * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid - * during early boot. Initialize the primary thread mask before SMP - * bringup. - */ -static int __init smp_init_primary_thread_mask(void) -{ - unsigned int cpu; - - /* - * XEN/PV provides either none or useless topology information. - * Pretend that all vCPUs are primary threads. - */ - if (xen_pv_domain()) { - cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); - return 0; - } - - for (cpu =3D 0; cpu < topo_info.nr_assigned_cpus; cpu++) - cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); - return 0; -} -early_initcall(smp_init_primary_thread_mask); #else static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int = apicid) { } #endif @@ -161,9 +137,6 @@ static void topo_set_cpuids(unsigned int #endif set_cpu_possible(cpu, true); set_cpu_present(cpu, true); - - if (system_state !=3D SYSTEM_BOOTING) - cpu_mark_primary_thread(cpu, apic_id); } =20 /** @@ -252,6 +225,7 @@ int topology_hotplug_apic(u32 apic_id, u =20 set_bit(apic_id, phys_cpu_present_map); topo_set_cpuids(cpu, apic_id, acpi_id); + cpu_mark_primary_thread(cpu, apic_id); return cpu; } =20 @@ -422,6 +396,7 @@ void __init topology_init_possible_cpus( if (apicid =3D=3D BAD_APICID) continue; =20 + cpu_mark_primary_thread(cpu, apicid); set_cpu_present(cpu, test_bit(apicid, phys_cpu_present_map)); } } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 161BCC001B0 for ; Mon, 7 Aug 2023 13:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbjHGN4Q (ORCPT ); Mon, 7 Aug 2023 09:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234575AbjHGNze (ORCPT ); Mon, 7 Aug 2023 09:55:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 251532719 for ; Mon, 7 Aug 2023 06:53:48 -0700 (PDT) Message-ID: <20230807135028.800668666@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AfQzecPadC51W0+MsVlK3HeQl1U7zVudClCfarez7gY=; b=o3DfM5U0t2/heXbjNrpNe+8MgvT4QU3LQfgTHRXocTWlyqrnHGZNM70YEC67f6seJ6oYyC fxveX/aTf8tLgHbBB0UQEMmtkGmC1U7BmWy2D85o3o5rU3I4N/RcTLLb4q9xTyddK4z0jn Z+vX5Cm/t18OeSXWodBOBacNzfaytosgpaNoejFmDnFwmG0Uda10M1rfZHc2umSzSU/VdL gcJ4nNBgc8R/3EOwSgWxgoh4eTWpRospBv3KlZ0AlFUv92Frqerr4e0BYNHGBaTzTXn8la ipk5LpKdJpA+f1XJXXy8So30LuuXvNG0XnL1jIlXWviUvsMlfy9TzB929UMSLw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AfQzecPadC51W0+MsVlK3HeQl1U7zVudClCfarez7gY=; b=IDoTbYofzNkQBexjtr281rhNB0OHaOZL+AMofq4QKR4XiiVdvkCJjeRknNnfvs6D2zO3LR aNw5JcxvNd3IaFCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 45/53] x86/cpu/topology: Simplify cpu_mark_primary_thread() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:44 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No point in creating a mask via fls(). smp_num_siblings is guaranteed to be a power of 2. So just using (smp_num_siblings - 1) has the same effect. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -86,10 +86,7 @@ bool arch_match_cpu_phys_id(int cpu, u64 #ifdef CONFIG_SMP static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { - /* Isolate the SMT bit(s) in the APICID and check for 0 */ - u32 mask =3D (1U << (fls(smp_num_siblings) - 1)) - 1; - - if (smp_num_siblings =3D=3D 1 || !(apicid & mask)) + if (!(apicid & (smp_num_siblings - 1))) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } #else From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBEEEC001B0 for ; Mon, 7 Aug 2023 13:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234627AbjHGN43 (ORCPT ); Mon, 7 Aug 2023 09:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232402AbjHGNzy (ORCPT ); Mon, 7 Aug 2023 09:55:54 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75772199C for ; Mon, 7 Aug 2023 06:53:57 -0700 (PDT) Message-ID: <20230807135028.852716187@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416426; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aiPd1kJ39cEUiKercbaDdBw1XcAUDDQu1AI+a4ZUPac=; b=NU7iSmQfUQwNrqJyCFAczRCZqUyKGATvOAUgm2VAVI3hydE0Djlcpn+HIWW4cVv5fHBMs+ h3z1aOSg8ZvOpur5AGs2hSqc6+o9sN8ZJ/kcZ6VphfRKxKvChB08vwFr/2lNgQAiPK6G/G i/R0n3Fkzb4lX4kNB5bKQgZPsaWFzQ+ZOe3pGjWn542YrPTbvERhsZUMkDo6TSO/AlVzyo Ti5365Vm/TOXVhjT1zOEPeZC+d1Gr/qv80awJovr895uvAbldkrQk28jatlY7quWM0Qjra EUO9f61Ey5gRitQ4SNJp7inm3oNnynRmNd9Ee80A3jgzhIdg6pdMtpir3Enhqw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416426; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aiPd1kJ39cEUiKercbaDdBw1XcAUDDQu1AI+a4ZUPac=; b=c0u5DRuWzz5yn+Xx0JLP4M+VQZfLcyZJhQUSKfjoCKpytodMjdCpVMXz8faPw1TLOMmmoX C3GH3ySuicSvuEBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 46/53] x86/cpu/topology: Provide logical pkg/die mapping References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:45 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the topology bitmaps in place the logical package and die IDs can trivially be retrieved by determining the bitmap weight of the relevant topology domain level up to and including the physical ID in question. Provide a function to that effect. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/topology.h | 2 ++ arch/x86/kernel/cpu/topology.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -156,6 +156,8 @@ static inline unsigned int topology_max_ return __max_dies_per_package; } =20 +int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level= ); + #ifdef CONFIG_SMP #define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu)) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -199,6 +199,34 @@ void __init topology_register_boot_apic( topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); } =20 +/** + * topology_get_logical_id - Retrieve the logical ID at a given topology d= omain level + * @apicid: The APIC ID for which to lookup the logical ID + * @at_level: The topology domain level to use + * + * @apicid must be a full APIC ID, not the normalized variant. It's valid = to have + * all bits below the domain level specified by @at_level to be clear. So = both + * real APIC IDs and backshifted normalized APIC IDs work correctly. + * + * Returns: + * - >=3D 0: The requested logical ID + * - -ERANGE: @apicid is out of range + * - -ENODEV: @apicid is not registered + */ +int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level) +{ + /* Remove the bits below @at_level to get the proper level ID of @apicid = */ + unsigned int lvlid =3D topo_apicid(apicid, at_level); + + if (lvlid >=3D MAX_LOCAL_APIC) + return -ERANGE; + if (!test_bit(lvlid, apic_maps[at_level].map)) + return -ENODEV; + /* Get the number of set bits before @lvlid. */ + return bitmap_weight(apic_maps[at_level].map, lvlid); +} +EXPORT_SYMBOL_GPL(topology_get_logical_id); + #ifdef CONFIG_ACPI_HOTPLUG_CPU /** * topology_hotplug_apic - Handle a physical hotplugged APIC after boot From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B1B5C001B0 for ; Mon, 7 Aug 2023 13:56:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234569AbjHGN4d (ORCPT ); Mon, 7 Aug 2023 09:56:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234346AbjHGN4M (ORCPT ); Mon, 7 Aug 2023 09:56:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC6E30D6 for ; Mon, 7 Aug 2023 06:54:02 -0700 (PDT) Message-ID: <20230807135028.905547409@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416427; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=j7OFjclpvkjeiv/gw2/Emcd71M9jz+vMU9xYSIvRiEo=; b=xqo9ZaM1LLCfF08ATvGnDcfpYmc4mAh21E6HXSz2Om+ipnlUgYwN5lmPluijLFLdM886kg qv/6chThN3AsZxYj8WBPuJMIU4j7g9X2MDcds2qTr0bhBe/364H0Yp+xVqesuciaKOc5ew s5Q5EOXD4NKqpbjtxg3KEpfbLNSJJgGt0WKNyNxdsw170KZXTaqXrksfvNWTfh3WPm/DwM XqrwbL5jqz1VpGLi4wLgDXimEn3rQJHVJQSxYxWFjkYeS59cohvC8ES0omJZwEealB8FjN 42ZJJmiHs2kNvgE946Or/nSi7XMM30sm6S7ZC60UrMqYSg48QLQ60TozG2Lemg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416427; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=j7OFjclpvkjeiv/gw2/Emcd71M9jz+vMU9xYSIvRiEo=; b=ngJBZMNxfFt/IejW6lJIeykdXTMvumCez1aqyhbJURw4eDoqjrSC5ZCtUKcGnhPFy6mADo yln+WXBT8AGRNXAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 47/53] x86/cpu/topology: Use topology logical mapping mechanism References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:47 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the logical package and die management functionality and retrieve the logical IDs from the topology bitmaps. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/topology.h | 13 +-- arch/x86/kernel/cpu/common.c | 13 --- arch/x86/kernel/cpu/topology_common.c | 4 + arch/x86/kernel/smpboot.c | 111 -----------------------------= ----- 4 files changed, 11 insertions(+), 130 deletions(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -158,6 +158,12 @@ static inline unsigned int topology_max_ =20 int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level= ); =20 +static inline int topology_phys_to_logical_pkg(unsigned int pkg) +{ + return topology_get_logical_id(pkg << x86_topo_system.dom_shifts[TOPO_PKG= _DOMAIN], + TOPO_PKG_DOMAIN); +} + #ifdef CONFIG_SMP #define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu)) @@ -172,9 +178,6 @@ static inline int topology_max_smt_threa return __max_smt_threads; } =20 -int topology_update_package_map(unsigned int apicid, unsigned int cpu); -int topology_update_die_map(unsigned int dieid, unsigned int cpu); -int topology_phys_to_logical_pkg(unsigned int pkg); bool topology_smt_supported(void); =20 extern unsigned int __amd_nodes_per_pkg; @@ -199,10 +202,6 @@ static inline bool topology_is_primary_t void topology_apply_cmdline_limits_early(void); =20 #else /* CONFIG_SMP */ -static inline int -topology_update_package_map(unsigned int apicid, unsigned int cpu) { retur= n 0; } -static inline int -topology_update_die_map(unsigned int dieid, unsigned int cpu) { return 0; } static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1679,18 +1679,6 @@ static void generic_identify(struct cpui #endif } =20 -static void update_package_map(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned int cpu =3D smp_processor_id(); - - BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); - BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); -#else - c->topo.logical_pkg_id =3D 0; -#endif -} - /* * This does the hard work of actually picking apart the CPU stuff... */ @@ -1868,7 +1856,6 @@ void identify_secondary_cpu(struct cpuin #ifdef CONFIG_X86_32 enable_sep_cpu(); #endif - update_package_map(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); =20 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -10,6 +10,7 @@ #include "cpu.h" =20 struct x86_topology_system x86_topo_system __ro_after_init; +EXPORT_SYMBOL_GPL(x86_topo_system); =20 unsigned int __amd_nodes_per_pkg __ro_after_init; EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg); @@ -147,6 +148,9 @@ static void topo_set_ids(struct topo_sca c->topo.pkg_id =3D topo_shift_apicid(apicid, TOPO_PKG_DOMAIN); c->topo.die_id =3D topo_shift_apicid(apicid, TOPO_DIE_DOMAIN); =20 + c->topo.logical_pkg_id =3D topology_get_logical_id(apicid, TOPO_PKG_DOMAI= N); + c->topo.logical_die_id =3D topology_get_logical_id(apicid, TOPO_DIE_DOMAI= N); + /* Relative core ID */ c->topo.core_id =3D topo_relative_domain_id(apicid, TOPO_CORE_DOMAIN); =20 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -124,23 +124,6 @@ struct mwait_cpu_dead { */ static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); =20 -/* Logical package management. */ -struct logical_maps { - u32 phys_pkg_id; - u32 phys_die_id; - u32 logical_pkg_id; - u32 logical_die_id; -}; - -/* Temporary workaround until the full topology mechanics is in place */ -static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) =3D { - .phys_pkg_id =3D U32_MAX, - .phys_die_id =3D U32_MAX, -}; - -static unsigned int logical_packages __read_mostly; -static unsigned int logical_die __read_mostly; - /* Maximum number of SMT threads on any online core */ int __read_mostly __max_smt_threads =3D 1; =20 @@ -345,103 +328,11 @@ bool topology_smt_supported(void) return smp_num_siblings > 1; } =20 -/** - * topology_phys_to_logical_pkg - Map a physical package id to a logical - * @phys_pkg: The physical package id to map - * - * Returns logical package id or -1 if not found - */ -int topology_phys_to_logical_pkg(unsigned int phys_pkg) -{ - int cpu; - - for_each_possible_cpu(cpu) { - if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D phys_pkg) - return per_cpu(logical_maps.logical_pkg_id, cpu); - } - return -1; -} -EXPORT_SYMBOL(topology_phys_to_logical_pkg); - -/** - * topology_phys_to_logical_die - Map a physical die id to logical - * @die_id: The physical die id to map - * @cur_cpu: The CPU for which the mapping is done - * - * Returns logical die id or -1 if not found - */ -static int topology_phys_to_logical_die(unsigned int die_id, unsigned int = cur_cpu) -{ - int cpu, proc_id =3D cpu_data(cur_cpu).topo.pkg_id; - - for_each_possible_cpu(cpu) { - if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D proc_id && - per_cpu(logical_maps.phys_die_id, cpu) =3D=3D die_id) - return per_cpu(logical_maps.logical_die_id, cpu); - } - return -1; -} - -/** - * topology_update_package_map - Update the physical to logical package map - * @pkg: The physical package id as retrieved via CPUID - * @cpu: The cpu for which this is updated - */ -int topology_update_package_map(unsigned int pkg, unsigned int cpu) -{ - int new; - - /* Already available somewhere? */ - new =3D topology_phys_to_logical_pkg(pkg); - if (new >=3D 0) - goto found; - - new =3D logical_packages++; - if (new !=3D pkg) { - pr_info("CPU %u Converting physical %u to logical package %u\n", - cpu, pkg, new); - } -found: - per_cpu(logical_maps.phys_pkg_id, cpu) =3D pkg; - per_cpu(logical_maps.logical_pkg_id, cpu) =3D new; - cpu_data(cpu).topo.logical_pkg_id =3D new; - return 0; -} -/** - * topology_update_die_map - Update the physical to logical die map - * @die: The die id as retrieved via CPUID - * @cpu: The cpu for which this is updated - */ -int topology_update_die_map(unsigned int die, unsigned int cpu) -{ - int new; - - /* Already available somewhere? */ - new =3D topology_phys_to_logical_die(die, cpu); - if (new >=3D 0) - goto found; - - new =3D logical_die++; - if (new !=3D die) { - pr_info("CPU %u Converting physical %u to logical die %u\n", - cpu, die, new); - } -found: - per_cpu(logical_maps.phys_die_id, cpu) =3D die; - per_cpu(logical_maps.logical_die_id, cpu) =3D new; - cpu_data(cpu).topo.logical_die_id =3D new; - return 0; -} - void __init smp_store_boot_cpu_info(void) { - int id =3D 0; /* CPU 0 */ - struct cpuinfo_x86 *c =3D &cpu_data(id); + struct cpuinfo_x86 *c =3D &cpu_data(0); =20 *c =3D boot_cpu_data; - c->cpu_index =3D id; - topology_update_package_map(c->topo.pkg_id, id); - topology_update_die_map(c->topo.die_id, id); c->initialized =3D true; } From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2644C001B0 for ; Mon, 7 Aug 2023 13:56:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232217AbjHGN4g (ORCPT ); Mon, 7 Aug 2023 09:56:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234574AbjHGN4N (ORCPT ); Mon, 7 Aug 2023 09:56:13 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D48C230E6 for ; Mon, 7 Aug 2023 06:54:03 -0700 (PDT) Message-ID: <20230807135028.957980935@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416429; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ph7RYPSGUyMuFVs2yJ045YytT8AyPZYMy0+K0KiHV3c=; b=lpaO6/ZmrKCyJgmJ2rFvtDsqnC+QbF2AxqmmgLpn15UrjOcbXwkSxXYQVL5t7Cy5Gfhvse R3VVz+SXGZWHcJ4A/TJ+X+qaGnfkP3d8key5eJ54lqx2fveumR3I4RrFFGYIuubBEH+QGw PMcFrcxnMRYmbXXR6kuY0q7ljtGq1MomJA/0bCc0jm6lXasZXgYjFfqIoLlnVldbxZ2Phh +7oELvK/Ke1j7/LEzmEmQbao+aD9xfxYxfCLI1e1Pv1ISa9ygiJnukOZhtpYVXgZe7QO0N l6SWnLkJVFMENO0RdaKYOAdyEpBLcrKBDQjoIm40yAiCm/gLTbvZ6vSW4m3njQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416429; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ph7RYPSGUyMuFVs2yJ045YytT8AyPZYMy0+K0KiHV3c=; b=sFnIZqwJYWUDUa5fF6yrsi+9p88PE8KFWxoTA0yzJBIp0OBhwuhlhCJ0Klz3NwuaWALTYj VTrpkk/0b3mQt+DQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 48/53] x86/cpu/topology: Retrieve cores per package from topology bitmaps References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:48 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to other sizing information the number of cores per package can be established from the topology bitmap. Provide a function for retrieving that information and replace the buggy hack in the CPUID evaluation with it. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/kernel/cpu/topology.c | 43 +++++++++++++++++++++++++++++= +++++ arch/x86/kernel/cpu/topology.h | 3 ++ arch/x86/kernel/cpu/topology_common.c | 18 ++------------ 3 files changed, 49 insertions(+), 15 deletions(-) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -227,6 +227,49 @@ int topology_get_logical_id(u32 apicid, } EXPORT_SYMBOL_GPL(topology_get_logical_id); =20 +/** + * topology_unit_count - Retrieve the count of specified units at a given = topology domain level + * @apicid: The APIC ID which specifies the search range + * @which_units: The domain level specifying the units to count + * @at_level: The domain level at which @which_units have to be counted + * + * This returns the number of possible units according to the enumerated + * information. + * + * E.g. topology_count_units(apicid, TOPO_CORE_DOMAIN, TOPO_PKG_DOMAIN) + * counts the number of possible cores in the package to which @apicid + * belongs. + * + * @at_level must obviously be greater than @which_level to produce useful + * results. If @at_level is equal to @which_units the result is + * unsurprisingly 1. If @at_level is less than @which_units the results + * is by definition undefined and the function returns 0. + */ +unsigned int topology_unit_count(u32 apicid, enum x86_topology_domains whi= ch_units, + enum x86_topology_domains at_level) +{ + /* Remove the bits below @at_level to get the proper level ID of @apicid = */ + unsigned int lvlid =3D topo_apicid(apicid, at_level); + unsigned int id, end, cnt =3D 0; + + if (lvlid >=3D MAX_LOCAL_APIC) + return 0; + if (!test_bit(lvlid, apic_maps[at_level].map)) + return 0; + if (which_units > at_level) + return 0; + if (which_units =3D=3D at_level) + return 1; + + /* Calculate the exclusive end */ + end =3D lvlid + (1U << x86_topo_system.dom_shifts[at_level]); + /* Unfortunately there is no bitmap_weight_range() */ + for (id =3D find_next_bit(apic_maps[which_units].map, end, lvlid); + id < end; id =3D find_next_bit(apic_maps[which_units].map, end, ++id= )) + cnt++; + return cnt; +} + #ifdef CONFIG_ACPI_HOTPLUG_CPU /** * topology_hotplug_apic - Handle a physical hotplugged APIC after boot --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -50,4 +50,7 @@ static inline void topology_update_dom(s =20 extern const char *domain_names[TOPO_MAX_DOMAIN]; =20 +unsigned int topology_unit_count(u32 apicid, enum x86_topology_domains whi= ch_units, + enum x86_topology_domains at_level); + #endif /* ARCH_X86_TOPOLOGY_H */ --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -154,25 +154,15 @@ static void topo_set_ids(struct topo_sca /* Relative core ID */ c->topo.core_id =3D topo_relative_domain_id(apicid, TOPO_CORE_DOMAIN); =20 + /* Maximum number of cores on this package */ + c->x86_max_cores =3D topology_unit_count(apicid, TOPO_CORE_DOMAIN, TOPO_P= KG_DOMAIN); + c->topo.amd_node_id =3D tscan->amd_node_id; =20 if (c->x86_vendor =3D=3D X86_VENDOR_AMD) cpu_topology_fixup_amd(tscan); } =20 -static void topo_set_max_cores(struct topo_scan *tscan) -{ - /* - * Bug compatible for now. This is broken on hybrid systems: - * 8 cores SMT + 8 cores w/o SMT - * tscan.dom_ncpus[TOPO_CORE_DOMAIN] =3D 24; 24 / 2 =3D 12 !! - * - * Cannot be fixed without further topology enumeration changes. - */ - tscan->c->x86_max_cores =3D tscan->dom_ncpus[TOPO_CORE_DOMAIN] >> - x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; -} - void cpu_parse_topology(struct cpuinfo_x86 *c) { unsigned int dom, cpu =3D smp_processor_id(); @@ -198,7 +188,6 @@ void cpu_parse_topology(struct cpuinfo_x } =20 topo_set_ids(&tscan); - topo_set_max_cores(&tscan); } =20 void __init cpu_init_topology(struct cpuinfo_x86 *c) @@ -220,7 +209,6 @@ void __init cpu_init_topology(struct cpu } =20 topo_set_ids(&tscan); - topo_set_max_cores(&tscan); =20 /* * AMD systems have Nodes per package which cannot be mapped to From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C18C04A6A for ; Mon, 7 Aug 2023 13:56:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232185AbjHGN4r (ORCPT ); Mon, 7 Aug 2023 09:56:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234609AbjHGN4Q (ORCPT ); Mon, 7 Aug 2023 09:56:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CFAC3586 for ; Mon, 7 Aug 2023 06:54:07 -0700 (PDT) Message-ID: <20230807135029.009917769@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416430; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Es3P3wUc8dTCX9Wd6cL1INpIUVEDH8jUOH/8KtNoObI=; b=JmooD2zOj8ZSgid2qaMEmTu0hVqCsJ/pfVNVxByLZNFYmJyOQw3qGRis4XgW04AHeRRn2Q LlobDT5i4qfXxuNikzUiYOA595Dxo7VWipOCwv+xJT4JQ0lMtxg9Fq8wSXQGrJx2QPRdgK Vd0BoA+tl3qiHwAt8xUQubIw7a4hsQGrYcJrSnNSLI92QZ4frbN41mRaca3WryQtyC4l/w upxCrke/7xK/UE0WfnRWOiXdaZzYQEBdD92BOrn87BSccs3IyWbr93qaHk4ogjj0mT5My8 IrNuC+yXcYRP7yUqBzUtRJw/uIMqbZUtbyTrGCYTSohNNJAXWm0hkeJuSviOXA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416430; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Es3P3wUc8dTCX9Wd6cL1INpIUVEDH8jUOH/8KtNoObI=; b=0rYCcFEPJqde2sSSM+Q1geAOPdxC8o0eSV/c7KAL2Rp7xHdaqeytT9E9GTXf1IAjyPMBO3 H5dOeX9uMVOq3cBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 49/53] x86: Use topology functions instead of smp_num_siblings where applicable References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:50 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Accessors exist for a reason. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/perf_event_p4.h | 11 ++--------- arch/x86/kernel/process.c | 2 +- arch/x86/kernel/smpboot.c | 2 +- 3 files changed, 4 insertions(+), 11 deletions(-) --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -180,19 +180,12 @@ static inline u64 p4_clear_ht_bit(u64 co =20 static inline int p4_ht_active(void) { -#ifdef CONFIG_SMP - return smp_num_siblings > 1; -#endif - return 0; + return topology_smt_supported(); } =20 static inline int p4_ht_thread(int cpu) { -#ifdef CONFIG_SMP - if (smp_num_siblings =3D=3D 2) - return cpu !=3D cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map)); -#endif - return 0; + return !topology_is_primary_thread(cpu); } =20 static inline int p4_should_swap_ts(u64 config, int cpu) --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -924,7 +924,7 @@ static __cpuidle void mwait_idle(void) void select_idle_routine(const struct cpuinfo_x86 *c) { #ifdef CONFIG_SMP - if (boot_option_idle_override =3D=3D IDLE_POLL && smp_num_siblings > 1) + if (boot_option_idle_override =3D=3D IDLE_POLL && topology_smt_supported(= )) pr_warn_once("WARNING: polling idle and HT enabled, performance may degr= ade\n"); #endif if (x86_idle_set() || boot_option_idle_override =3D=3D IDLE_POLL) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -573,7 +573,7 @@ static void __init build_sched_topology( =20 void set_cpu_sibling_map(int cpu) { - bool has_smt =3D smp_num_siblings > 1; + bool has_smt =3D topology_smt_supported(); bool has_mp =3D has_smt || boot_cpu_data.x86_max_cores > 1; struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct cpuinfo_x86 *o; From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DD9FC04A6A for ; Mon, 7 Aug 2023 13:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231676AbjHGN5G (ORCPT ); Mon, 7 Aug 2023 09:57:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234655AbjHGN4m (ORCPT ); Mon, 7 Aug 2023 09:56:42 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA6FF3AB9 for ; Mon, 7 Aug 2023 06:54:21 -0700 (PDT) Message-ID: <20230807135029.061717423@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416432; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vq2LqKgDPaDhnlrBU4urRm/zoBPsw6UyhSpMosqqfTs=; b=2LMEqnSWJ88DG/xbwPK2/D8zRGGIDIMKG7vbcYXhn+Wb6eyTJpYCjg3Ci+25IRBstViGLd NSRdyQggrVb362Cf2Tuk3KczI8Y34GXrlLQ4LV8Pn/hz172+Cgqip//1Jcreqcotho152O e7D3L6QzosmBajJ4SklaxErB+DUC0oBESJJ/orOqVQ4MUJjzzd9/r06VncMtDd7zcd2PPR aumWruEG/huibXlfzAXznRCLI6oT68FgrcQOB3DXB1XlpHz93Q119JUUJXtu+THFY3N7lm rGzURS6OAVToStmULtTJkDohNVbK8EZF5vsQLSHpbJ9GFiKcotn3lTGE1YTEdg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416432; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vq2LqKgDPaDhnlrBU4urRm/zoBPsw6UyhSpMosqqfTs=; b=iv5hFfUxtG6Oze3lXxizz8BN2fAYPck3cM0RnS9YRy9x9lKZAWlY252Q15kAEabfCk7580 JIy+zgv1GLUG45AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 50/53] x86/cpu/topology: Rename smp_num_siblings References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's really a non-intuitive name. Rename it to __max_threads_per_core which is obvious. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/smp.h | 2 -- arch/x86/include/asm/topology.h | 6 +++++- arch/x86/kernel/cpu/common.c | 4 ++-- arch/x86/kernel/cpu/debugfs.c | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/cpu/topology.c | 6 +++--- arch/x86/kernel/smpboot.c | 8 -------- 7 files changed, 12 insertions(+), 18 deletions(-) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -8,8 +8,6 @@ #include #include =20 -extern unsigned int smp_num_siblings; - DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -145,6 +145,7 @@ extern const struct cpumask *cpu_cluster =20 extern unsigned int __max_dies_per_package; extern unsigned int __max_logical_packages; +extern unsigned int __max_threads_per_core; =20 static inline unsigned int topology_max_packages(void) { @@ -178,7 +179,10 @@ static inline int topology_max_smt_threa return __max_smt_threads; } =20 -bool topology_smt_supported(void); +static inline bool topology_smt_supported(void) +{ + return __max_threads_per_core > 1; +} =20 extern unsigned int __amd_nodes_per_pkg; =20 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -72,8 +72,8 @@ u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ -unsigned int smp_num_siblings __ro_after_init =3D 1; -EXPORT_SYMBOL(smp_num_siblings); +unsigned int __max_threads_per_core __ro_after_init =3D 1; +EXPORT_SYMBOL(__max_threads_per_core); =20 unsigned int __max_dies_per_package __ro_after_init =3D 1; EXPORT_SYMBOL(__max_dies_per_package); --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -30,7 +30,7 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); seq_printf(m, "max_cores: %u\n", c->x86_max_cores); seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); - seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); + seq_printf(m, "max_threads_per_core:%u\n", __max_threads_per_core); return 0; } =20 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -433,7 +433,7 @@ static u32 get_nbc_for_node(int node_id) struct cpuinfo_x86 *c =3D &boot_cpu_data; u32 cores_per_node; =20 - cores_per_node =3D (c->x86_max_cores * smp_num_siblings) / topology_amd_n= odes_per_pkg(); + cores_per_node =3D (c->x86_max_cores * __max_threads_per_core) / topology= _amd_nodes_per_pkg(); return cores_per_node * node_id; } =20 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -86,7 +86,7 @@ bool arch_match_cpu_phys_id(int cpu, u64 #ifdef CONFIG_SMP static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { - if (!(apicid & (smp_num_siblings - 1))) + if (!(apicid & (__max_threads_per_core - 1))) cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); } #else @@ -427,8 +427,8 @@ void __init topology_init_possible_cpus( =20 cnta =3D domain_weight(TOPO_CORE_DOMAIN); cntb =3D domain_weight(TOPO_SMT_DOMAIN); - smp_num_siblings =3D 1U << (get_count_order(cntb) - get_count_order(cnta)= ); - pr_info("Max. threads per core: %3u\n", smp_num_siblings); + __max_threads_per_core =3D 1U << (get_count_order(cntb) - get_count_order= (cnta)); + pr_info("Max. threads per core: %3u\n", __max_threads_per_core); =20 pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -320,14 +320,6 @@ static void notrace start_secondary(void cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); } =20 -/** - * topology_smt_supported - Check whether SMT is supported by the CPUs - */ -bool topology_smt_supported(void) -{ - return smp_num_siblings > 1; -} - void __init smp_store_boot_cpu_info(void) { struct cpuinfo_x86 *c =3D &cpu_data(0); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58E95C001B0 for ; Mon, 7 Aug 2023 13:56:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229785AbjHGN4t (ORCPT ); Mon, 7 Aug 2023 09:56:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231682AbjHGN40 (ORCPT ); Mon, 7 Aug 2023 09:56:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3EC835AE for ; Mon, 7 Aug 2023 06:54:10 -0700 (PDT) Message-ID: <20230807135029.113801542@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=w4U+yB4ROBK4XzZUwiiPUCYehecaC+ipD1PTXQaVmCQ=; b=fgD2PDxVwUdKHh2/dXbkPQQh2+P8oZa9wFPNt0LfCVfaIwvLWbw8GnzZbrnMp3vzym6fY/ gzy1z1c4L3xVcEiFqdgki0QIPc6dxSeR9DVvxlkCCLpA/cjO6wqkt+5zPaXoli0v41dAdh ++GoXSRoY4G7Desul1Xx4PQxIwjbKGIj3h//Op0eKxEnUpAOZxzvRbSRMmAVgrU8Bb+igW NYHJUi0vJNak3MvubdkU/vA587wuuGdln6dxUBcbWjYi23sN0bDpKcBXq+2hpumeNA2oUn 928/YyKdFDcYsNixfENVifg+o4NL85+d6MF1ntEgW5NYKITnEcV5qz/JWeLeNw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=w4U+yB4ROBK4XzZUwiiPUCYehecaC+ipD1PTXQaVmCQ=; b=/kkrO2CUw/3bkBxO1bRbt/+Dbz00VgAyWPb+rqGZ93bThk51PNJlMJoFL0axJDwnasya16 rwDq9Vm9y3Q3X9DA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 51/53] x86/cpu/topology: Rename topology_max_die_per_package() References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:53 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The plural of die is dies. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/events/intel/cstate.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/intel/uncore_snbep.c | 2 +- arch/x86/events/rapl.c | 2 +- arch/x86/include/asm/topology.h | 2 +- drivers/hwmon/coretemp.c | 2 +- drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c | 2 +- drivers/powercap/intel_rapl_common.c | 2 +- drivers/thermal/intel/intel_hfi.c | 2 +- drivers/thermal/intel/intel_powerclamp.c | 2 +- drivers/thermal/intel/x86_pkg_temp_thermal.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -751,7 +751,7 @@ static int __init cstate_init(void) } =20 if (has_cstate_pkg) { - if (topology_max_die_per_package() > 1) { + if (topology_max_dies_per_package() > 1) { err =3D perf_pmu_register(&cstate_pkg_pmu, "cstate_die", -1); } else { --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1881,7 +1881,7 @@ static int __init intel_uncore_init(void return -ENODEV; =20 __uncore_max_dies =3D - topology_max_packages() * topology_max_die_per_package(); + topology_max_packages() * topology_max_dies_per_package(); =20 id =3D x86_match_cpu(intel_uncore_match); if (!id) { --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -1441,7 +1441,7 @@ static int snbep_pci2phy_map_init(int de */ for (i =3D 0; i < 8; i++) { if (nodeid =3D=3D GIDNIDMAP(config, i)) { - if (topology_max_die_per_package() > 1) + if (topology_max_dies_per_package() > 1) die_id =3D i; else die_id =3D topology_phys_to_logical_pkg(i); --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -678,7 +678,7 @@ static const struct attribute_group *rap =20 static int __init init_rapl_pmus(void) { - int maxdie =3D topology_max_packages() * topology_max_die_per_package(); + int maxdie =3D topology_max_packages() * topology_max_dies_per_package(); size_t size; =20 size =3D sizeof(*rapl_pmus) + maxdie * sizeof(struct rapl_pmu *); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -152,7 +152,7 @@ static inline unsigned int topology_max_ return __max_logical_packages; } =20 -static inline unsigned int topology_max_die_per_package(void) +static inline unsigned int topology_max_dies_per_package(void) { return __max_dies_per_package; } --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -780,7 +780,7 @@ static int __init coretemp_init(void) if (!x86_match_cpu(coretemp_ids)) return -ENODEV; =20 - max_zones =3D topology_max_packages() * topology_max_die_per_package(); + max_zones =3D topology_max_packages() * topology_max_dies_per_package(); zone_devices =3D kcalloc(max_zones, sizeof(struct platform_device *), GFP_KERNEL); if (!zone_devices) --- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c +++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c @@ -229,7 +229,7 @@ static int __init intel_uncore_init(void return -ENODEV; =20 uncore_max_entries =3D topology_max_packages() * - topology_max_die_per_package(); + topology_max_dies_per_package(); uncore_instances =3D kcalloc(uncore_max_entries, sizeof(*uncore_instances), GFP_KERNEL); if (!uncore_instances) --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -1566,7 +1566,7 @@ struct rapl_package *rapl_add_package(in if (id_is_cpu) { rp->id =3D topology_logical_die_id(id); rp->lead_cpu =3D id; - if (topology_max_die_per_package() > 1) + if (topology_max_dies_per_package() > 1) snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d-die-%d", topology_physical_package_id(id), topology_die_id(id)); else --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -542,7 +542,7 @@ void __init intel_hfi_init(void) =20 /* There is one HFI instance per die/package. */ max_hfi_instances =3D topology_max_packages() * - topology_max_die_per_package(); + topology_max_dies_per_package(); =20 /* * This allocation may fail. CPU hotplug callbacks must check --- a/drivers/thermal/intel/intel_powerclamp.c +++ b/drivers/thermal/intel/intel_powerclamp.c @@ -616,7 +616,7 @@ static int powerclamp_idle_injection_reg poll_pkg_cstate_enable =3D false; if (cpumask_equal(cpu_present_mask, idle_injection_cpu_mask)) { ii_dev =3D idle_inject_register_full(idle_injection_cpu_mask, idle_injec= t_update); - if (topology_max_packages() =3D=3D 1 && topology_max_die_per_package() = =3D=3D 1) + if (topology_max_packages() =3D=3D 1 && topology_max_dies_per_package() = =3D=3D 1) poll_pkg_cstate_enable =3D true; } else { ii_dev =3D idle_inject_register(idle_injection_cpu_mask); --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -494,7 +494,7 @@ static int __init pkg_temp_thermal_init( if (!x86_match_cpu(pkg_temp_thermal_ids)) return -ENODEV; =20 - max_id =3D topology_max_packages() * topology_max_die_per_package(); + max_id =3D topology_max_packages() * topology_max_dies_per_package(); zones =3D kcalloc(max_id, sizeof(struct zone_device *), GFP_KERNEL); if (!zones) From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF009C00528 for ; Mon, 7 Aug 2023 13:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234644AbjHGN5S (ORCPT ); Mon, 7 Aug 2023 09:57:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232312AbjHGN45 (ORCPT ); Mon, 7 Aug 2023 09:56:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F20E74222 for ; Mon, 7 Aug 2023 06:54:31 -0700 (PDT) Message-ID: <20230807135029.166295656@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gGPnBkTfW+8B5SQXJHv1hpNWRmiBwz+4UGwUc972rDw=; b=gUx+AJ4BNaJQrnonAOcot/xmdvpaOMg6OhvZ2XZ2EsQGYvVALa8wQyI1Rw7PAdCZy0qSwH Yqc4yKmozV6zAaG6CqeGst/MuASRp5t/yXP8b/g4NIFUkzmf6uXhuClATg9Fltv6Iz9ESR yEQJUeaFjKrXYAB6zQh96OwItVovZrcHyCmcg4vEy7Thp2numswApE+yDbUTftDkMIqAug Xi1GR1KNazhvbRagclkmiQRp2oaxi3wDcuelpyxpsyZd/9APWxZd3gMfbykBkT4XAthVCd lC1lBcnVt6AnRKfzAVXvR4jJ/kynSy4GSTAXQjHuNpmnD/0TsIcR4X4PhQ8D/Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gGPnBkTfW+8B5SQXJHv1hpNWRmiBwz+4UGwUc972rDw=; b=jsdqZR++153ohXhEKjnvEMV/nlkzpS3n+K0Ps0yPvvZC2iOtFWrkmlbOJVUThtoYKP+S2d FKzyUz+C04J3vTAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 52/53] x86/cpu/topology: Provide __num_[cores|threads]_per_package References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:55 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expose properly accounted information and accessors so the fiddling with other topology variables can be replaced. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- arch/x86/include/asm/topology.h | 12 ++++++++++++ arch/x86/kernel/cpu/common.c | 6 ++++++ arch/x86/kernel/cpu/topology.c | 8 +++++++- 3 files changed, 25 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -146,6 +146,8 @@ extern const struct cpumask *cpu_cluster extern unsigned int __max_dies_per_package; extern unsigned int __max_logical_packages; extern unsigned int __max_threads_per_core; +extern unsigned int __num_threads_per_package; +extern unsigned int __num_cores_per_package; =20 static inline unsigned int topology_max_packages(void) { @@ -157,6 +159,16 @@ static inline unsigned int topology_max_ return __max_dies_per_package; } =20 +static inline unsigned int topology_num_cores_per_package(void) +{ + return __num_cores_per_package; +} + +static inline unsigned int topology_num_threads_per_package(void) +{ + return __num_threads_per_package; +} + int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level= ); =20 static inline int topology_phys_to_logical_pkg(unsigned int pkg) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -81,6 +81,12 @@ EXPORT_SYMBOL(__max_dies_per_package); unsigned int __max_logical_packages __ro_after_init =3D 1; EXPORT_SYMBOL(__max_logical_packages); =20 +unsigned int __num_cores_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__num_cores_per_package); + +unsigned int __num_threads_per_package __ro_after_init =3D 1; +EXPORT_SYMBOL(__num_threads_per_package); + static struct ppin_info { int feature; int msr_ppin_ctl; --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -391,7 +391,7 @@ void __init topology_init_possible_cpus( unsigned int disabled =3D topo_info.nr_disabled_cpus; unsigned int cnta, cntb, cpu, dom, allowed =3D 1; unsigned int total =3D assigned + disabled; - u32 apicid; + u32 apicid, firstid; =20 if (!restrict_to_up()) { if (total > 1) @@ -430,6 +430,12 @@ void __init topology_init_possible_cpus( __max_threads_per_core =3D 1U << (get_count_order(cntb) - get_count_order= (cnta)); pr_info("Max. threads per core: %3u\n", __max_threads_per_core); =20 + firstid =3D find_first_bit(apic_maps[TOPO_SMT_DOMAIN].map, MAX_LOCAL_APIC= ); + __num_cores_per_package =3D topology_unit_count(firstid, TOPO_CORE_DOMAIN= , TOPO_PKG_DOMAIN); + pr_info("Num. cores per package: %3u\n", __num_cores_per_package); + __num_threads_per_package =3D topology_unit_count(firstid, TOPO_SMT_DOMAI= N, TOPO_PKG_DOMAIN); + pr_info("Num. threads per package: %3u\n", __num_threads_per_package); + pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disa= bled); if (topo_info.nr_rejected_cpus) pr_info("Rejected CPUs %u\n", topo_info.nr_rejected_cpus); From nobody Tue Dec 16 21:02:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CCE3C001B0 for ; Mon, 7 Aug 2023 13:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233413AbjHGN5V (ORCPT ); Mon, 7 Aug 2023 09:57:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232009AbjHGN5B (ORCPT ); Mon, 7 Aug 2023 09:57:01 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35165448B for ; Mon, 7 Aug 2023 06:54:34 -0700 (PDT) Message-ID: <20230807135029.218547661@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691416437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WqgG4QEoiVjOabpVvy0BSbv+5bAKRRIBbAeySHAi/Gw=; b=jplEhKbdRKLpyID7HB7clAc+iF3FbHIl1alIVDPIN2RChzXEX6l1oQV1GRsabostqPKh/u U9yhz4fgWqHtOkLsyNQvX8fKB9QzzNbRpGW5/3UM5qEYCxfK5N85dg7RaVRZwc231Uopeg RBq6/SopVomP3bUj8VOS9cq97f382yabGVWwg5M0dbilqtB8kvk71+pnEWqZbJK2Q6YdvS MkEKr0e43LuC/7Byvp3wZWihy7gQhFqbEKCffPu04zVUaFmhbeb6nguCR/3eYilAA1bu9l FR+9OZy7acEhTd7t8+QunHs4NBkDhu76UyNLdpF1UljUvuctWl7+n6RClcR6LQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691416437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WqgG4QEoiVjOabpVvy0BSbv+5bAKRRIBbAeySHAi/Gw=; b=SZvbr7iLmGg2ibPrgsxC4r+kOcvUHzL3r0BAAvhlMZbCE+zH8NJu/m7q8oylKBci3zlFGS gc1PSm+EsT8J4NDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko Subject: [patch 53/53] x86/cpu/topology: Get rid of cpuinfo::x86_max_cores References: <20230807130108.853357011@linutronix.de> MIME-Version: 1.0 Date: Mon, 7 Aug 2023 15:53:56 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that __num_cores_per_package and __num_threads_per_package are available, cpuinfo::x86_max_cores and the related math all over the place can be replaced with the ready to consume data. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Sohil Mehta --- Documentation/arch/x86/topology.rst | 24 ++++++++----------= ----- arch/x86/events/intel/uncore_nhmex.c | 4 +-- arch/x86/events/intel/uncore_snb.c | 8 +++---- arch/x86/events/intel/uncore_snbep.c | 16 +++++++-------- arch/x86/include/asm/processor.h | 2 - arch/x86/kernel/cpu/cacheinfo.c | 2 - arch/x86/kernel/cpu/common.c | 1=20 arch/x86/kernel/cpu/debugfs.c | 3 +- arch/x86/kernel/cpu/mce/inject.c | 3 -- arch/x86/kernel/cpu/microcode/intel.c | 4 +-- arch/x86/kernel/cpu/topology_common.c | 3 -- arch/x86/kernel/smpboot.c | 2 - drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 2 - drivers/hwmon/fam15h_power.c | 2 - 14 files changed, 32 insertions(+), 44 deletions(-) --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -47,17 +47,21 @@ AMD nomenclature for package is 'Node'. =20 Package-related topology information in the kernel: =20 - - cpuinfo_x86.x86_max_cores: + - topology_num_threads_per_package() =20 - The number of cores in a package. This information is retrieved via CP= UID. + The number of threads in a package. =20 - - cpuinfo_x86.x86_max_dies: + - topology_num_cores_per_package() =20 - The number of dies in a package. This information is retrieved via CPU= ID. + The number of cores in a package. + + - topology_max_dies_per_package() + + The maximum number of dies in a package. =20 - cpuinfo_x86.topo_die_id: =20 - The physical ID of the die. This information is retrieved via CPUID. + The physical ID of the die. =20 - cpuinfo_x86.topo.pkg_id: =20 @@ -96,16 +100,6 @@ are SMT- or CMT-type threads. AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses "core". =20 -Core-related topology information in the kernel: - - - smp_num_siblings: - - The number of threads in a core. The number of threads in a package ca= n be - calculated by:: - - threads_per_package =3D cpuinfo_x86.x86_max_cores * smp_num_siblings - - Threads =3D=3D=3D=3D=3D=3D=3D A thread is a single scheduling unit. It's the equivalent to a logical Lin= ux --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -1221,8 +1221,8 @@ void nhmex_uncore_cpu_init(void) uncore_nhmex =3D true; else nhmex_uncore_mbox.event_descs =3D wsmex_uncore_mbox_events; - if (nhmex_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - nhmex_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (nhmex_uncore_cbox.num_boxes > topology_num_cores_per_package()) + nhmex_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D nhmex_msr_uncores; } /* end of Nehalem-EX uncore support */ --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -364,8 +364,8 @@ static struct intel_uncore_type *snb_msr void snb_uncore_cpu_init(void) { uncore_msr_uncores =3D snb_msr_uncores; - if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - snb_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (snb_uncore_cbox.num_boxes > topology_num_cores_per_package()) + snb_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); } =20 static void skl_uncore_msr_init_box(struct intel_uncore_box *box) @@ -428,8 +428,8 @@ static struct intel_uncore_type *skl_msr void skl_uncore_cpu_init(void) { uncore_msr_uncores =3D skl_msr_uncores; - if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - skl_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (skl_uncore_cbox.num_boxes > topology_num_cores_per_package()) + skl_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); snb_uncore_arb.ops =3D &skl_uncore_msr_ops; } =20 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -1172,8 +1172,8 @@ static struct intel_uncore_type *snbep_m =20 void snbep_uncore_cpu_init(void) { - if (snbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - snbep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (snbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + snbep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D snbep_msr_uncores; } =20 @@ -1837,8 +1837,8 @@ static struct intel_uncore_type *ivbep_m =20 void ivbep_uncore_cpu_init(void) { - if (ivbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - ivbep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (ivbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + ivbep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D ivbep_msr_uncores; } =20 @@ -2909,8 +2909,8 @@ static bool hswep_has_limit_sbox(unsigne =20 void hswep_uncore_cpu_init(void) { - if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - hswep_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (hswep_uncore_cbox.num_boxes > topology_num_cores_per_package()) + hswep_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); =20 /* Detect 6-8 core systems with only two SBOXes */ if (hswep_has_limit_sbox(HSWEP_PCU_DID)) @@ -3272,8 +3272,8 @@ static struct event_constraint bdx_uncor =20 void bdx_uncore_cpu_init(void) { - if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) - bdx_uncore_cbox.num_boxes =3D boot_cpu_data.x86_max_cores; + if (bdx_uncore_cbox.num_boxes > topology_num_cores_per_package()) + bdx_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); uncore_msr_uncores =3D bdx_msr_uncores; =20 /* Detect systems with no SBOXes */ --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -148,8 +148,6 @@ struct cpuinfo_x86 { unsigned long loops_per_jiffy; /* protected processor identification number */ u64 ppin; - /* cpuid returned max cores value: */ - u16 x86_max_cores; u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -301,7 +301,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_ eax->split.type =3D types[leaf]; eax->split.level =3D levels[leaf]; eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D __this_cpu_read(cpu_info.x86_max_cores) -= 1; + eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 =20 if (assoc =3D=3D 0xffff) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1698,7 +1698,6 @@ static void identify_cpu(struct cpuinfo_ c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ c->x86_vendor_id[0] =3D '\0'; /* Unset */ c->x86_model_id[0] =3D '\0'; /* Unset */ - c->x86_max_cores =3D 1; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -28,7 +28,8 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "l2c_id: %u\n", c->topo.l2c_id); seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); - seq_printf(m, "max_cores: %u\n", c->x86_max_cores); + seq_printf(m, "num_threads: %u\n", __num_threads_per_package); + seq_printf(m, "num_cores: %u\n", __num_cores_per_package); seq_printf(m, "max_dies_per_pkg: %u\n", __max_dies_per_package); seq_printf(m, "max_threads_per_core:%u\n", __max_threads_per_core); return 0; --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -430,10 +430,9 @@ static void trigger_thr_int(void *info) =20 static u32 get_nbc_for_node(int node_id) { - struct cpuinfo_x86 *c =3D &boot_cpu_data; u32 cores_per_node; =20 - cores_per_node =3D (c->x86_max_cores * __max_threads_per_core) / topology= _amd_nodes_per_pkg(); + cores_per_node =3D topology_num_threads_per_package() / topology_amd_node= s_per_pkg(); return cores_per_node * node_id; } =20 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -43,7 +43,7 @@ static const char ucode_path[] =3D "kernel static struct microcode_intel *intel_ucode_patch; =20 /* last level cache size per core */ -static int llc_size_per_core; +static unsigned long llc_size_per_core; =20 /* * Returns 1 if update has been found, 0 otherwise. @@ -777,7 +777,7 @@ static int __init calc_llc_size_per_core { u64 llc_size =3D c->x86_cache_size * 1024ULL; =20 - do_div(llc_size, c->x86_max_cores); + do_div(llc_size, topology_num_cores_per_package()); =20 return (int)llc_size; } --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -154,9 +154,6 @@ static void topo_set_ids(struct topo_sca /* Relative core ID */ c->topo.core_id =3D topo_relative_domain_id(apicid, TOPO_CORE_DOMAIN); =20 - /* Maximum number of cores on this package */ - c->x86_max_cores =3D topology_unit_count(apicid, TOPO_CORE_DOMAIN, TOPO_P= KG_DOMAIN); - c->topo.amd_node_id =3D tscan->amd_node_id; =20 if (c->x86_vendor =3D=3D X86_VENDOR_AMD) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -566,7 +566,7 @@ static void __init build_sched_topology( void set_cpu_sibling_map(int cpu) { bool has_smt =3D topology_smt_supported(); - bool has_mp =3D has_smt || boot_cpu_data.x86_max_cores > 1; + bool has_mp =3D has_smt || topology_num_cores_per_package() > 1; struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct cpuinfo_x86 *o; int i, threads; --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -472,7 +472,7 @@ static int vangogh_init_smc_tables(struc =20 #ifdef CONFIG_X86 /* AMD x86 APU only */ - smu->cpu_core_num =3D boot_cpu_data.x86_max_cores; + smu->cpu_core_num =3D topology_num_cores_per_package(); #else smu->cpu_core_num =3D 4; #endif --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -209,7 +209,7 @@ static ssize_t power1_average_show(struc * With the new x86 topology modelling, x86_max_cores is the * compute unit number. */ - cu_num =3D boot_cpu_data.x86_max_cores; + cu_num =3D topology_num_cores_per_package(); =20 ret =3D read_registers(data); if (ret)