From nobody Wed Dec 17 10:42:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE35FEE49A3 for ; Tue, 22 Aug 2023 07:10:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233239AbjHVHKO (ORCPT ); Tue, 22 Aug 2023 03:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233233AbjHVHKE (ORCPT ); Tue, 22 Aug 2023 03:10:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0C2BCD4 for ; Tue, 22 Aug 2023 00:09:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1EE3B64D18 for ; Tue, 22 Aug 2023 07:09:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBA84C433C8; Tue, 22 Aug 2023 07:09:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692688192; bh=YWcF5FYjmBa5ZzNhVXuTsMWow8CghL/K0RmXeemBMIU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TsjNsNl5KE+5gIEKx76Yi79TjlkLlVljlVzLJ1C6OlosqeY4UtLuH4PUIQSxLFBx4 xtrbP1+P2//22eYCRJllvW9ehshooGzcqQvEmaynmiSWhkLhQJ7Rq2L8EDdRwxRV0g sZOtPpyR/Iy0W19Oc9jU+zaDldcF8sYRAv1H2WDJybUeX5QARjSDX5aGjc6f0T7xXx kHJBizWvTGVPZPOBCzt92+8tKV/o13y0BN69X5aIWIzatdhjwpjbkVu50FIKeVVdde 2RskH8m58rXXPSiUM8jJX9cje+uQJetTmYZIrJcxcnBKAAIVZ60zPtVQeT8GGnGj80 Z07h9/4Q1a79g== From: Michael Walle Date: Tue, 22 Aug 2023 09:09:24 +0200 Subject: [PATCH v2 08/41] mtd: spi-nor: default .n_banks to 1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230807-mtd-flash-info-db-rework-v2-8-291a0f39f8d8@kernel.org> References: <20230807-mtd-flash-info-db-rework-v2-0-291a0f39f8d8@kernel.org> In-Reply-To: <20230807-mtd-flash-info-db-rework-v2-0-291a0f39f8d8@kernel.org> To: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle X-Mailer: b4 0.12.2 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If .n_banks is not set in the flash_info database, the default value should be 1. This way, we don't have to always set the .n_banks parameter in flash_info. Signed-off-by: Michael Walle Reviewed-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 +-- drivers/mtd/spi-nor/core.h | 8 ++++---- drivers/mtd/spi-nor/xilinx.c | 1 - 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e27f1323fa0b..68baf6032639 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2017,7 +2017,6 @@ static const struct spi_nor_manufacturer *manufacture= rs[] =3D { =20 static const struct flash_info spi_nor_generic_flash =3D { .name =3D "spi-nor-generic", - .n_banks =3D 1, .parse_sfdp =3D true, }; =20 @@ -2997,7 +2996,7 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) params->size =3D info->size; params->bank_size =3D params->size; params->page_size =3D info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; - params->n_banks =3D info->n_banks; + params->n_banks =3D info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; =20 if (!(info->flags & SPI_NOR_NO_FR)) { /* Default to Fast Read for DT and non-DT platform devices. */ diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2fc999f2787c..8627d0b95be6 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -15,6 +15,7 @@ * have the page size defined within their SFDP tables. */ #define SPI_NOR_DEFAULT_PAGE_SIZE 256 +#define SPI_NOR_DEFAULT_N_BANKS 1 =20 /* Standard SPI NOR flash operations. */ #define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ @@ -453,7 +454,7 @@ struct spi_nor_fixups { * @size: the size of the flash in bytes. * @sector_size: the size listed here is what works with SPINOR_OP_SE, = which * isn't necessarily called a "sector" by the vendor. - * @n_banks: the number of banks. + * @n_banks: (optional) the number of banks. Defaults to 1. * @page_size: (optional) the flash's page size. Defaults to 256. * @addr_nbytes: number of address bytes to send. * @@ -570,7 +571,7 @@ struct flash_info { /* Used when the "_ext_id" is two bytes at most */ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors) \ SPI_NOR_ID((_jedec_id), (_ext_id)), \ - SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 1), + SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 0), =20 #define INFOB(_jedec_id, _ext_id, _sector_size, _n_sectors, _n_banks) \ SPI_NOR_ID((_jedec_id), (_ext_id)), \ @@ -578,13 +579,12 @@ struct flash_info { =20 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors) \ SPI_NOR_ID6((_jedec_id), (_ext_id)), \ - SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 1), + SPI_NOR_GEOMETRY((_sector_size), (_n_sectors), 0), =20 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_nbytes) \ .size =3D (_sector_size) * (_n_sectors), \ .sector_size =3D (_sector_size), \ .page_size =3D (_page_size), \ - .n_banks =3D 1, \ .addr_nbytes =3D (_addr_nbytes), \ .flags =3D SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \ =20 diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 284e2e4970ab..8d4539e32dfe 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -26,7 +26,6 @@ .size =3D 8 * (_page_size) * (_n_sectors), \ .sector_size =3D (8 * (_page_size)), \ .page_size =3D (_page_size), \ - .n_banks =3D 1, \ .flags =3D SPI_NOR_NO_FR =20 /* Xilinx S3AN share MFR with Atmel SPI NOR */ --=20 2.39.2