From nobody Thu Sep 11 17:31:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B4AC001DF for ; Sun, 6 Aug 2023 16:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230457AbjHFQtB (ORCPT ); Sun, 6 Aug 2023 12:49:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbjHFQs7 (ORCPT ); Sun, 6 Aug 2023 12:48:59 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9758310CC; Sun, 6 Aug 2023 09:48:58 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 376Gml6q020260; Sun, 6 Aug 2023 11:48:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691340527; bh=7q6VvTj7zCInrnfOecFlb1jOVk+v0+/lH9T8gEC27a0=; h=From:To:Subject:Date:In-Reply-To:References; b=PlIkdbwCCBitgLEcbG6bW+AqL2eGfN+3hG3ZwN/okpcRnhY5acEylVNuPqEfH04qG M9RiKD+lCH4AhkkMmhpuwCLEUBVLCe6LWznvXyngtCnwMD93Bed3HngG1vHn5feXP5 ERlKXbgVn8evp4Zw6s0eoeXEW2SQKmsfE0UmghJg= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 376GmlfS086824 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 6 Aug 2023 11:48:47 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 6 Aug 2023 11:48:46 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 6 Aug 2023 11:48:46 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 376GmdMY009591; Sun, 6 Aug 2023 11:48:43 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla Subject: [PATCH 1/3] arm64: dts: ti: k3-j784s4-main: Add bootph-pre-ram property for SPL nodes Date: Sun, 6 Aug 2023 22:18:36 +0530 Message-ID: <20230806164838.18088-2-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230806164838.18088-1-a-nandan@ti.com> References: <20230806164838.18088-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram property for all the nodes used in SPL stage, for syncing it later to u-boot j784s4 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index a04c44708a09..6bba73c8f359 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,6 +6,7 @@ */ =20 &cbass_main { + bootph-pre-ram; msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; reg =3D <0x00 0x70000000 0x00 0x800000>; @@ -670,6 +671,7 @@ main_sdhci1: mmc@4fb0000 { }; =20 main_navss: bus@30000000 { + bootph-pre-ram; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -705,6 +707,7 @@ main_udmass_inta: msi-controller@33d00000 { }; =20 secure_proxy_main: mailbox@32c00000 { + bootph-pre-ram; compatible =3D "ti,am654-secure-proxy"; #mbox-cells =3D <1>; reg-names =3D "target_data", "rt", "scfg"; --=20 2.34.1 From nobody Thu Sep 11 17:31:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40B7AC001B0 for ; Sun, 6 Aug 2023 16:49:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230459AbjHFQtG (ORCPT ); Sun, 6 Aug 2023 12:49:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbjHFQtD (ORCPT ); Sun, 6 Aug 2023 12:49:03 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87B4810CC; Sun, 6 Aug 2023 09:49:02 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 376GmoqL006533; Sun, 6 Aug 2023 11:48:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691340530; bh=gOgHxaFNknEPQkRXnHJvFNHYD58prAaSGp1BrvLOPEk=; h=From:To:Subject:Date:In-Reply-To:References; b=uWYxqcmIsoDOx1z1lqYdTbwRTW/mkX01LbIKzSOm+Wq7aukLtQrDc0X3QsYIlfbcU rK/4Rgt3ZSLcFRkmBFfMWkBT4NCphD7Uw0YkoIOXHDA83ZyxHx64szTA250fuQcsF4 8v6EQazIvpqSV/Ngf9SAbbWs8Fo/GC6QC7vUFabU= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 376Gmodx086835 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 6 Aug 2023 11:48:50 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 6 Aug 2023 11:48:50 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 6 Aug 2023 11:48:50 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 376GmdMZ009591; Sun, 6 Aug 2023 11:48:47 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla Subject: [PATCH 2/3] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add bootph-pre-ram property for SPL nodes Date: Sun, 6 Aug 2023 22:18:37 +0530 Message-ID: <20230806164838.18088-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230806164838.18088-1-a-nandan@ti.com> References: <20230806164838.18088-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram property for all the nodes used in SPL stage, for syncing it later to u-boot j784s4 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..57bf0261c343 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -6,7 +6,9 @@ */ =20 &cbass_mcu_wakeup { + bootph-pre-ram; sms: system-controller@44083000 { + bootph-pre-ram; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; =20 @@ -19,22 +21,26 @@ sms: system-controller@44083000 { reg =3D <0x00 0x44083000 0x00 0x1000>; =20 k3_pds: power-controller { + bootph-pre-ram; compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; }; =20 k3_clks: clock-controller { + bootph-pre-ram; compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; }; =20 k3_reset: reset-controller { + bootph-pre-ram; compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; }; }; =20 chipid@43000014 { + bootph-pre-ram; compatible =3D "ti,am654-chipid"; reg =3D <0x00 0x43000014 0x00 0x4>; }; @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 { }; =20 mcu_navss: bus@28380000 { + bootph-pre-ram; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 { dma-ranges; =20 mcu_ringacc: ringacc@2b800000 { + bootph-pre-ram; compatible =3D "ti,am654-navss-ringacc"; reg =3D <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 { }; =20 mcu_udmap: dma-controller@285c0000 { + bootph-pre-ram; compatible =3D "ti,j721e-navss-mcu-udmap"; reg =3D <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, --=20 2.34.1 From nobody Thu Sep 11 17:31:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E78CC001DF for ; Sun, 6 Aug 2023 16:49:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230208AbjHFQtO (ORCPT ); Sun, 6 Aug 2023 12:49:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbjHFQtK (ORCPT ); Sun, 6 Aug 2023 12:49:10 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A020F1733; Sun, 6 Aug 2023 09:49:05 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 376Gmsej006540; Sun, 6 Aug 2023 11:48:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691340534; bh=JPRORifvGrUrwDZIN/iGzlfeEl6AVt2arl7a65Q6VzE=; h=From:To:Subject:Date:In-Reply-To:References; b=WLA6OcoXxT+uCPp3wZFmohvOketKmXWuIdGkHD/QtmcI1xosngtp69dCOlwLOI8r4 zJ9cVJyneexZuSLiBXfk9nXk1vpBtvhBJJuT3SBmhymsoBSMlVisZfevnB1vfG+OjA 15/a/ncV+YYjuo2GpN04rOwVEpjb+BnEdrolMNwE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 376GmsXM074078 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 6 Aug 2023 11:48:54 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 6 Aug 2023 11:48:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 6 Aug 2023 11:48:53 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 376GmdMa009591; Sun, 6 Aug 2023 11:48:50 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla Subject: [PATCH 3/3] arm64: dts: ti: k3-j784s4-evm: Add bootph-pre-ram property for SPL nodes Date: Sun, 6 Aug 2023 22:18:38 +0530 Message-ID: <20230806164838.18088-4-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230806164838.18088-1-a-nandan@ti.com> References: <20230806164838.18088-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram property for all the nodes used in SPL stage, for syncing it later to u-boot j784s4 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 1e38a8f1bec5..12455baf68b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; =20 &main_pmx0 { + bootph-pre-ram; main_uart8_pins_default: main-uart8-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.G= PIO0_8 */ }; =20 &wkup_pmx2 { + bootph-pre-ram; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC= 1_AIN7 */ }; =20 &wkup_pmx0 { + bootph-pre-ram; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -385,6 +394,7 @@ J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OS= PI0_CSn2.MCU_OSPI0_RESET_ }; =20 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -399,6 +409,7 @@ J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSP= I1_LBCLKO */ }; =20 &wkup_uart0 { + bootph-pre-ram; /* Firmware usage */ status =3D "reserved"; pinctrl-names =3D "default"; @@ -406,6 +417,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-pre-ram; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -419,12 +431,14 @@ eeprom@50 { }; =20 &mcu_uart0 { + bootph-pre-ram; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; }; =20 &main_uart8 { + bootph-pre-ram; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -435,15 +449,18 @@ &ufs_wrapper { }; =20 &fss { + bootph-pre-ram; status =3D "okay"; }; =20 &ospi0 { + bootph-pre-ram; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 flash@0 { + bootph-pre-ram; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <8>; @@ -491,6 +508,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-pre-ram; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -499,11 +517,13 @@ partition@3fc0000 { }; =20 &ospi1 { + bootph-pre-ram; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; =20 flash@0 { + bootph-pre-ram; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <1>; @@ -551,6 +571,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-pre-ram; label =3D "qspi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -595,6 +616,7 @@ exp2: gpio@22 { }; =20 &main_sdhci0 { + bootph-pre-ram; /* eMMC */ status =3D "okay"; non-removable; @@ -603,6 +625,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-pre-ram; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1