From nobody Thu Sep 11 16:41:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F50C001DB for ; Sat, 5 Aug 2023 07:07:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbjHEHH0 (ORCPT ); Sat, 5 Aug 2023 03:07:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229655AbjHEHHV (ORCPT ); Sat, 5 Aug 2023 03:07:21 -0400 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E7103C2D for ; Sat, 5 Aug 2023 00:07:20 -0700 (PDT) Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 37576ouK013850; Sat, 5 Aug 2023 15:06:50 +0800 (+08) (envelope-from zhifeng.tang@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4RHtrF5HV0z2K1r9q; Sat, 5 Aug 2023 15:05:01 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 5 Aug 2023 15:06:48 +0800 From: Zhifeng Tang To: Michael Turquette , Stephen Boyd , Orson Zhai , Baolin Wang , Chunyan Zhang , Zhifeng Tang , Cixi Geng , Maxime Ripard CC: , , Zhifeng Tang , Wenming Wu Subject: [PATCH] clk: sprd: Composite driver support offset config Date: Sat, 5 Aug 2023 15:06:43 +0800 Message-ID: <20230805070643.30705-1-zhifeng.tang@unisoc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.13.2.29] X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx04.spreadtrum.com (10.0.1.214) X-MAIL: SHSQR01.spreadtrum.com 37576ouK013850 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The composite interface support the offset configuration, which is userd to support mux and div in different registers. Signed-off-by: Zhifeng Tang --- drivers/clk/sprd/composite.h | 38 +++++++++++++++++++++++++----------- drivers/clk/sprd/div.c | 6 +++--- drivers/clk/sprd/div.h | 17 +++++++++++----- 3 files changed, 42 insertions(+), 19 deletions(-) diff --git a/drivers/clk/sprd/composite.h b/drivers/clk/sprd/composite.h index adbabbe596b7..74765584021d 100644 --- a/drivers/clk/sprd/composite.h +++ b/drivers/clk/sprd/composite.h @@ -19,24 +19,24 @@ struct sprd_comp { }; =20 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ - _mshift, _mwidth, _dshift, _dwidth, \ - _flags, _fn) \ + _mshift, _mwidth, _doffset, _dshift, \ + _dwidth, _flags, _fn) \ struct sprd_comp _struct =3D { \ .mux =3D _SPRD_MUX_CLK(_mshift, _mwidth, _table), \ - .div =3D _SPRD_DIV_CLK(_dshift, _dwidth), \ + .div =3D _SPRD_DIV_CLK(_doffset, _dshift, _dwidth), \ .common =3D { \ .regmap =3D NULL, \ .reg =3D _reg, \ .hw.init =3D _fn(_name, _parent, \ &sprd_comp_ops, _flags), \ - } \ + } \ } =20 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ _mshift, _mwidth, _dshift, _dwidth, _flags) \ SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ - _mshift, _mwidth, _dshift, _dwidth, \ - _flags, CLK_HW_INIT_PARENTS) + _mshift, _mwidth, 0x0, _dshift, \ + _dwidth, _flags, CLK_HW_INIT_PARENTS) =20 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ _mwidth, _dshift, _dwidth, _flags) \ @@ -47,14 +47,30 @@ struct sprd_comp { _mshift, _mwidth, _dshift, \ _dwidth, _flags) \ SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ - _mshift, _mwidth, _dshift, _dwidth, \ - _flags, CLK_HW_INIT_PARENTS_DATA) + _mshift, _mwidth, 0x0, _dshift, \ + _dwidth, _flags, \ + CLK_HW_INIT_PARENTS_DATA) =20 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ _mwidth, _dshift, _dwidth, _flags) \ - SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \ - _mshift, _mwidth, _dshift, _dwidth, \ - _flags) + SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \ + _mshift, _mwidth, _dshift, \ + _dwidth, _flags) + +#define SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct, _name, _parent, _reg, \ + _table, _mshift, _mwidth, \ + _dshift, _dwidth, _flags) \ + SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ + _mshift, _mwidth, 0x4, _dshift, \ + _dwidth, _flags, \ + CLK_HW_INIT_PARENTS_DATA) + +#define SPRD_COMP_CLK_DATA_OFFSET(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _dshift, \ + _dwidth, _flags) \ + SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct, _name, _parent, _reg, \ + NULL, _mshift, _mwidth, \ + _dshift, _dwidth, _flags) =20 static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw) { diff --git a/drivers/clk/sprd/div.c b/drivers/clk/sprd/div.c index c7261630cab4..0fb41d653f1e 100644 --- a/drivers/clk/sprd/div.c +++ b/drivers/clk/sprd/div.c @@ -25,7 +25,7 @@ unsigned long sprd_div_helper_recalc_rate(struct sprd_clk= _common *common, unsigned long val; unsigned int reg; =20 - regmap_read(common->regmap, common->reg, ®); + regmap_read(common->regmap, common->reg - div->offset, ®); val =3D reg >> div->shift; val &=3D (1 << div->width) - 1; =20 @@ -53,10 +53,10 @@ int sprd_div_helper_set_rate(const struct sprd_clk_comm= on *common, val =3D divider_get_val(rate, parent_rate, NULL, div->width, 0); =20 - regmap_read(common->regmap, common->reg, ®); + regmap_read(common->regmap, common->reg - div->offset, ®); reg &=3D ~GENMASK(div->width + div->shift - 1, div->shift); =20 - regmap_write(common->regmap, common->reg, + regmap_write(common->regmap, common->reg - div->offset, reg | (val << div->shift)); =20 return 0; diff --git a/drivers/clk/sprd/div.h b/drivers/clk/sprd/div.h index f5d614b3dcf1..db6b62ee6a8d 100644 --- a/drivers/clk/sprd/div.h +++ b/drivers/clk/sprd/div.h @@ -20,12 +20,14 @@ * classes. */ struct sprd_div_internal { + u32 offset; u8 shift; u8 width; }; =20 -#define _SPRD_DIV_CLK(_shift, _width) \ +#define _SPRD_DIV_CLK(_offset, _shift, _width) \ { \ + .offset =3D _offset, \ .shift =3D _shift, \ .width =3D _width, \ } @@ -35,10 +37,10 @@ struct sprd_div { struct sprd_clk_common common; }; =20 -#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ +#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ _shift, _width, _flags, _fn) \ struct sprd_div _struct =3D { \ - .div =3D _SPRD_DIV_CLK(_shift, _width), \ + .div =3D _SPRD_DIV_CLK(_offset, _shift, _width), \ .common =3D { \ .regmap =3D NULL, \ .reg =3D _reg, \ @@ -49,12 +51,17 @@ struct sprd_div { =20 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ _shift, _width, _flags) \ - SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \ _shift, _width, _flags, CLK_HW_INIT) =20 +#define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \ + _shift, _width, _flags) \ + SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \ + _shift, _width, _flags, CLK_HW_INIT_FW_NAME) + #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ _shift, _width, _flags) \ - SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \ _shift, _width, _flags, CLK_HW_INIT_HW) =20 static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw) --=20 2.17.1