From nobody Thu Sep 11 16:41:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F0D0EB64DD for ; Sat, 5 Aug 2023 06:49:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229648AbjHEGtH (ORCPT ); Sat, 5 Aug 2023 02:49:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229570AbjHEGtD (ORCPT ); Sat, 5 Aug 2023 02:49:03 -0400 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6676412E for ; Fri, 4 Aug 2023 23:48:59 -0700 (PDT) Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3756mPhO000242; Sat, 5 Aug 2023 14:48:25 +0800 (+08) (envelope-from zhifeng.tang@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4RHtR10WMGz2MxJxw; Sat, 5 Aug 2023 14:46:37 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 5 Aug 2023 14:48:24 +0800 From: Zhifeng Tang To: Michael Turquette , Stephen Boyd , Orson Zhai , Baolin Wang , Chunyan Zhang , Zhifeng Tang , Cixi Geng CC: , , Zhifeng Tang , Wenming Wu Subject: [PATCH] clk: sprd: Fix thm_parents incorrect configuration Date: Sat, 5 Aug 2023 14:48:20 +0800 Message-ID: <20230805064820.30305-1-zhifeng.tang@unisoc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.13.2.29] X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx04.spreadtrum.com (10.0.1.214) X-MAIL: SHSQR01.spreadtrum.com 3756mPhO000242 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The thm*_clk have two clock sources 32k and 250k,excluding 32m. Signed-off-by: Zhifeng Tang Acked-by: Chunyan Zhang Reviewed-by: Baolin Wang --- drivers/clk/sprd/ums512-clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c index fc25bdd85e4e..f43bb10bd5ae 100644 --- a/drivers/clk/sprd/ums512-clk.c +++ b/drivers/clk/sprd/ums512-clk.c @@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_p= arents, 0x250, 0, 3, UMS512_MUX_FLAG); =20 static const struct clk_parent_data thm_parents[] =3D { - { .fw_name =3D "ext-32m" }, + { .fw_name =3D "ext-32k" }, { .hw =3D &clk_250k.hw }, }; static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents, --=20 2.17.1