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[83.9.32.15]) by smtp.gmail.com with ESMTPSA id f2-20020ac251a2000000b004fbac2646e3sm739453lfk.195.2023.08.05.05.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Aug 2023 05:25:58 -0700 (PDT) From: Konrad Dybcio Date: Sat, 05 Aug 2023 14:25:58 +0200 Subject: [PATCH] arm64: dts: qcom: msm8998: Add DPU1 nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230805-topic-8998_dpu-v1-1-0da18d4a3453@linaro.org> X-B4-Tracking: v=1; b=H4sIANU/zmQC/x2N0QqEIBAAfyX2uQWzAr1fOSJMt1oIE604iP79l h5nYJgbCmWmAp/qhkwXF96jQFNX4FcXF0IOwqCVbpVRPR57Yo/GWjOGdGIzB9MG3ZGzHiSaXCG csot+lSye2yYyZZr5916+w/P8ASNpk9Z1AAAA To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1691238358; l=7663; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UgDVEyH7951UxBCmRrbMHbDiHfODaWA2DozHQ31ai1E=; b=oaMdOg84PefTay5/oS2KyTCTcl4JfSkad0sY0atPkxRP4aESu78/rMk4ABAVv+tFN591JL2FT mOuHwxLlAxJD3Nu1oS5/OBp0e25wCITczfjw9vhz55SpYSajehCu1di X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: AngeloGioacchino Del Regno Add the required nodes to support the display hardware on msm8998. Signed-off-by: AngeloGioacchino Del Regno [konrad: update the commit msg and AGdR's email, rebase] Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 283 ++++++++++++++++++++++++++++++= +++- 1 file changed, 279 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index a41a34dbcc3c..e28c5bbc99e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -316,6 +316,25 @@ scm { }; }; =20 + dsi_opp_table: opp-table-dsi { + compatible =3D "operating-points-v2"; + + opp-131250000 { + opp-hz =3D /bits/ 64 <131250000>; + required-opps =3D <&rpmpd_opp_low_svs>; + }; + + opp-210000000 { + opp-hz =3D /bits/ 64 <210000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; @@ -2727,15 +2746,271 @@ mmcc: clock-controller@c8c0000 { "dpvco"; clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, - <0>, - <0>, - <0>, - <0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>; }; =20 + mdss: display-subsystem@c900000 { + compatible =3D "qcom,msm8998-mdss"; + reg =3D <0x0c900000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names =3D "iface", + "bus", + "core"; + + power-domains =3D <&mmcc MDSS_GDSC>; + iommus =3D <&mmss_smmu 0>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@c901000 { + compatible =3D "qcom,msm8998-dpu"; + reg =3D <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names =3D "mdp", + "regdma", + "vbif", + "vbif_nrt"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "mnoc", + "core", + "vsync"; + + assigned-clocks =3D <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd MSM8998_VDDMX>; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-171430000 { + opp-hz =3D /bits/ 64 <171430000>; + required-opps =3D <&rpmpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz =3D /bits/ 64 <275000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-330000000 { + opp-hz =3D /bits/ 64 <330000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-412500000 { + opp-hz =3D /bits/ 64 <412500000>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@c994000 { + compatible =3D "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0c994000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks =3D <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd MSM8998_VDDCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@c994400 { + compatible =3D "qcom,dsi-phy-10nm-8998"; + reg =3D <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@c996000 { + compatible =3D "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0c996000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks =3D <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd MSM8998_VDDCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@c996400 { + compatible =3D "qcom,dsi-phy-10nm-8998"; + reg =3D <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + mmss_smmu: iommu@cd00000 { compatible =3D "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg =3D <0x0cd00000 0x40000>; --- base-commit: bdffb18b5dd8071cd25685b966f380a30b1fadaa change-id: 20230805-topic-8998_dpu-1fd83d24ea9c Best regards, --=20 Konrad Dybcio