From nobody Thu Sep 11 16:38:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47273C04A94 for ; Fri, 4 Aug 2023 10:14:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231345AbjHDKOa (ORCPT ); Fri, 4 Aug 2023 06:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231352AbjHDKN5 (ORCPT ); Fri, 4 Aug 2023 06:13:57 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D87C94C27 for ; Fri, 4 Aug 2023 03:13:45 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 524F8113E; Fri, 4 Aug 2023 03:14:28 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.3.154]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D5AF93F6C4; Fri, 4 Aug 2023 03:13:42 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: James Clark , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/3] arm64: KVM: Add support for exclude_guest and exclude_host for ETM Date: Fri, 4 Aug 2023 11:13:11 +0100 Message-Id: <20230804101317.460697-2-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804101317.460697-1-james.clark@arm.com> References: <20230804101317.460697-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add an interface for the Coresight driver to use to set the current exclude settings for the current CPU. This will be used to configure TRFCR_EL1. The settings must be copied to the vCPU before each run in the same way that PMU events are because the per-cpu struct isn't accessible in protected mode. This is only needed for nVHE, otherwise it works automatically with TRFCR_EL{1,2}. Unfortunately it can't be gated on CONFIG_CORESIGHT because Coresight can be built as a module. It can however be gated on CONFIG_PERF_EVENTS because that is required by Coresight. Signed-off-by: James Clark --- arch/arm64/include/asm/kvm_host.h | 10 ++++++- arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/etm.c | 48 +++++++++++++++++++++++++++++++ include/kvm/etm.h | 43 +++++++++++++++++++++++++++ 5 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/kvm/etm.c create mode 100644 include/kvm/etm.h diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index d7b1403a3fb2..f33262217c84 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -35,6 +35,7 @@ #include #include #include +#include =20 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS =20 @@ -500,7 +501,7 @@ struct kvm_vcpu_arch { u8 cflags; =20 /* Input flags to the hypervisor code, potentially cleared after use */ - u8 iflags; + u16 iflags; =20 /* State flags for kernel bookkeeping, unused by the hypervisor code */ u8 sflags; @@ -541,6 +542,9 @@ struct kvm_vcpu_arch { u64 pmscr_el1; /* Self-hosted trace */ u64 trfcr_el1; + /* exclude_guest settings for nVHE */ + struct kvm_etm_event etm_event; + } host_debug_state; =20 /* VGIC state */ @@ -713,6 +717,8 @@ struct kvm_vcpu_arch { #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) /* vcpu running in HYP context */ #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) +/* Save TRFCR and apply exclude_guest rules */ +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(8)) =20 /* SVE enabled for host EL0 */ #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) @@ -1096,6 +1102,8 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_v= cpu *vcpu); void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); void kvm_clr_pmu_events(u32 clr); bool kvm_set_pmuserenr(u64 val); +void kvm_set_etm_events(struct perf_event_attr *attr); +void kvm_clr_etm_events(void); #else static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *att= r) {} static inline void kvm_clr_pmu_events(u32 clr) {} diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index c0c050e53157..0faff57423c4 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -23,6 +23,7 @@ kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.= o \ vgic/vgic-its.o vgic/vgic-debug.o =20 kvm-$(CONFIG_HW_PERF_EVENTS) +=3D pmu-emul.o pmu.o +kvm-$(CONFIG_PERF_EVENTS) +=3D etm.o =20 always-y :=3D hyp_constants.h hyp-constants.s =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b1a9d47fb2f3..7bd5975328a3 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -952,6 +952,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) kvm_vgic_flush_hwstate(vcpu); =20 kvm_pmu_update_vcpu_events(vcpu); + kvm_etm_update_vcpu_events(vcpu); =20 /* * Ensure we set mode to IN_GUEST_MODE after we disable diff --git a/arch/arm64/kvm/etm.c b/arch/arm64/kvm/etm.c new file mode 100644 index 000000000000..359c37745de2 --- /dev/null +++ b/arch/arm64/kvm/etm.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +#include + +static DEFINE_PER_CPU(struct kvm_etm_event, kvm_etm_events); + +struct kvm_etm_event *kvm_get_etm_event(void) +{ + return this_cpu_ptr(&kvm_etm_events); +} + +void kvm_etm_set_events(struct perf_event_attr *attr) +{ + struct kvm_etm_event *etm_event; + + /* + * Exclude guest option only requires extra work with nVHE. + * Otherwise it works automatically with TRFCR_EL{1,2} + */ + if (has_vhe()) + return; + + etm_event =3D kvm_get_etm_event(); + + etm_event->exclude_guest =3D attr->exclude_guest; + etm_event->exclude_host =3D attr->exclude_host; + etm_event->exclude_kernel =3D attr->exclude_kernel; + etm_event->exclude_user =3D attr->exclude_user; +} +EXPORT_SYMBOL_GPL(kvm_etm_set_events); + +void kvm_etm_clr_events(void) +{ + struct kvm_etm_event *etm_event; + + if (has_vhe()) + return; + + etm_event =3D kvm_get_etm_event(); + + etm_event->exclude_guest =3D false; + etm_event->exclude_host =3D false; + etm_event->exclude_kernel =3D false; + etm_event->exclude_user =3D false; +} +EXPORT_SYMBOL_GPL(kvm_etm_clr_events); diff --git a/include/kvm/etm.h b/include/kvm/etm.h new file mode 100644 index 000000000000..95c4809fa2b0 --- /dev/null +++ b/include/kvm/etm.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __KVM_DEBUG_H +#define __KVM_DEBUG_H + +struct perf_event_attr; +struct kvm_vcpu; + +#if IS_ENABLED(CONFIG_KVM) && IS_ENABLED(CONFIG_PERF_EVENTS) + +struct kvm_etm_event { + bool exclude_host; + bool exclude_guest; + bool exclude_kernel; + bool exclude_user; +}; + +struct kvm_etm_event *kvm_get_etm_event(void); +void kvm_etm_clr_events(void); +void kvm_etm_set_events(struct perf_event_attr *attr); + +/* + * Updates the vcpu's view of the etm events for this cpu. Must be + * called before every vcpu run after disabling interrupts, to ensure + * that an interrupt cannot fire and update the structure. + */ +#define kvm_etm_update_vcpu_events(vcpu) \ + do { \ + if (!has_vhe() && vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRFCR)) \ + vcpu->arch.host_debug_state.etm_event =3D *kvm_get_etm_event(); \ + } while (0) + +#else + +struct kvm_etm_event {}; + +static inline void kvm_etm_update_vcpu_events(struct kvm_vcpu *vcpu) {} +static inline void kvm_etm_set_events(struct perf_event_attr *attr) {} +static inline void kvm_etm_clr_events(void) {} + +#endif + +#endif --=20 2.34.1 From nobody Thu Sep 11 16:38:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2493DC001DB for ; Fri, 4 Aug 2023 10:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbjHDKOg (ORCPT ); Fri, 4 Aug 2023 06:14:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231395AbjHDKN7 (ORCPT ); Fri, 4 Aug 2023 06:13:59 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 50B5446AC for ; Fri, 4 Aug 2023 03:13:52 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA8D81007; Fri, 4 Aug 2023 03:14:34 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.3.154]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4AC883F6C4; Fri, 4 Aug 2023 03:13:49 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: James Clark , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/3] arm64: KVM: Support exclude_guest for Coresight trace in nVHE Date: Fri, 4 Aug 2023 11:13:12 +0100 Message-Id: <20230804101317.460697-3-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804101317.460697-1-james.clark@arm.com> References: <20230804101317.460697-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently trace will always be generated in nVHE as long as TRBE isn't being used. To allow filtering out guest trace, re-apply the filter rules before switching to the guest. The TRFCR restore function remains the same. Signed-off-by: James Clark --- arch/arm64/kvm/debug.c | 7 ++++ arch/arm64/kvm/hyp/nvhe/debug-sr.c | 56 +++++++++++++++++++++++++++--- 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 8725291cb00a..ebb4db20a859 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -335,10 +335,17 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_= vcpu *vcpu) if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffe= r_SHIFT) && !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P)) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + /* + * Save TRFCR on nVHE if FEAT_TRF exists. This will be done in cases + * where DEBUG_STATE_SAVE_TRBE doesn't completely disable trace. + */ + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_= SHIFT)) + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); } =20 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) { vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE); vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); + vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); } diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/d= ebug-sr.c index 4558c02eb352..0e8c85b29b92 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -51,13 +51,17 @@ static void __debug_restore_spe(u64 pmscr_el1) write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); } =20 -static void __debug_save_trace(u64 *trfcr_el1) +/* + * Save TRFCR and disable trace completely if TRBE is being used. Return t= rue + * if trace was disabled. + */ +static bool __debug_save_trace(u64 *trfcr_el1) { *trfcr_el1 =3D 0; =20 /* Check if the TRBE is enabled */ if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_E)) - return; + return false; /* * Prohibit trace generation while we are in guest. * Since access to TRFCR_EL1 is trapped, the guest can't @@ -68,6 +72,8 @@ static void __debug_save_trace(u64 *trfcr_el1) isb(); /* Drain the trace buffer to memory */ tsb_csync(); + + return true; } =20 static void __debug_restore_trace(u64 trfcr_el1) @@ -79,14 +85,55 @@ static void __debug_restore_trace(u64 trfcr_el1) write_sysreg_s(trfcr_el1, SYS_TRFCR_EL1); } =20 +#if IS_ENABLED(CONFIG_PERF_EVENTS) +static inline void __debug_save_trfcr(struct kvm_vcpu *vcpu) +{ + u64 trfcr; + struct kvm_etm_event etm_event =3D vcpu->arch.host_debug_state.etm_event; + + /* No change if neither are excluded */ + if (!etm_event.exclude_guest && !etm_event.exclude_host) { + /* Zeroing prevents restoring a stale value */ + vcpu->arch.host_debug_state.trfcr_el1 =3D 0; + return; + } + + trfcr =3D read_sysreg_s(SYS_TRFCR_EL1); + vcpu->arch.host_debug_state.trfcr_el1 =3D trfcr; + + if (etm_event.exclude_guest) { + trfcr &=3D ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE); + } else { + /* + * If host was excluded then EL0 and ELx tracing bits will + * already be cleared so they need to be set now for the guest. + */ + trfcr |=3D etm_event.exclude_kernel ? 0 : TRFCR_ELx_ExTRE; + trfcr |=3D etm_event.exclude_user ? 0 : TRFCR_ELx_E0TRE; + } + write_sysreg_s(trfcr, SYS_TRFCR_EL1); +} +#else +static inline void __debug_save_trfcr(struct kvm_vcpu *vcpu) {} +#endif + void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) { + bool trc_disabled =3D false; + /* Disable and flush SPE data generation */ if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_SPE)) __debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1); /* Disable and flush Self-Hosted Trace generation */ if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRBE)) - __debug_save_trace(&vcpu->arch.host_debug_state.trfcr_el1); + trc_disabled =3D __debug_save_trace(&vcpu->arch.host_debug_state.trfcr_e= l1); + + /* + * As long as trace wasn't completely disabled due to use of TRBE, + * TRFCR can be saved and the exclude_guest rules applied. + */ + if (!trc_disabled && vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRFCR)) + __debug_save_trfcr(vcpu); } =20 void __debug_switch_to_guest(struct kvm_vcpu *vcpu) @@ -98,7 +145,8 @@ void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *= vcpu) { if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_SPE)) __debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1); - if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRBE)) + if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRBE) || + vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRFCR)) __debug_restore_trace(vcpu->arch.host_debug_state.trfcr_el1); } =20 --=20 2.34.1 From nobody Thu Sep 11 16:38:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA75FC001DB for ; Fri, 4 Aug 2023 10:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231449AbjHDKO6 (ORCPT ); Fri, 4 Aug 2023 06:14:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230288AbjHDKOC (ORCPT ); Fri, 4 Aug 2023 06:14:02 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AD52149D4 for ; Fri, 4 Aug 2023 03:13:58 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3146C1007; Fri, 4 Aug 2023 03:14:41 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.3.154]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A9FDE3F6C4; Fri, 4 Aug 2023 03:13:55 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: James Clark , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/3] coresight: Support exclude_guest with Feat_TRF and nVHE Date: Fri, 4 Aug 2023 11:13:13 +0100 Message-Id: <20230804101317.460697-4-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804101317.460697-1-james.clark@arm.com> References: <20230804101317.460697-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With nVHE the filters need to be applied before switching to the guest, so supply the per-cpu filter status to KVM. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 5ca6278baff4..f78f05e656f5 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -510,6 +511,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) } =20 out: + kvm_etm_set_events(&event->attr); /* Tell the perf core the event is alive */ event->hw.state =3D 0; /* Save the event_data for this ETM */ @@ -627,6 +629,8 @@ static void etm_event_stop(struct perf_event *event, in= t mode) =20 /* Disabling the path make its elements available to other sessions */ coresight_disable_path(path); + + kvm_etm_clr_events(); } =20 static int etm_event_add(struct perf_event *event, int mode) --=20 2.34.1