From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB4E1C04FE1 for ; Thu, 3 Aug 2023 11:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235467AbjHCLCq (ORCPT ); Thu, 3 Aug 2023 07:02:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233582AbjHCLC1 (ORCPT ); Thu, 3 Aug 2023 07:02:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB27930F4 for ; Thu, 3 Aug 2023 04:02:23 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D9FD1660719B; Thu, 3 Aug 2023 12:02:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060542; bh=yEFNmriytfzFlnNR03nQnEhTvtOxc2/EEUJg2NG5628=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UsG8V28tw0bigg1Ek2Tuh5EPudg0RlK7ykhFerJorw4zwzz4SYnZh6+hdJFUPwss4 jZPanH64D7lsc8s9LeGB3MtmvUI/lyCsFJE5tq91ZOcAi4I0XRVbOXUxJLvGtuu1sV dzLNsMjsCvAxAdNL613mUR64D53hfL2vq1wdGaNPaVSAGGsL5jQNIEKxnnHD36Q46P MgDj0TrG2dOrd8XkRd/SYV4hOXpgUkiT/56loUFzaAgWN9QH8tHLuTPVACJ2UUwwH5 9YEKbX+KV4HftdvanyAUoUx3lWOUNyd4FQmNmKppKe+AI8gtcZo8J76DH43u20NHQT I0K9qdXgpE/eg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH.Lin" , Alexandre Mergnat Subject: [PATCH v9 01/16] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Thu, 3 Aug 2023 13:01:59 +0200 Message-ID: <20230803110214.163645-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index cdbec79474d1..2f602f1f1c49 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -66,7 +66,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state) struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); =20 if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } =20 void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 7746dceadb20..d42cc0698d83 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,24 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { + struct mtk_disp_gamma *gamma; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] =3D {0}; =20 + /* If we're called from AAL, dev is NULL */ + gamma =3D dev ? dev_get_drvdata(dev) : NULL; + + if (gamma && gamma->data) + lut_diff =3D gamma->data->lut_diff; + else + lut_diff =3D false; + if (state->gamma_lut) { reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; @@ -91,12 +101,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct dr= m_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - bool lut_diff =3D false; - - if (gamma->data) - lut_diff =3D gamma->data->lut_diff; =20 - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } =20 void mtk_gamma_config(struct device *dev, unsigned int w, --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3405BC04FDF for ; Thu, 3 Aug 2023 11:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235555AbjHCLCt (ORCPT ); Thu, 3 Aug 2023 07:02:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233912AbjHCLC1 (ORCPT ); Thu, 3 Aug 2023 07:02:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA2B530F6 for ; Thu, 3 Aug 2023 04:02:24 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BD76E660719C; Thu, 3 Aug 2023 12:02:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060543; bh=kYeyT6HbEedO1YRPTVJsJxzagOYrnms3xwsfF+B40oU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=diQZ8P0l8FqvcczN2RTKnkHQ20mXn44WWkOxNNT9HOIxcalQ484QtQ1rcu+bapUiR x+FWJ2medcWhshtqESAIZLqW56EEF6XREqrzUp8lG+vgq33amBHx1zo0cx7qvXf8kC /gmeW9zAuV5XgiQQp557oT9aKeHdB4dXG5P4Ye2LBmjBAZpigH13t2Xb4Z2SnsNcE0 MYrotTwKwiCPXQ4mOTNVoAc7gFv5mFkujkrmU2etFqhLfsEHB9l0egShi9Cp7vIpZt F6Cv+7cvL9bL8tWy8+aDxQHcfeS8yEr0xYn+XsMAWsB07VNqb50/aaDzYwvwqGZ1ht 6pcRRloHaZutg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 02/16] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Thu, 3 Aug 2023 13:02:00 +0200 Message-ID: <20230803110214.163645-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index d42cc0698d83..47751864bd5c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -64,6 +64,10 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt u32 word; u32 diff[3] =3D {0}; =20 + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + /* If we're called from AAL, dev is NULL */ gamma =3D dev ? dev_get_drvdata(dev) : NULL; =20 @@ -72,29 +76,26 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt else lut_diff =3D false; =20 - if (state->gamma_lut) { - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; - lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg =3D readl(regs + DISP_GAMMA_CFG); + reg =3D reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base =3D regs + DISP_GAMMA_LUT; + lut =3D (struct drm_color_lut *)state->gamma_lut->data; + for (i =3D 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } =20 --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32927C04E69 for ; Thu, 3 Aug 2023 11:03:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235606AbjHCLCz (ORCPT ); Thu, 3 Aug 2023 07:02:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233948AbjHCLC1 (ORCPT ); Thu, 3 Aug 2023 07:02:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 917E0359A for ; Thu, 3 Aug 2023 04:02:25 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A1631660719E; Thu, 3 Aug 2023 12:02:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060544; bh=dRCUBSAJhyuAuYLj+KM0no1asegc1IsekM6rzVKVlw8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jl6O7GZCo/w4f1Kp/RTd/QO8PVforqsFak9FrtxEtuXpgXdhLwyppECX/oD8RR8Fo 86rvS5ZTtSqYL9UElpiCDEEtYXUgeBv5Umm7tYGw5SlTA9ngqS/Yr8djQKjZ6rj2ov Yy62Lsyh/s07vOICQNYsB2HLSfd78tDxJZE9gBARABoW+5ghLBcZ/qPVoNx7swTF7G nmG0VW2bxuTib/ZV6vI/gIapztlVA9dAxF3cgHSUw2uoGw+jJZ9suNU8bwOfVnhYzt 6GkIHgqCFCG2swFUw2S5SS0tvXdM5am3P3ir/XznmS7OBjExSR6/Iv02mcEjr59FIk u8iqaDcOFS8pw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 03/16] drm/mediatek: gamma: Support SoC specific LUT size Date: Thu, 3 Aug 2023 13:02:01 +0200 Message-ID: <20230803110214.163645-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 17 ++++++++++++++- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 23 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 +++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++++++++ 7 files changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 2f602f1f1c49..e2e4155faf01 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -19,7 +19,7 @@ #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_OUTPUT_SIZE 0x04d8 - +#define DISP_AAL_LUT_SIZE 512 =20 struct mtk_disp_aal_data { bool has_gamma; @@ -61,6 +61,21 @@ void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_= OUTPUT_SIZE); } =20 +/** + * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL + * @dev: Pointer to struct device + * + * Return: 0 if gamma control not supported in AAL or gamma LUT size + */ +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); + + if (aal->data && aal->data->has_gamma) + return DISP_AAL_LUT_SIZE; + return 0; +} + void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 75045932353e..ca377265e5eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,7 @@ void mtk_aal_clk_disable(struct device *dev); void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev); void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); @@ -53,6 +54,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 47751864bd5c..7575237625d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,10 +24,12 @@ #define DISP_GAMMA_LUT 0x0700 =20 #define LUT_10BIT_MASK 0x03ff +#define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; =20 /* @@ -54,6 +56,15 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + + if (gamma && gamma->data) + return gamma->data->lut_size; + return LUT_SIZE_DEFAULT; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma; @@ -61,6 +72,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u16 lut_size; u32 word; u32 diff[3] =3D {0}; =20 @@ -71,17 +83,20 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt /* If we're called from AAL, dev is NULL */ gamma =3D dev ? dev_get_drvdata(dev) : NULL; =20 - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; - else + lut_size =3D gamma->data->lut_size; + } else { lut_diff =3D false; + lut_size =3D LUT_SIZE_DEFAULT; + } =20 reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { + for (i =3D 0; i < lut_size; i++) { if (!lut_diff || (i % 2 =3D=3D 0)) { word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -198,10 +213,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { .lut_diff =3D true, + .lut_size =3D 512, }; =20 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index 8a43656ecc30..ebe0cc3a1a4c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -959,8 +959,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] =3D comp; =20 if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size =3D MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { + unsigned int lut_sz =3D mtk_ddp_gamma_get_lut_size(comp); + + if (lut_sz) + gamma_lut_size =3D lut_sz; + } =20 if (comp->funcs->ctm_set) has_ctm =3D true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" =20 -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index f114da4d36a9..f3212e08f2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -271,6 +271,7 @@ static void mtk_ufoe_start(struct device *dev) static const struct mtk_ddp_comp_funcs ddp_aal =3D { .clk_enable =3D mtk_aal_clk_enable, .clk_disable =3D mtk_aal_clk_disable, + .gamma_get_lut_size =3D mtk_aal_gamma_get_lut_size, .gamma_set =3D mtk_aal_gamma_set, .config =3D mtk_aal_config, .start =3D mtk_aal_start, @@ -322,6 +323,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi =3D { static const struct mtk_ddp_comp_funcs ddp_gamma =3D { .clk_enable =3D mtk_gamma_clk_enable, .clk_disable =3D mtk_gamma_clk_disable, + .gamma_get_lut_size =3D mtk_gamma_get_lut_size, .gamma_set =3D mtk_gamma_set, .config =3D mtk_gamma_config, .start =3D mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mt= k_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } =20 +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp = *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F8BAC04A94 for ; Thu, 3 Aug 2023 11:03:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235626AbjHCLC6 (ORCPT ); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TCGrTJgzddooAoaxRx+IbS/4+k6CR+JqLd+oMUiceQJJlsfp195iUWI/sJEIspuoD RXD5S9+3z2Iaj0dINZwuoeeOIztGdWV5GDxFYWacdigKFcPIblBuRnIkQ5KSEauyER TAWCjv/Ml1O6UXmh5LVNzNe/3nHboIXhk7jiX1pvwwoW5K+b/o7ulhbDIeEcMVByUJ hxKWTGQ32RLWKDJsALyc3ASko1DnG0kkQr2q9qspRkfVDDUuuEw4Z8yQTA4bjnwEgI lQRekvEJMKh9miSZBPrFb1FdctgYpOV0w/m4BpAAIFAxRC4N0UF0/nrcCLgJHFieTK TBlW3T3MtBpQA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 04/16] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Thu, 3 Aug 2023 13:02:02 +0200 Message-ID: <20230803110214.163645-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 7575237625d2..fd6a75a64a9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -74,7 +74,6 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt bool lut_diff; u16 lut_size; u32 word; - u32 diff[3] =3D {0}; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -97,18 +96,29 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); + hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word =3D hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red =3D lut[i].red - lut[i - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, 10); + + diff.green =3D lut[i].green - lut[i - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, 10); + + diff.blue =3D lut[i].blue - lut[i - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, 10); =20 - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word =3D diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81392C3DA40 for ; Thu, 3 Aug 2023 11:03:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235736AbjHCLDM (ORCPT ); Thu, 3 Aug 2023 07:03:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234881AbjHCLC3 (ORCPT ); Thu, 3 Aug 2023 07:02:29 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DF0730EA for ; Thu, 3 Aug 2023 04:02:28 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5F43366071A0; Thu, 3 Aug 2023 12:02:25 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060546; bh=jQ1ukxJYhgqz3VRiaaOzbMrQXLA2ENp1Hjs7vpajFxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l/u3vbOwy8Eea9VxnGCM+QJuc7g6GI9gnt7WTLuaItIbqLswCF1/icgiTSSaum7Lt lqfn5xDMOouKt6W7pzpUi0pUih+xJBwe2n80KeOhVU8UNYtIaAeO/HBV1Pzk5kr+nW AFhdHGuqIe8UdHkaeAjPii5SKaqu2IAbJXE6+FyoMOQvBrq1vLFm+FNYNBgH9wg0Q+ UGdkbORjio8oCW3+gHcBZK084UQ95lnuNSQhP92KiSjU1Ne1L4PwJWuYsZNUUoaxC6 zpMQjX6pLWrLUlSuW0QkgxpxULXIVgCa8oCs8tghfH1pFkz4qvlUTm/2q7rYMkQvhj Yyk3Jx273gqWg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 05/16] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Thu, 3 Aug 2023 13:02:03 +0200 Message-ID: <20230803110214.163645-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index fd6a75a64a9f..18b102bef370 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -68,12 +68,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt lut_size =3D LUT_SIZE_DEFAULT; } =20 - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val =3D cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57920C00528 for ; Thu, 3 Aug 2023 11:03:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235678AbjHCLDE (ORCPT ); Thu, 3 Aug 2023 07:03:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234872AbjHCLC3 (ORCPT ); Thu, 3 Aug 2023 07:02:29 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BB4B1AB for ; Thu, 3 Aug 2023 04:02:28 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3F1E8660719F; Thu, 3 Aug 2023 12:02:26 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060546; bh=0Ced9zHqXOE8csCfTU84KdtIY5YMgWKarAWvRB7Z5c0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J4OlXbEM9U6zJc3Ny9YttYpQrK0BJ8zXzcs2lvY1YLjzEuQ5g4cf0xdQVleBQv4hg eqIvS5Cq5fwYmJ/e4rBpDrxHxAedLMoPyIK6iH6EzNscKaNxoaGyPhIMLPqKTOmiIh 8kHNuikGIi3w0x/4AtbvyR/PjKcmILeZ+cQ2so+uRoM6cjsEKXoTN7h6Z9GKMDpOwB eE2sbjhJA4D9BCV8uw2FEMiEAXwHBWBaknaXAC7+RZzQmvo6zY0K+9yNDrBaObiLVh SGkMySntNjnjEAiqTQjugBoHzr3UzzEzVdVDglWCnU2FcifN39Ev5qm0XJrfK9dfeN JR7HTvElRTTqQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 06/16] drm/mediatek: gamma: Use bitfield macros Date: Thu, 3 Aug 2023 13:02:04 +0200 Message-ID: <20230803110214.163645-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 18b102bef370..ea91d3619716 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -21,9 +22,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 =20 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { @@ -96,33 +104,33 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt for (i =3D 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); - hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, 10); + diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, 10); + diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, 10); + diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); =20 - word =3D diff.blue << 20 + - diff.green << 10 + - diff.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ - cfg_val =3D cfg_val | GAMMA_LUT_EN; + cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -139,9 +147,12 @@ void mtk_gamma_config(struct device *dev, unsigned int= w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + u32 sz; + + sz =3D FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |=3D FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); =20 - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZ= E); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62084C04A6A for ; Thu, 3 Aug 2023 11:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232321AbjHCLDQ (ORCPT ); Thu, 3 Aug 2023 07:03:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234891AbjHCLCa (ORCPT ); Thu, 3 Aug 2023 07:02:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF65830ED for ; Thu, 3 Aug 2023 04:02:28 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 208ED66071A3; Thu, 3 Aug 2023 12:02:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060547; bh=ozW4byw7zGTKaXL8BQX+fQ96tzc29duKFdiPZzdm3yo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C3gfGe/IZJORkDKC1SAjovki/4zP/YwX2c7qYeKxY/wsSpaFFtE4N36/CnSsQEd7c O1FRXDn0wJRKIEa78Kw9ZpnypykA8qz0oa5pfUmSnXc+kbnto+syVj7MQ1oB1AoiA1 SASjNvSlaiLjMCoRvkGasYM5buYhXnNO1ESfMbtFKz8dvId1+7IC3as6PMqsLv95+H +8QP91+OPxPKyLbB+asc+Ey6eS9dWmDUH0iDLmUTi+29TeGymHry4jmlwpLwu/zXmf iY9eL8ILqgGsF4DxgdA2jEo3Ly8SsPN42oIh4wLULGD2Rh9wkA5eqpIKCJq3HxHjB2 mhxUnrUDu3Yqw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v9 07/16] drm/mediatek: aal: Use bitfield macros Date: Thu, 3 Aug 2023 13:02:05 +0200 Message-ID: <20230803110214.163645-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index e2e4155faf01..05790b444e17 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -18,6 +18,8 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 +#define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) +#define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 #define DISP_AAL_LUT_SIZE 512 =20 @@ -56,9 +58,13 @@ void mtk_aal_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); + u32 sz; =20 - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_= SIZE); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_= OUTPUT_SIZE); + sz =3D FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |=3D FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); + + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SI= ZE); } =20 /** --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DFF1C04E69 for ; Thu, 3 Aug 2023 11:03:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234588AbjHCLDU (ORCPT ); Thu, 3 Aug 2023 07:03:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235220AbjHCLCb (ORCPT ); Thu, 3 Aug 2023 07:02:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CB753A86 for ; Thu, 3 Aug 2023 04:02:29 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DD66366071A8; Thu, 3 Aug 2023 12:02:27 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060548; bh=+ZT9MVxsyo6MHu8EY6ZlJn7amkAtw1lByyRkv1lq5z0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GMnO9OgiJ0yWnys1nyBEBTPKtVk8VnZu2hxmyf/teT97LbrBaLiXF/Ak7YQkuYbJL LkGsk3owPZ3ukdh152BsQmCZo3QnvzDkrpPfAITQyssjyvUf9gisXPisTOrk3fEoGR NI2/os9Bf6nnxlkBynKhGobN1pGrDDt7DtrETYisPyu2wbAj+0kOTMPnosulE2wPYz DBCeZFCVgBFEwLGQTzhBTr+3fEmjevwFfRh4L3ErteKhfOxLUe8Hs6q2OID6k8rKRk PT32VxlpwsQxCwoD0iGqVSI9rIX/4WRWdCVf0eis5hd9owPhzoTDbgMjj5txUBU2fc +ne/d3q3O8YEA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v9 08/16] drm/mediatek: De-commonize disp_aal/disp_gamma gamma_set functions Date: Thu, 3 Aug 2023 13:02:06 +0200 Message-ID: <20230803110214.163645-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding a 12-bits gamma support for the DISP_GAMMA IP, remove the mtk_gamma_set_common() function and move the relevant bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for DISP_AAL: since the latter has no more support for gamma manipulation (being moved to a different IP) in newer revisions, those functions are about to diverge and it makes no sense to keep a common one (with all the complications of passing common data and making exclusions for device driver data) for just a few bits. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 43 ++++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 - drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 34 ++++-------------- 3 files changed, 46 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 05790b444e17..21b25470e9b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -17,10 +17,18 @@ =20 #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) +#define DISP_AAL_CFG 0x0020 +#define AAL_RELAY_MODE BIT(0) +#define AAL_GAMMA_LUT_EN BIT(1) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) #define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 +#define DISP_AAL_GAMMA_LUT 0x0700 +#define DISP_AAL_GAMMA_LUT_R GENMASK(29, 20) +#define DISP_AAL_GAMMA_LUT_G GENMASK(19, 10) +#define DISP_AAL_GAMMA_LUT_B GENMASK(9, 0) +#define DISP_AAL_LUT_BITS 10 #define DISP_AAL_LUT_SIZE 512 =20 struct mtk_disp_aal_data { @@ -60,8 +68,8 @@ void mtk_aal_config(struct device *dev, unsigned int w, struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); u32 sz; =20 - sz =3D FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); - sz |=3D FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); + sz =3D FIELD_PREP(DISP_AAL_SIZE_HSIZE, w); + sz |=3D FIELD_PREP(DISP_AAL_SIZE_VSIZE, h); =20 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SI= ZE); @@ -85,9 +93,36 @@ unsigned int mtk_aal_gamma_get_lut_size(struct device *d= ev) void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); + struct drm_color_lut *lut; + unsigned int i; + u32 cfg_val; + + /* If gamma is not supported in AAL, go out immediately */ + if (!(aal->data && aal->data->has_gamma)) + return; + + /* Also, if there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + + cfg_val =3D readl(aal->regs + DISP_AAL_CFG); + lut =3D (struct drm_color_lut *)state->gamma_lut->data; + + for (i =3D 0; i < DISP_AAL_LUT_SIZE; i++) { + struct drm_color_lut hwlut =3D { + .red =3D drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), + .green =3D drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), + .blue =3D drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) + }; + u32 word; + + word =3D FIELD_PREP(DISP_AAL_GAMMA_LUT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_AAL_GAMMA_LUT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_AAL_GAMMA_LUT_B, hwlut.blue); + writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); + } =20 - if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(NULL, aal->regs, state); + writel(cfg_val, aal->regs + DISP_AAL_CFG); } =20 void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index ca377265e5eb..54d3712e2afd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -56,7 +56,6 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index ea91d3619716..001b98694761 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -73,42 +73,29 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_disp_gamma *gamma; + struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - bool lut_diff; - u16 lut_size; u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; =20 - /* If we're called from AAL, dev is NULL */ - gamma =3D dev ? dev_get_drvdata(dev) : NULL; - - if (gamma && gamma->data) { - lut_diff =3D gamma->data->lut_diff; - lut_size =3D gamma->data->lut_size; - } else { - lut_diff =3D false; - lut_size =3D LUT_SIZE_DEFAULT; - } - - cfg_val =3D readl(regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; + cfg_val =3D readl(gamma->regs + DISP_GAMMA_CFG); + lut_base =3D gamma->regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < lut_size; i++) { + for (i =3D 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; =20 hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); =20 - if (!lut_diff || (i % 2 =3D=3D 0)) { + if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); @@ -132,14 +119,7 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 - writel(cfg_val, regs + DISP_GAMMA_CFG); -} - -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) -{ - struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - - mtk_gamma_set_common(dev, gamma->regs, state); + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } =20 void mtk_gamma_config(struct device *dev, unsigned int w, --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB594C04A94 for ; Thu, 3 Aug 2023 11:03:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234607AbjHCLDc (ORCPT ); Thu, 3 Aug 2023 07:03:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235359AbjHCLCb (ORCPT ); Thu, 3 Aug 2023 07:02:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 846653A81 for ; Thu, 3 Aug 2023 04:02:30 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id ACC3966071A9; Thu, 3 Aug 2023 12:02:28 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060549; bh=G9jUBbuND2wlk1NRIFaK24JaPI1K8tQwQG9IqubvDH8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d0+Ftu88Cle2UkG96ilsTMn3206yazQ+Zze/3bL+tu2NQY2HNUsR1fN6VXUKAien3 GPGsUDgh0UtvOAULHZtxE83y5iLZMWn9uAFzIhA9g0TInmjQm+XKR0MyOva0h7274o wJJwkMDMNSJh3jiXOJWw3bAkiqmszPt0vZqF/DDK3pYRUweMPgn+Md8RFydu2CplwJ 6HKPyX4a4wN3u08M0OI0w6TAQAN2Iwj9ju24RefjXNQA3AGLX7E8dMyKs9e4xp+o5t rv3OFD0coc3DetFGDz7TqGdJxqhtpjiOUjvxnwnbS3IW1PDbNcdYyl+V3sEOMiLanO wfWQKzS0G7gbQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 09/16] drm/mediatek: gamma: Support specifying number of bits per LUT component Date: Thu, 3 Aug 2023 13:02:07 +0200 Message-ID: <20230803110214.163645-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 001b98694761..1845bd326a6d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -38,6 +38,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; =20 /* @@ -91,9 +92,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_st= ate *state) for (i =3D 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); - hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); + hwlut.red =3D drm_color_lut_extract(lut[i].red, gamma->data->lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[i].green, gamma->data->lut_bit= s); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, gamma->data->lut_bits); =20 if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); @@ -101,13 +102,13 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); + diff.red =3D drm_color_lut_extract(diff.red, gamma->data->lut_bits); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); + diff.green =3D drm_color_lut_extract(diff.green, gamma->data->lut_bits); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); + diff.blue =3D drm_color_lut_extract(diff.blue, gamma->data->lut_bits); =20 word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); @@ -217,10 +218,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, }; --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7753C00528 for ; Thu, 3 Aug 2023 11:03:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235365AbjHCLDY (ORCPT ); Thu, 3 Aug 2023 07:03:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233489AbjHCLCd (ORCPT ); Thu, 3 Aug 2023 07:02:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67E072129 for ; Thu, 3 Aug 2023 04:02:31 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 905C466071AB; Thu, 3 Aug 2023 12:02:29 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060550; bh=2c+FsWSMCsIjoPxVpExi1poYE+difGX9dXXLJhfN7Oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dHrZofMMy1N2oJWOfruhV0mVknJBFo9G4S0mlhRwcsIP46npAQmjPuzXZIUwtIqoR Z5lJkoB6fDeSYuzS56MeBsdL9NBoFOS5CkbkDF/xd4AlfyGPtmUPjmmMeVhDZI+8Du PHWkp502zW+80HvTkOZkNvxWYs8rRqLMi0nfD5WyuebG7Z5so0JDFFyC8ZpUb0LDoO abhiAkaQNtfjZwm5XYH+oe4VyzZ294Qj+c4rFJr3ISKcYKijCuv9fVvTvv2n7rR/eY EZL8KmLF2WgQazWD0xB8fIWsnXESaMP0lJ1vaMPH0Jy043fPyfXWrWkJtuGvv3XxVC MaFzhFD7zvqHg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 10/16] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Thu, 3 Aug 2023 13:02:08 +0200 Message-ID: <20230803110214.163645-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 70 ++++++++++++++--------- 1 file changed, 44 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 1845bd326a6d..3f1c6815ea5a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,6 +24,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 =20 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -37,6 +39,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -80,41 +83,54 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_= state *state) unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; =20 + num_lut_banks =3D gamma->data->lut_size / gamma->data->lut_bank_size; cfg_val =3D readl(gamma->regs + DISP_GAMMA_CFG); lut_base =3D gamma->regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < gamma->data->lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red =3D drm_color_lut_extract(lut[i].red, gamma->data->lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[i].green, gamma->data->lut_bit= s); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, gamma->data->lut_bits); - - if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, gamma->data->lut_bits); - - diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, gamma->data->lut_bits); - - diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, gamma->data->lut_bits); - - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); + } + + for (i =3D 0; i < gamma->data->lut_bank_size; i++) { + int n =3D (cur_bank * gamma->data->lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[n].red, gamma->data->lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[n].green, gamma->data->lut_bi= ts); + hwlut.blue =3D drm_color_lut_extract(lut[n].blue, gamma->data->lut_bits= ); + + if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red =3D lut[n].red - lut[n - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, gamma->data->lut_bits); + + diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, gamma->data->lut_bits= ); + + diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, gamma->data->lut_bits); + + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ @@ -218,11 +234,13 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43412C04A94 for ; Thu, 3 Aug 2023 11:03:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235379AbjHCLDf (ORCPT ); Thu, 3 Aug 2023 07:03:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235458AbjHCLCe (ORCPT ); Thu, 3 Aug 2023 07:02:34 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD47430F8 for ; Thu, 3 Aug 2023 04:02:32 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7403F66071A6; Thu, 3 Aug 2023 12:02:30 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060551; bh=n8HvV63ZZGMSvMV6QA95OQQ7cx7V5oON5E66oBaNqmA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N/wuBhL5RfBQ83ntwFbrMNoTHw14m7RF521k2cMK6UBlNQlRFhAjh/A1Zl3qy9H/5 Ykoc+wvz4qIvq5VBdb86kKZRnHiXsd73plSfFT7SCrk8YX0YuVdebYzFyjxwjWkODl 0Pm5GwAhGU0zr4xkf7z514R18Qa8XVXwzZLzgFSheh9Rf0LnCOGbpmEp3UW4Ht624d P+2nyu5mWhsRvf1ZsDxbDKJzoGP1kjTbYPO1AAIODQQ+yShrDxijXbdbTqwPWqBlmm DKjO+skdHD8B/1TaSCBY+4RaYZDkQOdEyhet772zU9TRSr6DBm/Vr40Awkcunr6aD6 yqqStageyAx4A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 11/16] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Thu, 3 Aug 2023 13:02:09 +0200 Message-ID: <20230803110214.163645-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 +++++++++++++++++++---- 1 file changed, 62 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 3f1c6815ea5a..7d2f8042ace0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,12 +26,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 =20 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) =20 +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 @@ -77,14 +85,30 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 +/* + * SoCs supporting 12-bits LUTs are using a new register layout that does + * always support (by HW) both 12-bits and 10-bits LUT but, on those, we + * ignore the support for 10-bits in this driver and always use 12-bits. + * + * Summarizing: + * - SoC HW support 9/10-bits LUT only + * - Old register layout + * - 10-bits LUT supported + * - 9-bits LUT not supported + * - SoC HW support both 10/12bits LUT + * - New register layout + * - 12-bits LUT supported + * - 10-its LUT not supported + */ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - unsigned int i; - struct drm_color_lut *lut; - void __iomem *lut_base; - u32 cfg_val, lbank_val, word; + void __iomem *lut0_base =3D gamma->regs + DISP_GAMMA_LUT; + void __iomem *lut1_base =3D gamma->regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; int cur_bank, num_lut_banks; + struct drm_color_lut *lut; + unsigned int i; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -92,14 +116,17 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc= _state *state) =20 num_lut_banks =3D gamma->data->lut_size / gamma->data->lut_bank_size; cfg_val =3D readl(gamma->regs + DISP_GAMMA_CFG); - lut_base =3D gamma->regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 + /* Switch to 12 bits data mode if supported */ + data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(gamma->data->lut_b= its =3D=3D 12)); + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { =20 /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |=3D data_mode; writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); } =20 @@ -112,9 +139,15 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc= _state *state) hwlut.blue =3D drm_color_lut_extract(lut[n].blue, gamma->data->lut_bits= ); =20 if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (gamma->data->lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red =3D lut[n].red - lut[n - 1].red; diff.red =3D drm_color_lut_extract(diff.red, gamma->data->lut_bits); @@ -125,11 +158,19 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) diff.blue =3D lut[n].blue - lut[n - 1].blue; diff.blue =3D drm_color_lut_extract(diff.blue, gamma->data->lut_bits); =20 - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (gamma->data->lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (gamma->data->lut_bits =3D=3D 12) + writel(word[1], (lut1_base + i * 4)); } } =20 @@ -246,11 +287,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_= driver_data =3D { .lut_size =3D 512, }; =20 +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data =3D { + .lut_bank_size =3D 256, + .lut_bits =3D 12, + .lut_diff =3D true, + .lut_size =3D 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt8173-disp-gamma", .data =3D &mt8173_gamma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-gamma", .data =3D &mt8183_gamma_driver_data}, + { .compatible =3D "mediatek,mt8195-disp-gamma", + .data =3D &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99C56C00528 for ; Thu, 3 Aug 2023 11:03:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235567AbjHCLDl (ORCPT ); Thu, 3 Aug 2023 07:03:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235459AbjHCLCe (ORCPT ); Thu, 3 Aug 2023 07:02:34 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60DBE3A87 for ; Thu, 3 Aug 2023 04:02:33 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 57EFA66071AD; Thu, 3 Aug 2023 12:02:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060552; bh=zIuIzaHEwa0qol/Hd+tCNwDoAKXf8h/2l/cB7d8v3GQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Po47SfpDrO8QRYfh0Yp8n/3/DG8uV8OPZDWAW5oGlWFlN/OcQldRt9V5K00nt4rBI FatYBUomIfPRUid+uc0kq4gd06Tu/s0EZl4KtRdO7BuDEUbL8yvqGM4SDRxlMLcFy8 XYzqfLAr24pdGftUSjxvLPJ3afUb4I1TZ34PE3auFfrFrAROZ7BYhy9DQIpc1xPsA9 HSpcyh/fKLfxpSD98o2M9fCHbrU011baabPTI7wnrwxirP9LjkAfdjO6EdLWAv4bjM oZS+ueRN48f8iF6IPmkp8/sCj0qhxDEbJk3gAsSSw32YCh5V2Rjy9Au478njkV/Tn7 9Fgnz3RmIVHyg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 12/16] drm/mediatek: gamma: Make sure relay mode is disabled Date: Thu, 3 Aug 2023 13:02:10 +0200 Message-ID: <20230803110214.163645-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Disable relay mode at the end of LUT programming to make sure that the processed image goes through in both DISP_GAMMA and DISP_AAL for gamma setting. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 3 +++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 21b25470e9b7..992dc1424c91 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -122,6 +122,9 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_c= rtc_state *state) writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); } =20 + /* Disable RELAY mode to pass the processed image */ + cfg_val &=3D ~AAL_RELAY_MODE; + writel(cfg_val, aal->regs + DISP_AAL_CFG); } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 7d2f8042ace0..fbff9f97b737 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -177,6 +178,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_= state *state) /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 + /* Disable RELAY mode to pass the processed image */ + cfg_val &=3D ~GAMMA_RELAY_MODE; + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } =20 --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05D99C04A94 for ; Thu, 3 Aug 2023 11:03:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235576AbjHCLDo (ORCPT ); Thu, 3 Aug 2023 07:03:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235466AbjHCLCf (ORCPT ); Thu, 3 Aug 2023 07:02:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 147C73A89 for ; Thu, 3 Aug 2023 04:02:34 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3BCA46607198; Thu, 3 Aug 2023 12:02:32 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060552; bh=Xw0ZEaJZnUUVzop6jWBNiSdfQOZObWFWliMoyYC7chw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lbqNvPN1XTJBra7lLbOaKJo6fVzcfqvVevuuGLM18Ac3OTkrJTpkf7I5ta6xOaxd+ 43tI5yFRGtWStBFQYL+/MWUAsAxCO4bt5R+ws0MDDaRo/J02UZZgq6cLOv/9p0cFt9 rYt19gpnzmNSlwNrytkcWr6feLCRAlg/Et8O3dvvi4HqTi/eIqfxPgk7k1HmLPMAJH crG1yoo4SaCb0YSf3/SndEdg6eZZabqhG/8/lWUG60uQw8IjZ4YYFom8uROH3TcTeh JrKzU4JU4IWUTtqhVjBirZzVkOvntljlh5wV4ZNxlqKiaNVdSR+OJ2F3OnRfdZx4pN +JFunLhd0qMbg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v9 13/16] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Thu, 3 Aug 2023 13:02:11 +0200 Message-ID: <20230803110214.163645-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index fbff9f97b737..d9a70238d524 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -86,6 +87,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + int last_entry =3D lut_size - 1; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[last_entry].red + lut[last_entry].green + lut[last_entry].bl= ue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -175,6 +187,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc= _state *state) } } =20 + if (!gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DECAC04A94 for ; Thu, 3 Aug 2023 11:03:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235579AbjHCLDs (ORCPT ); Thu, 3 Aug 2023 07:03:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235472AbjHCLCf (ORCPT ); Thu, 3 Aug 2023 07:02:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9B823A90 for ; Thu, 3 Aug 2023 04:02:34 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1F8D5660719D; Thu, 3 Aug 2023 12:02:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060553; bh=0mQCLyW1Ws1lLoPWJcO0iech2ujtO9xHY8S2bs46Dv8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e2/mtPw8EeN/ZJS00t/viHD3xVgr+d8fZ5QCFaSPVQDMWbGweFHHeL89MVNSqIWiN mKlijUhjkMm9OFHYwhkdaqXUcVzq0QdeAPUq4j5gUDy9a5VTOQa+cGex05rTWbA1pz hyQNLHZQkY0bIur97zaFiORsF/Rrgy9nIDjbkfiteWbegmcuDBYRwMQhcfvwr464p6 NwRRUeh8lWAtJPDhwNSvkdtmcYR3rkki9HFXBUj3s0tLiLvWsGPH1bYENtNY+XCaDc 1jLPtJNBuj+NJ//Wj2RUHZCJg9j+66LbPppsHgkPlxPVhKafVerL0q29lqi9nLHbbx mchcH9f88mYjg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v9 14/16] drm/mediatek: aal: Rewrite kerneldoc for struct mtk_disp_aal Date: Thu, 3 Aug 2023 13:02:12 +0200 Message-ID: <20230803110214.163645-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kerneldoc for struct mtk_disp_aal was entirely wrong: rewrite it to actually document the structure. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 992dc1424c91..e6ab3eaa1126 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -36,9 +36,11 @@ struct mtk_disp_aal_data { }; =20 /** - * struct mtk_disp_aal - DISP_AAL driver structure - * @ddp_comp - structure containing type enum and hardware resources - * @crtc - associated crtc to report irq events to + * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure + * @clk: clock for DISP_AAL controller + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform specific data for DISP_AAL */ struct mtk_disp_aal { struct clk *clk; --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA5AC04A94 for ; Thu, 3 Aug 2023 11:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235587AbjHCLDy (ORCPT ); Thu, 3 Aug 2023 07:03:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231461AbjHCLCg (ORCPT ); Thu, 3 Aug 2023 07:02:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE563A93 for ; Thu, 3 Aug 2023 04:02:35 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E45D7660719E; Thu, 3 Aug 2023 12:02:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060554; bh=EES2yF/cg8QCjFjl2OGiEbmr3nkWYxd9TW0sjHleq8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J4sJkz+hyIsoZ3Z5RYW1/dEItwKl69Hr8/VaPoib0kmdXtCW0d1og28pknDD4gyKB 5mv4zT7shwfHcRG7KgxNKkNdfNgQlbGtnIkwlsj91qr+4s1kuC0BV+Mb4YCKFuPqzo 6UEMP7VDO2iGOSNSQRQ7mawh5c7x78bg0VClhvipK8l3y38tDu4ZruYVTqgBbt80yY DfRcM45jhwPhlvhggPFHIEHFftuo0RROfscQprTxyWlcdejaKaY8gAEMbvNti812FB e/mgTtcyxWbAy2VX9wUvmoVKlGPhTiKTfn1gSrsgT/2vaBXmuR90IaYbmqony1IIsU Koa+IeoNzxjOw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v9 15/16] drm/mediatek: gamma: Add kerneldoc for struct mtk_disp_gamma Date: Thu, 3 Aug 2023 13:02:13 +0200 Message-ID: <20230803110214.163645-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index d9a70238d524..867445a2af9e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,8 +54,12 @@ struct mtk_disp_gamma_data { u8 lut_bits; }; =20 -/* - * struct mtk_disp_gamma - DISP_GAMMA driver structure +/** + * struct mtk_disp_gamma - Display Gamma driver structure + * @clk: clock for DISP_GAMMA block + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform data for DISP_GAMMA */ struct mtk_disp_gamma { struct clk *clk; --=20 2.41.0 From nobody Fri Sep 20 12:41:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0807CC00528 for ; Thu, 3 Aug 2023 11:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235597AbjHCLD5 (ORCPT ); Thu, 3 Aug 2023 07:03:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235013AbjHCLCi (ORCPT ); Thu, 3 Aug 2023 07:02:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7F333AA0 for ; Thu, 3 Aug 2023 04:02:36 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B36E066071B2; Thu, 3 Aug 2023 12:02:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691060555; bh=eOGxKFVDezkCZBwW2hUee7R5nYDwDHZk82jsXyRXIgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oYg+BLNcCZWfYvOBc79Cldv92wmSwBsSTRdQesNTk0xi+aDyXWMskQVNtYHYBHYMJ 8ciy72f9F2L7SSoEu41qA8BvGN5gD7Lr2cvAShiZlVxiP2ZUj//MqN3HYGfSkgeTE/ 5mU94q8T0cah+fgS+GS7V/9vDcLEg1QryM5hIlPW05ctOudm/rKEQVWsEkYlBbb7Wn b96idRuoIisXzYkTpfbtWpB13ray91f5Zs7RoZrB6t7M8fZfeHJVy/hvlHZGU0KbW6 8Wm/RZ+y43Y7o7XHMiHKQjgJdK5BN9p63NKhclzQdaCARjY9AHULQINhs80n9qIm9B zVHZo0Gn9sMBg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v9 16/16] drm/mediatek: aal: Compress of_device_id entries and add sentinel Date: Thu, 3 Aug 2023 13:02:14 +0200 Message-ID: <20230803110214.163645-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> References: <20230803110214.163645-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Compress the entry for mediatek,mt8173-disp-aal, as it fits in one line, and fix the style; while at it, also add the usual sentinel comment to the last entry. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index e6ab3eaa1126..70de5f3007e4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -212,10 +212,9 @@ static const struct mtk_disp_aal_data mt8173_aal_drive= r_data =3D { }; =20 static const struct of_device_id mtk_disp_aal_driver_dt_match[] =3D { - { .compatible =3D "mediatek,mt8173-disp-aal", - .data =3D &mt8173_aal_driver_data}, - { .compatible =3D "mediatek,mt8183-disp-aal"}, - {}, + { .compatible =3D "mediatek,mt8173-disp-aal", .data =3D &mt8173_aal_drive= r_data }, + { .compatible =3D "mediatek,mt8183-disp-aal" }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_disp_aal_driver_dt_match); =20 --=20 2.41.0