From nobody Mon Feb 9 08:56:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B08BCC04A6A for ; Thu, 3 Aug 2023 08:14:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234362AbjHCIOQ (ORCPT ); Thu, 3 Aug 2023 04:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234445AbjHCINR (ORCPT ); Thu, 3 Aug 2023 04:13:17 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BA5C7284; Thu, 3 Aug 2023 01:05:01 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37384lXK104519; Thu, 3 Aug 2023 03:04:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691049887; bh=BXwqRN7hZ/CXAcZTpese9gH2sAP8NvY5YH/7mWhwlVg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q626M9hgQpmAMLdb+tPYPxRyQtjFTHcEzrQkxzOJatYRetBziYXroYchODhsXgfWm XvLN8cWz7D1XrMiMbBHiGVTeBDb1H7A8Sx/bsJVKfJHmSnrTYuHGtp5/KI/hGA2gCp xt7Yi2RUslYURTHmAUQaGrVemwS3O6VuAeLCeFp4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37384lXd048743 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Aug 2023 03:04:47 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 3 Aug 2023 03:04:46 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 3 Aug 2023 03:04:46 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37384j5g101650; Thu, 3 Aug 2023 03:04:46 -0500 From: Jayesh Choudhary To: , , , CC: , , , , , , , , , , , Subject: [PATCH v9 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Date: Thu, 3 Aug 2023 13:34:39 +0530 Message-ID: <20230803080441.367341-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803080441.367341-1-j-choudhary@ti.com> References: <20230803080441.367341-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rahul T R Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. The DP is Cadence MHDP8546. Signed-off-by: Rahul T R [j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 446d7efa715f..824312b9ef9f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1741,4 +1741,67 @@ c71_3: dsp@67800000 { resets =3D <&k3_reset 40 1>; firmware-name =3D "j784s4-c71_3-fw"; }; + + mhdp: bridge@a000000 { + compatible =3D "ti,j721e-mhdp8546"; + reg =3D <0x0 0xa000000 0x0 0x30a00>, + <0x0 0x4f40000 0x0 0x20>; + reg-names =3D "mhdptx", "j721e-intg"; + clocks =3D <&k3_clks 217 11>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + power-domains =3D <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + dp0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + dss: dss@4a00000 { + compatible =3D "ti,j721e-dss"; + reg =3D <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names =3D "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks =3D <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names =3D "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains =3D <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + interrupts =3D , + , + , + ; + interrupt-names =3D "common_m", + "common_s0", + "common_s1", + "common_s2"; + status =3D "disabled"; + + dss_ports: ports { + }; + }; }; --=20 2.25.1