From nobody Wed Dec 17 09:14:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3103AC04A6A for ; Thu, 3 Aug 2023 07:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234075AbjHCHhT (ORCPT ); Thu, 3 Aug 2023 03:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231958AbjHCHgH (ORCPT ); Thu, 3 Aug 2023 03:36:07 -0400 Received: from mgamail.intel.com (unknown [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F1749D7; Thu, 3 Aug 2023 00:32:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691047938; x=1722583938; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BYJCqqXlCBMi7/Rnb/mQI1paLqwceR/LZ8vb3nUNbyo=; b=BvzHyV4fZDVQvImqQRHudVhzBiqEJ2NPaMm7UX/JaE6DCCEXBi3do5ue LemdwO64OBVr/Q9gLNomwPRpEOOYZm9/SSPICla30aVH1SSrJMQmT3u1G iqVUpbwEBz72l0RzCYt2a6pGoiK0zK/wWDxvlZlazYFzu5A99tndVfPtK Y1rP7xwByeO1T3iaS6BlKdnVRb2Z4SLuwfhYmKol8viUVkO3WFegSBkU4 5naZASv1h10WlF9g1yYGL/7GXxmrSGx87fRQfmKAEi/cv1pKhnjgb88/C cu/7d/x8cURvRM5C6jSXgUzwOy7RgGLvMzFXxHXcncZf2BuJXPbOIRRGJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="354708111" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208";a="354708111" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2023 00:32:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="794888486" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208";a="794888486" Received: from embargo.jf.intel.com ([10.165.9.183]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2023 00:32:16 -0700 From: Yang Weijiang To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, john.allen@amd.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: rick.p.edgecombe@intel.com, chao.gao@intel.com, binbin.wu@linux.intel.com, weijiang.yang@intel.com Subject: [PATCH v5 07/19] KVM:x86: Add fault checks for guest CR4.CET setting Date: Thu, 3 Aug 2023 00:27:20 -0400 Message-Id: <20230803042732.88515-8-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230803042732.88515-1-weijiang.yang@intel.com> References: <20230803042732.88515-1-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Check potential faults for CR4.CET setting per Intel SDM. CET can be enabled if and only if CR0.WP=3D=3D1, i.e. setting CR4.CET=3D1 faults if CR0.WP=3D=3D0 and setting CR0.WP=3D0 fails if CR4.CET=3D=3D1. Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Signed-off-by: Yang Weijiang Reviewed-by: Chao Gao --- arch/x86/kvm/x86.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 015fb0ef102c..82b9f14990da 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -993,6 +993,9 @@ int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr= 0) (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))) return 1; =20 + if (!(cr0 & X86_CR0_WP) && kvm_is_cr4_bit_set(vcpu, X86_CR4_CET)) + return 1; + static_call(kvm_x86_set_cr0)(vcpu, cr0); =20 kvm_post_set_cr0(vcpu, old_cr0, cr0); @@ -1204,6 +1207,9 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long = cr4) return 1; } =20 + if ((cr4 & X86_CR4_CET) && !kvm_is_cr0_bit_set(vcpu, X86_CR0_WP)) + return 1; + static_call(kvm_x86_set_cr4)(vcpu, cr4); =20 kvm_post_set_cr4(vcpu, old_cr4, cr4); --=20 2.27.0