From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53ADDC001E0 for ; Wed, 2 Aug 2023 20:53:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232808AbjHBUxg (ORCPT ); Wed, 2 Aug 2023 16:53:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbjHBUxX (ORCPT ); Wed, 2 Aug 2023 16:53:23 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7157C1FF2; Wed, 2 Aug 2023 13:53:22 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrCAW045361; Wed, 2 Aug 2023 15:53:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009592; bh=ikH5ABT8LZJrm7nGoHEgUHGZs13YKt53UZF5jbARDvk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NJRYI2l7cXBEIEADyY0cSWI5d1dT1C+5hxvo+2uCPqbHg3KgALxTPH4N9X4zUU7wW fkv+ZCCCOzVlRmOLRK0JZRBTdiyuOewFJCICeD93ihVHyuzaGxxBKQzkWXf9giYTF8 +ujGoxFGiFqQp6iq/GCpKhJC8L3oLmt/QwODVvFQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrCGJ043463 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:12 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:11 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrAS8090834; Wed, 2 Aug 2023 15:53:11 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 01/13] arm64: dts: ti: k3-j721e: Enable SDHCI nodes at the board level Date: Wed, 2 Aug 2023 15:52:57 -0500 Message-ID: <20230802205309.257392-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 11 +---------- 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66aac145e7530..64eed76bbb7a3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -563,6 +563,7 @@ &main_uart0 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -570,6 +571,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD Card */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -578,11 +580,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &ospi0 { /* Unused */ status =3D "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c1cbbae761827..e9b84d2c64b26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -504,6 +504,7 @@ &wkup_gpio1 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -511,6 +512,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD/MMC */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -519,11 +521,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &usb_serdes_mux { idle-states =3D <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 3acd55ffd4ffc..0ca31186b9b74 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1478,6 +1478,7 @@ main_sdhci0: mmc@4f80000 { ti,itap-del-sel-ddr52 =3D <0x3>; ti,trm-icp =3D <0x8>; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -1505,6 +1506,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; dma-coherent; sdhci-caps-mask =3D <0x2 0x0>; + status =3D "disabled"; }; =20 main_sdhci2: mmc@4f98000 { @@ -1532,6 +1534,7 @@ main_sdhci2: mmc@4f98000 { ti,clkbuf-sel =3D <0x7>; dma-coherent; sdhci-caps-mask =3D <0x2 0x0>; + status =3D "disabled"; }; =20 usbss0: cdns-usb@4104000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 0ee4f38ec8f03..bd1bd1b746056 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -582,13 +582,9 @@ &main_uart1 { pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 -&main_sdhci0 { - /* Unused */ - status =3D "disabled"; -}; - &main_sdhci1 { /* SD Card */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -597,11 +593,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0002C04FE0 for ; Wed, 2 Aug 2023 20:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232666AbjHBUx1 (ORCPT ); Wed, 2 Aug 2023 16:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232545AbjHBUxW (ORCPT ); Wed, 2 Aug 2023 16:53:22 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 419D426B0; Wed, 2 Aug 2023 13:53:21 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrCxJ109448; Wed, 2 Aug 2023 15:53:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009592; bh=KuRrfwlrYN7ck4e9lXUh/hH/ruzG2lPDTZNjQtzdsy8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TXhQX8xJ9RaUjb52meUEp0HrxtUHpbBRzMyrMyPOPVOAoUED1VLU2S9NsrcctYh6M tzmSEP6LQvma89cjyjr1+vD159CUtLYIFo63fdJBEYBTtka+Lq/5/sQX4wJwS1WeTV QrjDZ3Ly3XcI6Dxwmce2PO1f145FSSWUT9snkAuQ= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrC5i071653 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:12 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:12 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrAS9090834; Wed, 2 Aug 2023 15:53:12 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 02/13] arm64: dts: ti: k3-j7200: Enable SDHCI nodes at the board level Date: Wed, 2 Aug 2023 15:52:58 -0500 Message-ID: <20230802205309.257392-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J7200 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 92a5414911729..dee9056f56051 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -326,6 +326,7 @@ exp3: gpio@20 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -333,6 +334,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; vmmc-supply =3D <&vdd_mmc1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 6eaade5aeb423..5d7542ba41b93 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -654,6 +654,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -677,6 +678,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; + status =3D "disabled"; }; =20 serdes_wiz0: wiz@5060000 { --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99BC4C00528 for ; Wed, 2 Aug 2023 20:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232664AbjHBUxb (ORCPT ); Wed, 2 Aug 2023 16:53:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232422AbjHBUxW (ORCPT ); Wed, 2 Aug 2023 16:53:22 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4984326B2; Wed, 2 Aug 2023 13:53:21 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrDFL045366; Wed, 2 Aug 2023 15:53:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009593; bh=fWSyFj3uZd4vOshVZF6VQQ8ba4qh5QIH6FgUNDtjwug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tawHfSXvY4trqc512CDqTf1SLM1EMYjuIT9ICGoVdoRNQT60FHyl+T+82Z9S+6RfM dp6u+/dJAVrSX/TkpxuVMHfWkRyTfzmHc60HoLv3bwdJNvVlwjI+2oUcrpoHNqNlNq iuRZNSWoqvPRrdJuox/rcKDgzAp35TRi4bGNvXfg= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrDNu086539 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:13 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:13 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASA090834; Wed, 2 Aug 2023 15:53:12 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 03/13] arm64: dts: ti: k3-j721s2: Enable SDHCI nodes at the board level Date: Wed, 2 Aug 2023 15:52:59 -0500 Message-ID: <20230802205309.257392-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J721s2 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 21ad49cfa7eed..ffca12df0a6da 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -373,13 +373,9 @@ &mcu_i2c0 { clock-frequency =3D <400000>; }; =20 -&main_sdhci0 { - /* Unused */ - status =3D "disabled"; -}; - &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 02b7a559bdf21..3a8e6eb402448 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -333,6 +333,7 @@ exp2: gpio@22 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -340,6 +341,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index ed79ab3a32718..c46079fe4ed6e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -665,6 +665,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -694,6 +695,7 @@ main_sdhci1: mmc@4fb0000 { dma-coherent; /* Masking support for SDR104 capability */ sdhci-caps-mask =3D <0x00000003 0x00000000>; + status =3D "disabled"; }; =20 main_navss: bus@30000000 { --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64EFCC001E0 for ; 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Wed, 2 Aug 2023 15:53:13 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:13 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASB090834; Wed, 2 Aug 2023 15:53:13 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 04/13] arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level Date: Wed, 2 Aug 2023 15:53:00 -0500 Message-ID: <20230802205309.257392-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index e26bd988e5224..6041862d5aa75 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -593,6 +593,7 @@ adc { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7b1f94a89eca8..2c9c20a9d9179 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -295,6 +295,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; =20 ospi1: spi@47050000 { @@ -309,6 +310,7 @@ ospi1: spi@47050000 { power-domains =3D <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 973a89b04a22f..43de7c132d343 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -530,6 +530,7 @@ &mcu_r5fss0_core1 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62F2CC04A94 for ; Wed, 2 Aug 2023 20:53:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232900AbjHBUxy (ORCPT ); Wed, 2 Aug 2023 16:53:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232698AbjHBUxa (ORCPT ); Wed, 2 Aug 2023 16:53:30 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E56D2726; Wed, 2 Aug 2023 13:53:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrExP098041; Wed, 2 Aug 2023 15:53:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009594; bh=fQ/532nBdHyDyg7gVLVsTIcGiqz0ZCTnjYpgJNoX93k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f1gBNyZqBWoo72/belRCWT4bYUhoIFlFkocPlfWZ6Ge92lPUGMz0GqLhTUucy+pqP TzKu5jE7d/BkK1/07twxXO/XFnhTpaJX9B4ZvpAu1n6jJFLTXcRvAArGPfVOhhL82W 3HJ6tHg4hMzYrERYpITVlZ0uM5MwEWIxUDTkJb1A= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrEjY071664 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:14 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:14 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:14 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASC090834; Wed, 2 Aug 2023 15:53:13 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 05/13] arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level Date: Wed, 2 Aug 2023 15:53:01 -0500 Message-ID: <20230802205309.257392-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 1 + 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 64eed76bbb7a3..0b89977351c98 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -580,16 +580,6 @@ &main_sdhci1 { disable-wp; }; =20 -&ospi0 { - /* Unused */ - status =3D "disabled"; -}; - -&ospi1 { - /* Unused */ - status =3D "disabled"; -}; - &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c1b6f8d7d1898..0c01bdd9656f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -378,6 +378,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; =20 ospi1: spi@47050000 { @@ -392,6 +393,7 @@ ospi1: spi@47050000 { power-domains =3D <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index bd1bd1b746056..4cd5346f2dd59 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -594,6 +594,7 @@ &main_sdhci1 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 @@ -657,11 +658,6 @@ partition@3fc0000 { }; }; =20 -&ospi1 { - /* Unused */ - status =3D "disabled"; -}; - &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index e90e43202546e..928d3a8ad2d09 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -202,6 +202,7 @@ eeprom@50 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0372BC001E0 for ; Wed, 2 Aug 2023 20:54:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233311AbjHBUyJ (ORCPT ); Wed, 2 Aug 2023 16:54:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232708AbjHBUxb (ORCPT ); Wed, 2 Aug 2023 16:53:31 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACB6D1A5; Wed, 2 Aug 2023 13:53:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrF6X098045; Wed, 2 Aug 2023 15:53:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009595; bh=e7Hj4FuyBxmorKTyYofLw+PErJZV5a7lGgU1QcTquOQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gXWyAGF8Mct6Y1Jlo/XAYc3R9xjALKyeoZLKTodKQLYbavGNUdBVG5DLFyNvwbu8m 1IW8hxx1sqjdnhIlecWnaSJ2tBTiET8ps14LLvMteTB9LORsewYc1jHvekDOSVpGVl 4EtZLiZq/IkXfz+sct+Lt2uGrLafw8SJjjeOHa4c= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrFQP071671 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:15 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:14 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:14 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASD090834; Wed, 2 Aug 2023 15:53:14 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 06/13] arm64: dts: ti: k3-j7200: Enable OSPI nodes at the board level Date: Wed, 2 Aug 2023 15:53:02 -0500 Message-ID: <20230802205309.257392-7-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ee7860913c387..571eb0e2eac92 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -544,6 +544,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4f..5a300d4c8ba03 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -267,6 +267,7 @@ eeprom@50 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74943C04FDF for ; Wed, 2 Aug 2023 20:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229547AbjHBUx5 (ORCPT ); Wed, 2 Aug 2023 16:53:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232685AbjHBUx3 (ORCPT ); Wed, 2 Aug 2023 16:53:29 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14A5B2708; Wed, 2 Aug 2023 13:53:25 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrFg3092475; Wed, 2 Aug 2023 15:53:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009595; bh=c+jmsJ+oDjhDHMr+F50lEy0xYbWV2+4R66PIkMPoEHc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VA21gPlYMCyuyIXHUg2e8QhSPmScsqGmfRSz3wFQ0x4Tg7BGWYa9shIF4PpAiIYiw kwGNUEC1XqqvfxTo7rFG/RXTrAcdQJdRqYkwoBbZ63FOTl6FPO51EAB3B+TSqiOygQ KpkzL6vJiV06m2+gcYPyN1LXLS8SGXQXjaJGcO58= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrF10071674 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:15 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:15 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:15 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASE090834; Wed, 2 Aug 2023 15:53:14 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 07/13] arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level Date: Wed, 2 Aug 2023 15:53:03 -0500 Message-ID: <20230802205309.257392-8-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index d3dd8c426dada..49f910e4b03fc 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -802,6 +802,7 @@ ospi0: spi@fc40000 { assigned-clock-parents =3D <&k3_clks 75 7>; assigned-clock-rates =3D <166666666>; power-domains =3D <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 5606d775153d4..1c2c8f0daca9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -181,6 +181,7 @@ i2c_som_rtc: rtc@52 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index d84e7ee160328..b4a1f73d4fb17 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -520,6 +520,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 963d796a3a970..af06ccd466802 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -518,6 +518,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10578C001E0 for ; Wed, 2 Aug 2023 20:54:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233321AbjHBUyT (ORCPT ); Wed, 2 Aug 2023 16:54:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbjHBUxe (ORCPT ); Wed, 2 Aug 2023 16:53:34 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 960A02D4B; Wed, 2 Aug 2023 13:53:28 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrGWF098050; Wed, 2 Aug 2023 15:53:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009596; bh=aDI8cMXt39aKEhmixQlgMMFEmWazt299GyEFV9WZ+SQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xHAFM2bWkVglW7hRAqsta3MrFHSlfMCOUaVP7fJO9kVh0ImoHbNLszpjNw0Cru0F0 WrfTO8ibfoH3ZgIiYOr6O7dSCG8PYdF8T+7QY1bL18PzhWAjEJjk+56jsGZxVy8cj9 uihdrdqW3RJdoxylEHp0oRUCHXNdtNqCEwV4GZYw= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrGkh071679 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:16 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:15 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:15 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASF090834; Wed, 2 Aug 2023 15:53:15 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 08/13] arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level Date: Wed, 2 Aug 2023 15:53:04 -0500 Message-ID: <20230802205309.257392-9-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 42 ++++--------------- .../dts/ti/k3-j721e-common-proc-board.dts | 35 ++++------------ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 + arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 31 +++----------- 5 files changed, 31 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 0b89977351c98..99536765939d9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -647,52 +647,24 @@ eeprom@50 { }; }; =20 -&main_gpio2 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio3 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio4 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio5 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio6 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio7 { - /* Unused */ - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, <&mikro_bus_pins_default>; }; =20 -&wkup_gpio1 { - /* Unused */ - status =3D "disabled"; -}; - &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; }; =20 +&main_gpio1 { + status =3D "okay"; + /* default pins */ +}; + &usb_serdes_mux { idle-states =3D <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e9b84d2c64b26..2fd940893eb5f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -469,37 +469,20 @@ &main_uart4 { pinctrl-0 =3D <&main_uart4_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio3 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio5 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - -&main_gpio7 { - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; + /* default pins */ +}; + +&main_gpio1 { + status =3D "okay"; + /* default pins */ }; =20 &main_sdhci0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 0ca31186b9b74..7f663d9280b57 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1339,6 +1339,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 105 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio1: gpio@601000 { @@ -1355,6 +1356,7 @@ main_gpio1: gpio@601000 { power-domains =3D <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 106 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -1372,6 +1374,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 107 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio3: gpio@611000 { @@ -1388,6 +1391,7 @@ main_gpio3: gpio@611000 { power-domains =3D <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 108 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -1405,6 +1409,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 109 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio5: gpio@621000 { @@ -1421,6 +1426,7 @@ main_gpio5: gpio@621000 { power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 110 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -1438,6 +1444,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio7: gpio@631000 { @@ -1454,6 +1461,7 @@ main_gpio7: gpio@631000 { power-domains =3D <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 112 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 0c01bdd9656f1..4d107eee9b341 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -281,6 +281,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -297,6 +298,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 mcu_i2c0: i2c@40b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 4cd5346f2dd59..dfb6af60482e7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -731,41 +731,20 @@ &main_i2c5 { }; =20 &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; }; =20 &main_gpio1 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio1_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio3 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio5 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - -&main_gpio7 { - status =3D "disabled"; -}; - -&wkup_gpio1 { - status =3D "disabled"; +&wkup_gpio0 { + status =3D "okay"; + /* default pins */ }; =20 &usb_serdes_mux { --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 457F6C00528 for ; Wed, 2 Aug 2023 20:54:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233250AbjHBUyD (ORCPT ); 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Wed, 2 Aug 2023 15:53:17 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:16 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASG090834; Wed, 2 Aug 2023 15:53:16 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 09/13] arm64: dts: ti: k3-j721s2: Enable GPIO nodes at the board level Date: Wed, 2 Aug 2023 15:53:05 -0500 Message-ID: <20230802205309.257392-10-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J721s2 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 18 ++---------------- .../dts/ti/k3-j721s2-common-proc-board.dts | 18 ++++++------------ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 4 ++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 4 files changed, 14 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index ffca12df0a6da..4c855dffb4cd2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -297,31 +297,17 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_= GPIO0_49 */ }; =20 &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpi= o0_pins1_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; -}; - &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 3a8e6eb402448..6f248d27a30a4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -266,20 +266,14 @@ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_O= SPI1_LBCLKO */ }; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; + /* default pins */ }; =20 -&wkup_gpio1 { - status =3D "disabled"; +&wkup_gpio0 { + status =3D "okay"; + /* default pins */ }; =20 &wkup_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index c46079fe4ed6e..0cc8057fce13c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -507,6 +507,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -523,6 +524,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 112 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -539,6 +541,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -555,6 +558,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_i2c0: i2c@2000000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 736ec5fa0ea28..3557f3338377d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -323,6 +323,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 115 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -339,6 +340,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 116 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_i2c0: i2c@42120000 { --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71DEDC001E0 for ; Wed, 2 Aug 2023 20:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232724AbjHBUxj (ORCPT ); Wed, 2 Aug 2023 16:53:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229801AbjHBUxY (ORCPT ); Wed, 2 Aug 2023 16:53:24 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D473C26B5; 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Wed, 2 Aug 2023 15:53:16 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASH090834; Wed, 2 Aug 2023 15:53:16 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Date: Wed, 2 Aug 2023 15:53:06 -0500 Message-ID: <20230802205309.257392-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f56051..4a5c4f36baeec 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,17 @@ &main_uart3 { pinctrl-0 =3D <&main_uart3_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; + /* default pins */ }; =20 &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; -}; - &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5d7542ba41b93..6a776f3bbcb19 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 105 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 107 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 109 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 571eb0e2eac92..5ae7320efad7b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 mcu_navss: bus@28380000 { --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B52BC001E0 for ; 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Wed, 2 Aug 2023 15:53:18 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:18 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:17 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASI090834; Wed, 2 Aug 2023 15:53:17 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 11/13] arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level Date: Wed, 2 Aug 2023 15:53:07 -0500 Message-ID: <20230802205309.257392-12-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 10 ---------- 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 99536765939d9..79245a85d7c69 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -748,6 +748,7 @@ &usb1 { }; =20 &tscadc0 { + status =3D "okay"; /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ adc { ti,adc-channels =3D <0 1 2 3 4 5 6>; @@ -755,6 +756,7 @@ adc { }; =20 &tscadc1 { + status =3D "okay"; /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ adc { ti,adc-channels =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2fd940893eb5f..6cea309fc247a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -621,12 +621,14 @@ partition@3fe0000 { }; =20 &tscadc0 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; =20 &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 4d107eee9b341..37a8c80de3bc5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -411,6 +411,7 @@ tscadc0: tscadc@40200000 { dmas =3D <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; @@ -430,6 +431,7 @@ tscadc1: tscadc@40210000 { dmas =3D <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index dfb6af60482e7..ca5be7797a02b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -829,16 +829,6 @@ &usb1 { phy-names =3D "cdns3,usb3-phy"; }; =20 -&tscadc0 { - /* Unused */ - status =3D "disabled"; -}; - -&tscadc1 { - /* Unused */ - status =3D "disabled"; -}; - &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A3BFC00528 for ; Wed, 2 Aug 2023 20:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232174AbjHBUxp (ORCPT ); Wed, 2 Aug 2023 16:53:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232633AbjHBUxZ (ORCPT ); Wed, 2 Aug 2023 16:53:25 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 777BF26AB; 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Wed, 2 Aug 2023 15:53:18 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASJ090834; Wed, 2 Aug 2023 15:53:17 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 12/13] arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level Date: Wed, 2 Aug 2023 15:53:08 -0500 Message-ID: <20230802205309.257392-13-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 5 +---- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 ++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6041862d5aa75..ba1c14a54acf4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -582,11 +582,8 @@ &mcu_spi0 { ti,pindir-d0-out-d1-in; }; =20 -&tscadc0 { - status =3D "disabled"; -}; - &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 2c9c20a9d9179..4defde540fe0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -112,6 +112,7 @@ tscadc0: tscadc@40200000 { dmas =3D <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; @@ -130,6 +131,7 @@ tscadc1: tscadc@40210000 { dmas =3D <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 43de7c132d343..17f45a9f7b146 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -478,12 +478,14 @@ &usb0_phy { }; =20 &tscadc0 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; =20 &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; --=20 2.39.2 From nobody Sun Feb 8 10:50:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CD06C00528 for ; Wed, 2 Aug 2023 20:53:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232868AbjHBUxv (ORCPT ); Wed, 2 Aug 2023 16:53:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232682AbjHBUx3 (ORCPT ); Wed, 2 Aug 2023 16:53:29 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E48A271C; Wed, 2 Aug 2023 13:53:26 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrJgF109483; Wed, 2 Aug 2023 15:53:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009599; bh=ZHnSjfvWyMiD35RmuNRSm+q3hGovfiL7kU9qUqJO7zI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=InJ9tyloqK1qj+j8x2aFAcj8898zuzOiFsLnvcWI1J6eWBIkKWB+/mvsZefIsyCsz SBPuzRyjc4ZcKE4vjsXEiEVTH7JyJdB7dYoSkvr6LNNuH0USl37OO+ZGBy8wNawwdT HSgjSK0kizrTUCyI4W7koGWiqriFLlbiwKK0za7Q= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrJ8n018966 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:19 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:18 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:18 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASK090834; Wed, 2 Aug 2023 15:53:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 13/13] arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board level Date: Wed, 2 Aug 2023 15:53:09 -0500 Message-ID: <20230802205309.257392-14-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 49f910e4b03fc..a9db9b6d03aca 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -773,6 +773,7 @@ tscadc0: tscadc@28001000 { assigned-clock-parents =3D <&k3_clks 0 3>; assigned-clock-rates =3D <60000000>; clock-names =3D "fck"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index af06ccd466802..722fd285a34ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -513,10 +513,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; =20 -&tscadc0 { - status =3D "disabled"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.39.2