From nobody Tue Sep 9 22:04:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0AB7C04A6A for ; Wed, 2 Aug 2023 15:14:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233441AbjHBPOz (ORCPT ); Wed, 2 Aug 2023 11:14:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234666AbjHBPOT (ORCPT ); Wed, 2 Aug 2023 11:14:19 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E468122; Wed, 2 Aug 2023 08:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=w5jjc+QVsIh+j5vOtRTYmxquHLNkP8D12I9UGj1E7Eg=; b=TlCsPOfk/qQ96o19eJTkNo/cmP oolOZfqX8FAl78ArzCEwq6A8K9XiVBkg2F9i7ch5PpW9qszzatA3yMoHSowaSc+9H4Itt+TbeSFEI i4qfRCWkMe81KooG9M8Mn+OjZ6XcgYVC809BLb9dX28bVnBtH4r1o8ZY8VY2DjuFdAC9VkB9JhPFm 1RP2mAejSN6bLfWFoAL9XYencUCQnYxx+LVvVOYsrcyTS2g+tFP3FHod0MGn+XBAAhVZM1A3HCRVO E6WtV5jtRqHyVQA/+Eh/bXvkg+0cCwPFRSV6yzfhKeaZJsH6Pz3WzHI3cBr8woXECSiAHCuieH/7b fSw0JZXw==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qRDYB-00Ffl3-7V; Wed, 02 Aug 2023 15:14:11 +0000 From: "Matthew Wilcox (Oracle)" To: Andrew Morton Cc: "Matthew Wilcox (Oracle)" , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Mike Rapoport , Max Filippov , linux-xtensa@linux-xtensa.org Subject: [PATCH v6 29/38] xtensa: Implement the new page table range API Date: Wed, 2 Aug 2023 16:13:57 +0100 Message-Id: <20230802151406.3735276-30-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230802151406.3735276-1-willy@infradead.org> References: <20230802151406.3735276-1-willy@infradead.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PFN_PTE_SHIFT, update_mmu_cache_range(), flush_dcache_folio() and flush_icache_pages(). Signed-off-by: Matthew Wilcox (Oracle) Acked-by: Mike Rapoport (IBM) Cc: Max Filippov Cc: linux-xtensa@linux-xtensa.org --- arch/xtensa/include/asm/cacheflush.h | 9 ++- arch/xtensa/include/asm/pgtable.h | 18 +++--- arch/xtensa/mm/cache.c | 83 ++++++++++++++++------------ 3 files changed, 63 insertions(+), 47 deletions(-) diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm= /cacheflush.h index 7b4359312c25..35153f6725e4 100644 --- a/arch/xtensa/include/asm/cacheflush.h +++ b/arch/xtensa/include/asm/cacheflush.h @@ -119,8 +119,14 @@ void flush_cache_page(struct vm_area_struct*, #define flush_cache_vmap(start,end) flush_cache_all() #define flush_cache_vunmap(start,end) flush_cache_all() =20 +void flush_dcache_folio(struct folio *folio); +#define flush_dcache_folio flush_dcache_folio + #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 -void flush_dcache_page(struct page *); +static inline void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); +} =20 void local_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); @@ -156,6 +162,7 @@ void local_flush_cache_page(struct vm_area_struct *vma, =20 /* This is not required, see Documentation/core-api/cachetlb.rst */ #define flush_icache_page(vma,page) do { } while (0) +#define flush_icache_pages(vma, page, nr) do { } while (0) =20 #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pg= table.h index fc7a14884c6c..ef79cb6c20dc 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h @@ -274,6 +274,7 @@ static inline pte_t pte_mkwrite(pte_t pte) * and a page entry and page directory to the page they refer to. */ =20 +#define PFN_PTE_SHIFT PAGE_SHIFT #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) #define pte_same(a,b) (pte_val(a) =3D=3D pte_val(b)) #define pte_page(x) pfn_to_page(pte_pfn(x)) @@ -301,15 +302,9 @@ static inline void update_pte(pte_t *ptep, pte_t pteva= l) =20 struct mm_struct; =20 -static inline void -set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pt= eval) -{ - update_pte(ptep, pteval); -} - -static inline void set_pte(pte_t *ptep, pte_t pteval) +static inline void set_pte(pte_t *ptep, pte_t pte) { - update_pte(ptep, pteval); + update_pte(ptep, pte); } =20 static inline void @@ -407,8 +402,11 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) =20 #else =20 -extern void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t *ptep); +struct vm_fault; +void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *v= ma, + unsigned long address, pte_t *ptep, unsigned int nr); +#define update_mmu_cache(vma, address, ptep) \ + update_mmu_cache_range(NULL, vma, address, ptep, 1) =20 typedef pte_t *pte_addr_t; =20 diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 19e5a478a7e8..7ec66a79f472 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -121,9 +121,9 @@ EXPORT_SYMBOL(copy_user_highpage); * */ =20 -void flush_dcache_page(struct page *page) +void flush_dcache_folio(struct folio *folio) { - struct address_space *mapping =3D page_mapping_file(page); + struct address_space *mapping =3D folio_flush_mapping(folio); =20 /* * If we have a mapping but the page is not mapped to user-space @@ -132,14 +132,14 @@ void flush_dcache_page(struct page *page) */ =20 if (mapping && !mapping_mapped(mapping)) { - if (!test_bit(PG_arch_1, &page->flags)) - set_bit(PG_arch_1, &page->flags); + if (!test_bit(PG_arch_1, &folio->flags)) + set_bit(PG_arch_1, &folio->flags); return; =20 } else { - - unsigned long phys =3D page_to_phys(page); - unsigned long temp =3D page->index << PAGE_SHIFT; + unsigned long phys =3D folio_pfn(folio) * PAGE_SIZE; + unsigned long temp =3D folio_pos(folio); + unsigned int i, nr =3D folio_nr_pages(folio); unsigned long alias =3D !(DCACHE_ALIAS_EQ(temp, phys)); unsigned long virt; =20 @@ -154,22 +154,26 @@ void flush_dcache_page(struct page *page) return; =20 preempt_disable(); - virt =3D TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); - __flush_invalidate_dcache_page_alias(virt, phys); + for (i =3D 0; i < nr; i++) { + virt =3D TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); + __flush_invalidate_dcache_page_alias(virt, phys); =20 - virt =3D TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK); + virt =3D TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK); =20 - if (alias) - __flush_invalidate_dcache_page_alias(virt, phys); + if (alias) + __flush_invalidate_dcache_page_alias(virt, phys); =20 - if (mapping) - __invalidate_icache_page_alias(virt, phys); + if (mapping) + __invalidate_icache_page_alias(virt, phys); + phys +=3D PAGE_SIZE; + temp +=3D PAGE_SIZE; + } preempt_enable(); } =20 /* There shouldn't be an entry in the cache for this page anymore. */ } -EXPORT_SYMBOL(flush_dcache_page); +EXPORT_SYMBOL(flush_dcache_folio); =20 /* * For now, flush the whole cache. FIXME?? @@ -207,45 +211,52 @@ EXPORT_SYMBOL(local_flush_cache_page); =20 #endif /* DCACHE_WAY_SIZE > PAGE_SIZE */ =20 -void -update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *p= tep) +void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *v= ma, + unsigned long addr, pte_t *ptep, unsigned int nr) { unsigned long pfn =3D pte_pfn(*ptep); - struct page *page; + struct folio *folio; + unsigned int i; =20 if (!pfn_valid(pfn)) return; =20 - page =3D pfn_to_page(pfn); + folio =3D page_folio(pfn_to_page(pfn)); =20 - /* Invalidate old entry in TLBs */ - - flush_tlb_page(vma, addr); + /* Invalidate old entries in TLBs */ + for (i =3D 0; i < nr; i++) + flush_tlb_page(vma, addr + i * PAGE_SIZE); + nr =3D folio_nr_pages(folio); =20 #if (DCACHE_WAY_SIZE > PAGE_SIZE) =20 - if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) { - unsigned long phys =3D page_to_phys(page); + if (!folio_test_reserved(folio) && test_bit(PG_arch_1, &folio->flags)) { + unsigned long phys =3D folio_pfn(folio) * PAGE_SIZE; unsigned long tmp; =20 preempt_disable(); - tmp =3D TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); - __flush_invalidate_dcache_page_alias(tmp, phys); - tmp =3D TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK); - __flush_invalidate_dcache_page_alias(tmp, phys); - __invalidate_icache_page_alias(tmp, phys); + for (i =3D 0; i < nr; i++) { + tmp =3D TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); + __flush_invalidate_dcache_page_alias(tmp, phys); + tmp =3D TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK); + __flush_invalidate_dcache_page_alias(tmp, phys); + __invalidate_icache_page_alias(tmp, phys); + phys +=3D PAGE_SIZE; + } preempt_enable(); =20 - clear_bit(PG_arch_1, &page->flags); + clear_bit(PG_arch_1, &folio->flags); } #else - if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) + if (!folio_test_reserved(folio) && !test_bit(PG_arch_1, &folio->flags) && (vma->vm_flags & VM_EXEC) !=3D 0) { - unsigned long paddr =3D (unsigned long)kmap_atomic(page); - __flush_dcache_page(paddr); - __invalidate_icache_page(paddr); - set_bit(PG_arch_1, &page->flags); - kunmap_atomic((void *)paddr); + for (i =3D 0; i < nr; i++) { + void *paddr =3D kmap_local_folio(folio, i * PAGE_SIZE); + __flush_dcache_page((unsigned long)paddr); + __invalidate_icache_page((unsigned long)paddr); + kunmap_local(paddr); + } + set_bit(PG_arch_1, &folio->flags); } #endif } --=20 2.40.1