From nobody Sun Feb 8 09:10:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9E16C001DF for ; Wed, 2 Aug 2023 15:02:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234463AbjHBPCs (ORCPT ); Wed, 2 Aug 2023 11:02:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234875AbjHBPC1 (ORCPT ); Wed, 2 Aug 2023 11:02:27 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD475358B for ; Wed, 2 Aug 2023 08:01:46 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1bbd03cb7c1so44625175ad.3 for ; Wed, 02 Aug 2023 08:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690988495; x=1691593295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xmvz1qAJlhi1JiLtSKn9YxPTKy/BQ3KTcH/R0EN23A0=; b=C/o2zBenrpA6l2Lqx38UHIvXhJEUEFSqz/kAeJMWcXZ8X0yWT0oSHfh99DLFfFpsEB 5Bh/+tvnBJXl0Afb4kr/f9K6VDTrW6rS/stKXNVRuadw0TUQzCZnzOduMhkks47bko6o cFbgBUS/OPQ5I5H0jrPlp52bzyvXgbtScIGXFIk9QPO50sJfUnpvtNJihwijJmrAaCjZ BuxBy7lBbKmKu0+Vw5POdNJL4UItKa9UjniW1AQtqWwUTXw0NCvGfIuEAAzsj4hFh6fH /RzkFiob9z/bfqYH1xakZgfcKTrcx6pxMP2FgIHyBys57mmH4HaWyOcesJ6Aw9J3ezH8 swRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690988495; x=1691593295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xmvz1qAJlhi1JiLtSKn9YxPTKy/BQ3KTcH/R0EN23A0=; b=hmB1tri8LX6Wm0OorCqlD9ZObldlNleRH5Lc9MR1KVnkK/aJmy7kfDGe+yXE+l4jAQ KSyZUIynvrJ21BqxrvxeetI2e2iOJ/SA7UCDlHS56g2CmCmWwIGwM3EvAhO0MxMtwxIR iSmYdHxHsppGrfHwRRs7ssGKXrUgNuF6W9OQvJi8CmtR5lQleJpp2AdxQzjjPslXjAt5 +jNs8ap0onKNyaGvLqpZEEE0onpuzOihevwNI6aVgBJDUvoLEN+AQnHVU5OicWUf2lEs fbX16p3i3uUXelaRfC468MyoC1D4e0Gl6PkkTmmc+V/k9B4K1ytnFgtNjCFEJI5BDv3G qKWA== X-Gm-Message-State: ABy/qLZ/U9PU5ol1S2LDwq90FU09FTQsynYUu7PcOy85yDZrgacylwSe RlZz0JJ+nXtn9WekeHaRqrw7dA== X-Google-Smtp-Source: APBJJlGjsLkcV62lQARrHNB4Kz73nZ2dPU32azUrBPiU/hC1zNIKsp2u3haiOAl2WgkRiy/N7PdjVA== X-Received: by 2002:a17:902:b187:b0:1b8:4e69:c8f7 with SMTP id s7-20020a170902b18700b001b84e69c8f7mr13241302plr.23.1690988494595; Wed, 02 Aug 2023 08:01:34 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id v11-20020a1709028d8b00b001bb99e188fcsm12503963plo.194.2023.08.02.08.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 08:01:34 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v7 10/15] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Wed, 2 Aug 2023 20:30:13 +0530 Message-Id: <20230802150018.327079-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802150018.327079-1-apatel@ventanamicro.com> References: <20230802150018.327079-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 ++++ drivers/irqchip/irq-riscv-imsic-platform.c | 48 ++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ =20 +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index b78f1b2ee3dc..ff737b4e195f 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -184,6 +185,39 @@ static const struct irq_domain_ops imsic_base_domain_o= ps =3D { .free =3D imsic_irq_domain_free, }; =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip =3D { + .name =3D "IMSIC-PCI", + .irq_mask =3D imsic_pci_mask_irq, + .irq_unmask =3D imsic_pci_unmask_irq, + .irq_eoi =3D irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops =3D { +}; + +static struct msi_domain_info imsic_pci_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops =3D &imsic_pci_domain_ops, + .chip =3D &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip =3D { .name =3D "IMSIC-PLAT", }; @@ -208,12 +242,26 @@ static int imsic_irq_domains_init(struct device *dev) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain =3D pci_msi_create_irq_domain(dev->fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + dev_err(dev, "failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain =3D platform_msi_create_irq_domain(dev->fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { dev_err(dev, "failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 3170018949a8..ff3c377b9b33 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -31,6 +31,7 @@ struct imsic_priv { =20 /* IRQ domains (created by platform driver) */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; =20 --=20 2.34.1