From nobody Thu Sep 11 10:15:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E051C001E0 for ; Wed, 2 Aug 2023 11:35:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233880AbjHBLfW (ORCPT ); Wed, 2 Aug 2023 07:35:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233300AbjHBLfV (ORCPT ); Wed, 2 Aug 2023 07:35:21 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FBD7211E; Wed, 2 Aug 2023 04:35:19 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372BZDIc115644; Wed, 2 Aug 2023 06:35:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1690976113; bh=N3aEGUEAKcwcM0z+aACk3Ka+pcKGBojvrgHFZ09VgPw=; h=From:To:CC:Subject:Date; b=chE8mybTllWQFbxRNvPdc0QBRf2OYCPtX/1qAWImgMbuMw1ihn6jaAemLYV0MmJb2 tiNXCBhkV7LnD6icHO+NTtkrDI2m4IWob95IjVgqSYOMq2WuHMBuCBq/HsZ1HeQsx2 O6bdEkoagqmBsHGtut1dxqnwwwcDqIyxExJ+AjUY= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372BZD6P107984 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 06:35:13 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 06:35:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 06:35:12 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372BZ8Mp116138; Wed, 2 Aug 2023 06:35:09 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [PATCH v2] arm64: dts: ti: k3-j721s2-som-p0: Correct pinmux offset for ospi0 Date: Wed, 2 Aug 2023 17:05:00 +0530 Message-ID: <20230802113500.162276-1-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Due to non-addressable regions in J721S2 SOC wkup_pmx was split into four regions from wkup_pmx0 to wkup_pmx3. After split while updating the pin mux references to newly defined four wkup_pmx, pin mux for OSPI0 was left. Pin mux for OSPI0 is spread over two range wkup_pmx0 and wkup_pmx1, along with correcting pin mux for ospi adding correct pin mux setting within ospi node. Fixes: 6bc829ceea41 ("arm64: dts: ti: k3-j721s2: Fix wkup pinmux range") Signed-off-by: Udit Kumar --- Logs with v2 https://gist.github.com/uditkumarti/701f5f21edd4a10d22abe5f70a752279 Change log: Changes in v2: Changed name of pin mux to align with https://lore.kernel.org/all/20230721082654.27036-1-tony@atomide.com/ patch v1: https://lore.kernel.org/all/20230801125626.3287306-1-u-kumar1@ti.com/ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index d57dd43da0ef..fd1d6c884736 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -45,8 +45,6 @@ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ - J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ - J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ @@ -61,6 +59,15 @@ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI= 0_LBCLKO */ }; }; =20 +&wkup_pmx1 { + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x004, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + >; + }; +}; + &wkup_pmx2 { wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins =3D < @@ -127,7 +134,7 @@ &main_mcan16 { &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; =20 flash@0 { compatible =3D "jedec,spi-nor"; --=20 2.34.1