From nobody Thu Sep 11 12:46:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FD42C001DF for ; Wed, 2 Aug 2023 10:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234004AbjHBKYf (ORCPT ); Wed, 2 Aug 2023 06:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233882AbjHBKXg (ORCPT ); Wed, 2 Aug 2023 06:23:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DB032698 for ; Wed, 2 Aug 2023 03:22:10 -0700 (PDT) Message-ID: <20230802101934.641924080@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690971711; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v1jagm3qezJbhLi1KwbMq1PXX83lXTZZ+4TGqrP0z90=; b=kcLGAGr8vM7wxvnJDZAIm84qWUyLQbZ131GYhWR2nUBgH0BXNc6LRZhNc/r/nhMZvhkC7j Er15Y6d7blSR2skuIbHBbCvfp5fXidLCf64XMiEKMBXXEbPyP9oooFaiGhP4eKLie51jAf h/KCzGBHBZ9Jj0Fh6QI3ebmNfejCLflyATl2tyQID9NDC8tCDPVn+EZMcag5IEPeFxiEWW UB2Z0wfmpAxVeBMaDu8W5HvJ8w6Jgb1Ksda7mDKPa4hjvaJ1Y2ixw1yHXW9nl17d/adP7F 2cvFJ5D67t+7WuhCcRmEZbIOOpje8O410+DVWt0vYwBhzM16foHhf+zv5MJTdQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690971711; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v1jagm3qezJbhLi1KwbMq1PXX83lXTZZ+4TGqrP0z90=; b=Rld9lTpVgQxq7V1PlqmPdI+w4f3FHxOXbaCI/j/VRhw5TtTS+OHW0NxB/T8ZpUPqMrWNFD l95uR0m/lpfAqzBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu Subject: [patch V3 34/40] x86/mm/numa: Use core domain size on AMD References: <20230802101635.459108805@linutronix.de> MIME-Version: 1.0 Date: Wed, 2 Aug 2023 12:21:51 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuinfo::topo::x86_coreid_bits is about to be phased out. Use the core domain size from the topology information. Add a comment why the early MPTABLE parsing is required and decrapify the loop which sets the APIC ID to node map. Signed-off-by: Thomas Gleixner --- arch/x86/mm/amdtopology.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -54,13 +54,11 @@ static __init int find_northbridge(void) =20 int __init amd_numa_init(void) { - u64 start =3D PFN_PHYS(0); + unsigned int numnodes, cores, apicid; + u64 prevbase, start =3D PFN_PHYS(0); u64 end =3D PFN_PHYS(max_pfn); - unsigned numnodes; - u64 prevbase; - int i, j, nb; u32 nodeid, reg; - unsigned int bits, cores, apicid_base; + int i, j, nb; =20 if (!early_pci_allowed()) return -EINVAL; @@ -158,26 +156,25 @@ int __init amd_numa_init(void) return -ENOENT; =20 /* - * We seem to have valid NUMA configuration. Map apicids to nodes - * using the coreid bits from early_identify_cpu. + * We seem to have valid NUMA configuration. Map apicids to nodes + * using the size of the core domain in the APIC space. */ - bits =3D boot_cpu_data.x86_coreid_bits; - cores =3D 1 << bits; - apicid_base =3D 0; + cores =3D topology_get_domain_size(TOPO_CORE_DOMAIN); =20 /* - * get boot-time SMP configuration: + * Scan MPTABLE to map the local APIC and ensure that the boot CPU + * APIC ID is valid. This is required because on pre ACPI/SRAT + * systems IO-APICs are mapped before the boot CPU. */ early_get_smp_config(); =20 - if (boot_cpu_physical_apicid > 0) { - pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid); - apicid_base =3D boot_cpu_physical_apicid; + apicid =3D boot_cpu_physical_apicid; + if (apicid > 0) + pr_info("BSP APIC ID: %02x\n", apicid); + + for_each_node_mask(i, numa_nodes_parsed) { + for (j =3D 0; j < cores; j++, apicid++) + set_apicid_to_node(apicid, i); } - - for_each_node_mask(i, numa_nodes_parsed) - for (j =3D apicid_base; j < cores + apicid_base; j++) - set_apicid_to_node((i << bits) + j, i); - return 0; }