From nobody Sun Feb 8 16:17:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E19C001DF for ; Wed, 2 Aug 2023 07:35:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232866AbjHBHfJ (ORCPT ); Wed, 2 Aug 2023 03:35:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232901AbjHBHe7 (ORCPT ); Wed, 2 Aug 2023 03:34:59 -0400 Received: from out28-52.mail.aliyun.com (out28-52.mail.aliyun.com [115.124.28.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82F8E212B for ; Wed, 2 Aug 2023 00:34:48 -0700 (PDT) X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1058688|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.732773-0.00313448-0.264092;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047206;MF=sunran001@208suo.com;NM=1;PH=DS;RN=5;RT=5;SR=0;TI=SMTPD_---.U6cXXim_1690961680; Received: from localhost.localdomain(mailfrom:sunran001@208suo.com fp:SMTPD_---.U6cXXim_1690961680) by smtp.aliyun-inc.com; Wed, 02 Aug 2023 15:34:42 +0800 From: Ran Sun To: alexander.deucher@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ran Sun Subject: [PATCH] drm/amdgpu: Clean up errors in nv.c Date: Wed, 2 Aug 2023 07:34:39 +0000 Message-Id: <20230802073439.13432-1-sunran001@208suo.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun --- drivers/gpu/drm/amd/amdgpu/nv.c | 48 +++++++++++---------------------- 1 file changed, 16 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/n= v.c index 51523b27a186..414c3c85172d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -67,21 +67,18 @@ static const struct amd_ip_funcs nv_common_ip_funcs; =20 /* Navi */ -static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[]= =3D -{ +static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[]= =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304,= 0)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, }; =20 -static const struct amdgpu_video_codecs nv_video_codecs_encode =3D -{ +static const struct amdgpu_video_codecs nv_video_codecs_encode =3D { .codec_count =3D ARRAY_SIZE(nv_video_codecs_encode_array), .codec_array =3D nv_video_codecs_encode_array, }; =20 /* Navi1x */ -static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[]= =3D -{ +static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[]= =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096,= 52)}, @@ -91,8 +88,7 @@ static const struct amdgpu_video_codec_info nv_video_code= cs_decode_array[] =3D {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, }; =20 -static const struct amdgpu_video_codecs nv_video_codecs_decode =3D -{ +static const struct amdgpu_video_codecs nv_video_codecs_decode =3D { .codec_count =3D ARRAY_SIZE(nv_video_codecs_decode_array), .codec_array =3D nv_video_codecs_decode_array, }; @@ -108,8 +104,7 @@ static const struct amdgpu_video_codecs sc_video_codecs= _encode =3D { .codec_array =3D sc_video_codecs_encode_array, }; =20 -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_v= cn0[] =3D -{ +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_v= cn0[] =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096,= 52)}, @@ -120,8 +115,7 @@ static const struct amdgpu_video_codec_info sc_video_co= decs_decode_array_vcn0[] {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, }; =20 -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_v= cn1[] =3D -{ +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_v= cn1[] =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096,= 52)}, @@ -131,27 +125,23 @@ static const struct amdgpu_video_codec_info sc_video_= codecs_decode_array_vcn1[] {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, }; =20 -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =3D -{ +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =3D { .codec_count =3D ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), .codec_array =3D sc_video_codecs_decode_array_vcn0, }; =20 -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =3D -{ +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =3D { .codec_count =3D ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), .codec_array =3D sc_video_codecs_decode_array_vcn1, }; =20 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ -static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[]= =3D -{ +static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[]= =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160,= 0)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, }; =20 -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_v= cn0[] =3D -{ +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_v= cn0[] =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096,= 52)}, @@ -162,8 +152,7 @@ static struct amdgpu_video_codec_info sriov_sc_video_co= decs_decode_array_vcn0[] {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, }; =20 -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_v= cn1[] =3D -{ +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_v= cn1[] =3D { {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096,= 52)}, @@ -173,20 +162,17 @@ static struct amdgpu_video_codec_info sriov_sc_video_= codecs_decode_array_vcn1[] {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, }; =20 -static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =3D -{ +static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =3D { .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_encode_array), .codec_array =3D sriov_sc_video_codecs_encode_array, }; =20 -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =3D -{ +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =3D { .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), .codec_array =3D sriov_sc_video_codecs_decode_array_vcn0, }; =20 -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =3D -{ +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =3D { .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), .codec_array =3D sriov_sc_video_codecs_decode_array_vcn1, }; @@ -536,8 +522,7 @@ static void nv_program_aspm(struct amdgpu_device *adev) =20 } =20 -const struct amdgpu_ip_block_version nv_common_ip_block =3D -{ +const struct amdgpu_ip_block_version nv_common_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_COMMON, .major =3D 1, .minor =3D 0, @@ -642,8 +627,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_de= vice *adev, return 0; } =20 -static const struct amdgpu_asic_funcs nv_asic_funcs =3D -{ +static const struct amdgpu_asic_funcs nv_asic_funcs =3D { .read_disabled_bios =3D &nv_read_disabled_bios, .read_bios_from_rom =3D &amdgpu_soc15_read_bios_from_rom, .read_register =3D &nv_read_register, --=20 2.17.1