From nobody Sun Feb 8 10:03:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9C88C41513 for ; Wed, 2 Aug 2023 07:18:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232274AbjHBHSU (ORCPT ); Wed, 2 Aug 2023 03:18:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229744AbjHBHSR (ORCPT ); Wed, 2 Aug 2023 03:18:17 -0400 Received: from out28-219.mail.aliyun.com (out28-219.mail.aliyun.com [115.124.28.219]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C0FC1734 for ; Wed, 2 Aug 2023 00:18:15 -0700 (PDT) X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07484511|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.401997-0.00104817-0.596955;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047205;MF=sunran001@208suo.com;NM=1;PH=DS;RN=5;RT=5;SR=0;TI=SMTPD_---.U6ar1OK_1690960687; Received: from localhost.localdomain(mailfrom:sunran001@208suo.com fp:SMTPD_---.U6ar1OK_1690960687) by smtp.aliyun-inc.com; Wed, 02 Aug 2023 15:18:09 +0800 From: Ran Sun To: alexander.deucher@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ran Sun Subject: [PATCH] drm/amdgpu: Clean up errors in dce_v8_0.c Date: Wed, 2 Aug 2023 07:18:05 +0000 Message-Id: <20230802071805.12808-1-sunran001@208suo.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: code indent should use tabs where possible ERROR: space required before the open brace '{' Signed-off-by: Ran Sun --- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/dce_v8_0.c index d421a268c9ff..f2b3cb5ed6be 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -53,8 +53,7 @@ static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); =20 -static const u32 crtc_offsets[6] =3D -{ +static const u32 crtc_offsets[6] =3D { CRTC0_REGISTER_OFFSET, CRTC1_REGISTER_OFFSET, CRTC2_REGISTER_OFFSET, @@ -63,8 +62,7 @@ static const u32 crtc_offsets[6] =3D CRTC5_REGISTER_OFFSET }; =20 -static const u32 hpd_offsets[] =3D -{ +static const u32 hpd_offsets[] =3D { HPD0_REGISTER_OFFSET, HPD1_REGISTER_OFFSET, HPD2_REGISTER_OFFSET, @@ -1345,9 +1343,9 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_= encoder *encoder) if (sad->channels > max_channels) { value =3D (sad->channels << AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT)= | - (sad->byte2 << + (sad->byte2 << AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__S= HIFT) | - (sad->freq << + (sad->freq << AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIE= S__SHIFT); max_channels =3D sad->channels; } @@ -1379,8 +1377,7 @@ static void dce_v8_0_audio_enable(struct amdgpu_devic= e *adev, enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MAS= K : 0); } =20 -static const u32 pin_offsets[7] =3D -{ +static const u32 pin_offsets[7] =3D { (0x1780 - 0x1780), (0x1786 - 0x1780), (0x178c - 0x1780), @@ -1740,8 +1737,7 @@ static void dce_v8_0_afmt_fini(struct amdgpu_device *= adev) } } =20 -static const u32 vga_control_regs[6] =3D -{ +static const u32 vga_control_regs[6] =3D { mmD1VGA_CONTROL, mmD2VGA_CONTROL, mmD3VGA_CONTROL, @@ -1895,9 +1891,9 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc = *crtc, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: fb_format =3D ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | - (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); + (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); fb_swap =3D ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT= ) | - (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT= )); + (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT)); #ifdef __BIG_ENDIAN fb_swap |=3D (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHI= FT); #endif @@ -3151,7 +3147,7 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device= *adev, =20 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); works =3D amdgpu_crtc->pflip_works; - if (amdgpu_crtc->pflip_status !=3D AMDGPU_FLIP_SUBMITTED){ + if (amdgpu_crtc->pflip_status !=3D AMDGPU_FLIP_SUBMITTED) { DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status =3D %d !=3D " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, @@ -3544,8 +3540,7 @@ static void dce_v8_0_set_irq_funcs(struct amdgpu_devi= ce *adev) adev->hpd_irq.funcs =3D &dce_v8_0_hpd_irq_funcs; } =20 -const struct amdgpu_ip_block_version dce_v8_0_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v8_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 8, .minor =3D 0, @@ -3553,8 +3548,7 @@ const struct amdgpu_ip_block_version dce_v8_0_ip_bloc= k =3D .funcs =3D &dce_v8_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version dce_v8_1_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v8_1_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 8, .minor =3D 1, @@ -3562,8 +3556,7 @@ const struct amdgpu_ip_block_version dce_v8_1_ip_bloc= k =3D .funcs =3D &dce_v8_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version dce_v8_2_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v8_2_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 8, .minor =3D 2, @@ -3571,8 +3564,7 @@ const struct amdgpu_ip_block_version dce_v8_2_ip_bloc= k =3D .funcs =3D &dce_v8_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version dce_v8_3_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v8_3_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 8, .minor =3D 3, @@ -3580,8 +3572,7 @@ const struct amdgpu_ip_block_version dce_v8_3_ip_bloc= k =3D .funcs =3D &dce_v8_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version dce_v8_5_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v8_5_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 8, .minor =3D 5, --=20 2.17.1