From nobody Mon Feb 9 10:27:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8992DC04A94 for ; Tue, 1 Aug 2023 09:49:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233682AbjHAJtd (ORCPT ); Tue, 1 Aug 2023 05:49:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232543AbjHAJtQ (ORCPT ); Tue, 1 Aug 2023 05:49:16 -0400 Received: from out28-52.mail.aliyun.com (out28-52.mail.aliyun.com [115.124.28.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8228A2D65 for ; Tue, 1 Aug 2023 02:47:52 -0700 (PDT) X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07778209|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.00228266-0.000301776-0.997416;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047206;MF=sunran001@208suo.com;NM=1;PH=DS;RN=7;RT=7;SR=0;TI=SMTPD_---.U5t4Bqw_1690883263; Received: from localhost.localdomain(mailfrom:sunran001@208suo.com fp:SMTPD_---.U5t4Bqw_1690883263) by smtp.aliyun-inc.com; Tue, 01 Aug 2023 17:47:46 +0800 From: Ran Sun To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ran Sun Subject: [PATCH] drm/amd/pm: Clean up errors in polaris_baco.c Date: Tue, 1 Aug 2023 09:47:42 +0000 Message-Id: <20230801094742.8032-1-sunran001@208suo.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun --- .../drm/amd/pm/powerplay/hwmgr/polaris_baco.c | 30 +++++++------------ 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/polaris_baco.c b/driver= s/gpu/drm/amd/pm/powerplay/hwmgr/polaris_baco.c index 8f8e296f2fe9..a6a6d43b09f8 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/polaris_baco.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/polaris_baco.c @@ -35,8 +35,7 @@ #include "smu/smu_7_1_3_d.h" #include "smu/smu_7_1_3_sh_mask.h" =20 -static const struct baco_cmd_entry gpio_tbl[] =3D -{ +static const struct baco_cmd_entry gpio_tbl[] =3D { { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 }, { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 }, { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 }, @@ -49,15 +48,13 @@ static const struct baco_cmd_entry gpio_tbl[] =3D { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 } }; =20 -static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =3D -{ +static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =3D { { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 }, { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 }, { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 } }; =20 -static const struct baco_cmd_entry use_bclk_tbl[] =3D -{ +static const struct baco_cmd_entry use_bclk_tbl[] =3D { { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS= _EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, @@ -70,8 +67,7 @@ static const struct baco_cmd_entry use_bclk_tbl[] =3D { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MA= SK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 } }; =20 -static const struct baco_cmd_entry turn_off_plls_tbl[] =3D -{ +static const struct baco_cmd_entry turn_off_plls_tbl[] =3D { { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__= GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0= , 0x1 }, { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_D= RAM__RST_CTL__SHIFT, 0, 0x1 }, @@ -92,8 +88,7 @@ static const struct baco_cmd_entry turn_off_plls_tbl[] = =3D { CMD_DELAY_US, 0, 0, 0, 5, 0x0 } }; =20 -static const struct baco_cmd_entry clk_req_b_tbl[] =3D -{ +static const struct baco_cmd_entry clk_req_b_tbl[] =3D { { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL }, { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MAS= K, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 }, { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MAS= K, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }, @@ -108,8 +103,7 @@ static const struct baco_cmd_entry clk_req_b_tbl[] =3D { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOU= T_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 } }; =20 -static const struct baco_cmd_entry enter_baco_tbl[] =3D -{ +static const struct baco_cmd_entry enter_baco_tbl[] =3D { { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B= ACO_EN__SHIFT, 0, 0x01 }, { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK,= BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 }, { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0= x40000 }, @@ -126,8 +120,7 @@ static const struct baco_cmd_entry enter_baco_tbl[] =3D =20 #define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__P= WRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK =20 -static const struct baco_cmd_entry exit_baco_tbl[] =3D -{ +static const struct baco_cmd_entry exit_baco_tbl[] =3D { { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_C= NTL__BACO_RESET_EN__SHIFT, 0, 0x01 }, { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_C= NTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 }, { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_= CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 }, @@ -142,14 +135,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] = =3D { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x0= 0 } }; =20 -static const struct baco_cmd_entry clean_baco_tbl[] =3D -{ +static const struct baco_cmd_entry clean_baco_tbl[] =3D { { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 }, { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 } }; =20 -static const struct baco_cmd_entry use_bclk_tbl_vg[] =3D -{ +static const struct baco_cmd_entry use_bclk_tbl_vg[] =3D { { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL }, { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS= _EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 }, { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 }, @@ -160,8 +151,7 @@ static const struct baco_cmd_entry use_bclk_tbl_vg[] = =3D { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOU= T_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 } }; =20 -static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =3D -{ +static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =3D { { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__= GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0= , 0x1 }, { CMD_DELAY_US, 0, 0, 0, 1, 0x0 }, { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_D= RAM__RST_CTL__SHIFT, 0, 0x1 }, --=20 2.17.1