From nobody Sun Feb 8 05:23:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 250CAC001E0 for ; Tue, 1 Aug 2023 06:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231363AbjHAGPm (ORCPT ); Tue, 1 Aug 2023 02:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229543AbjHAGPk (ORCPT ); Tue, 1 Aug 2023 02:15:40 -0400 Received: from out28-193.mail.aliyun.com (out28-193.mail.aliyun.com [115.124.28.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BFD518E for ; Mon, 31 Jul 2023 23:15:38 -0700 (PDT) X-Alimail-AntiSpam: AC=CONTINUE;BC=0.08867355|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0219141-0.000104645-0.977981;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047209;MF=sunran001@208suo.com;NM=1;PH=DS;RN=7;RT=7;SR=0;TI=SMTPD_---.U5foOkY_1690870530; Received: from localhost.localdomain(mailfrom:sunran001@208suo.com fp:SMTPD_---.U5foOkY_1690870530) by smtp.aliyun-inc.com; Tue, 01 Aug 2023 14:15:32 +0800 From: Ran Sun To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ran Sun Subject: [PATCH] drm/amdgpu: Clean up errors in smu7_powertune.c Date: Tue, 1 Aug 2023 06:15:29 +0000 Message-Id: <20230801061529.6269-1-sunran001@208suo.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: space required after that ',' (ctx:VxV) Signed-off-by: Ran Sun --- .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c b/driv= ers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c index 21be23ec3c79..edab3ef09d33 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c @@ -520,8 +520,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Polari= s12[] =3D { { 0xFFFFFFFF } }; =20 -static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =3D -{ +static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =3D { /* -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- * Offset Mask = Shift Va= lue Type * -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- @@ -646,7 +645,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Polari= s11_Kicker[] =3D { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CT= RL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x000= 1, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DE= LAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x000= 1, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DE= LAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x000= 1, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER= _THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01a= a, GPU_CONFIGREG_DIDT_IND }, + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER= _THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01= aa, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK= , DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x000= 0, GPU_CONFIGREG_DIDT_IND }, =20 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_= ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x000= 1, GPU_CONFIGREG_DIDT_IND }, @@ -666,8 +665,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Polari= s11_Kicker[] =3D { 0xFFFFFFFF } /* End of list */ }; =20 -static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =3D -{ +static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =3D { // -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- // Offset Mask = Shift Va= lue Type // -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- @@ -703,8 +701,7 @@ static const struct gpu_pt_config_reg GCCACConfig_VegaM= [] =3D { 0xFFFFFFFF } // End of list }; =20 -static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =3D -{ +static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =3D { // -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- // Offset Mask = Shift Va= lue Type // -----------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------- @@ -831,7 +828,7 @@ static const struct gpu_pt_config_reg DIDTConfig_VegaM[= ] =3D { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL= _CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x= 0001, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL= _DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x= 0001, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL= _DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x= 0001, GPU_CONFIGREG_DIDT_IND }, - { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_PO= WER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x= 01aa, GPU_CONFIGREG_DIDT_IND }, + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_PO= WER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0= x01aa, GPU_CONFIGREG_DIDT_IND }, { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_M= ASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x= 0000, GPU_CONFIGREG_DIDT_IND }, =20 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNI= NG_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x= 0001, GPU_CONFIGREG_DIDT_IND }, --=20 2.17.1