From nobody Mon Feb 9 10:49:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0806CC001DE for ; Mon, 31 Jul 2023 10:49:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231175AbjGaKtJ (ORCPT ); Mon, 31 Jul 2023 06:49:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbjGaKsx (ORCPT ); Mon, 31 Jul 2023 06:48:53 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE0621A7 for ; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-56cf9a86277so57554687b3.3 for ; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800531; x=1691405331; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=XpxDiPCFOm0sbFmMF9gdCcsfofnkpvd6AL0rLhPbViQ=; b=CprqZcvZgWUASS/ghl9a0jTUcICzr0dBfO70oSWdJfBWyUAYLPGAJS9BuMs3dZ8YXn AqdNx95bDXgpWgiPE29Tz1iz6qujpe9IE+sgGgxAGilKICawmzbihG/ip2rFZZeolni7 ADDKck32yG7qiKiayt3KdzPEZYIWPp7w6m+ri9SGlUqpsrpzTkdq7tzbpC3bwuBv7ouI XL0j+2Km05HTCeuonvWxIIEbXxKFYNJOEP39NfUFNaNBD32G5Hfa1Ul5AcVV9SFBH/gB 7/pJxG9Pn4dSAp4ycfQSFSV7hynPP3THy08jCMX6g5c6Rq0SnG0a/br0+sDq1tXuWT+v DJng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800531; x=1691405331; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XpxDiPCFOm0sbFmMF9gdCcsfofnkpvd6AL0rLhPbViQ=; b=UR0NAI99TBCeHhdRaMbjq89MhK6Ief/EvgAddqv72P6F8vGkD9sIMfxX4z6RkHLq5V EsP2i9xps/DPEwAY58Q3k/b9yoKskD9xq14sTy5LeV8gO04axij8jsQaakBQGPErwTUW TYajdU9/ZXpmkbbMfcyzlpsaOtEgn3VYoHVf2CwQt+K/qHv3co5TKdiJQeeiqf+0T6Qe haVKN5s4OV8EiqALYM9mhDa56YtUi0u3n2q4DDzPtw48jn0vREEFhpdivNN9zZAHt9LF Y7p6tb1BTiYX94nO7Kakwb7J+Jg/AqwhmN7BKpVG1y11+DG2qMUPLg5zKn2pc4txETVG gyvQ== X-Gm-Message-State: ABy/qLajC+Jt/1D0LTDwz6pL6YfaaOwthslW7aS+S//4DbSD1aSJrcP6 2gZDwRvPf4OUlhofL2H4LLGMEg/ivHnB X-Google-Smtp-Source: APBJJlHp594QjUMqu/ZD7+TJXoN8QMn/4PScDeBmoDukzwKHNPjMbBjTCQkOCEODttdNrPCwcszA8YRKwtpF X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:c609:0:b0:570:b1:ca37 with SMTP id l9-20020a81c609000000b0057000b1ca37mr69408ywi.5.1690800531032; Mon, 31 Jul 2023 03:48:51 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:12 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.2.I1ef1ed19d7786c8176a0d05820c869e650c8d68f@changeid> Subject: [PATCH v2 2/8] iommu/arm-smmu-v3: Replace s1_cfg with cdtab_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" arm_smmu_ctx_desc_cfg is renamed to arm_smmu_cdtab_cfg to make it more obvious that it represents a cd table. The max number of CDs that can be represented by the CD table is stored in this truct in its log2 form since it is more useful for users of the CD table, and replaces the s1cdmax field in s1_cfg. Instead of storing s1_cfg.s1fmt, it can also be trivially computed from the cdtab_cfg, and is therefore removed from s1_cfg. Signed-off-by: Michael Shavit --- Changes in v2: - Updated commit message drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++++---------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 10 ++--- 2 files changed, 26 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bb277ff86f65f..8cf4987dd9ec7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1033,9 +1033,9 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_do= main *smmu_domain, unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 - if (smmu_domain->s1_cfg.s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) + if (!cdcfg->l1_desc) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; =20 idx =3D ssid >> CTXDESC_SPLIT; @@ -1071,7 +1071,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, bool cd_live; __le64 *cdptr; =20 - if (WARN_ON(ssid >=3D (1 << smmu_domain->s1_cfg.s1cdmax))) + if (WARN_ON(ssid >=3D (1 << smmu_domain->cd_table.max_cds_bits))) return -E2BIG; =20 cdptr =3D arm_smmu_get_cd_ptr(smmu_domain, ssid); @@ -1138,19 +1138,16 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _domain *smmu_domain) size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &cfg->cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 - max_contexts =3D 1 << cfg->s1cdmax; + max_contexts =3D 1 << cdcfg->max_cds_bits; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || max_contexts <=3D CTXDESC_L2_ENTRIES) { - cfg->s1fmt =3D STRTAB_STE_0_S1FMT_LINEAR; cdcfg->num_l1_ents =3D max_contexts; =20 l1size =3D max_contexts * (CTXDESC_CD_DWORDS << 3); } else { - cfg->s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2; cdcfg->num_l1_ents =3D DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); =20 @@ -1186,7 +1183,7 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_d= omain *smmu_domain) int i; size_t size, l1size; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 if (cdcfg->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1276,7 +1273,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, u64 val =3D le64_to_cpu(dst[0]); bool ste_live =3D false; struct arm_smmu_device *smmu =3D NULL; - struct arm_smmu_s1_cfg *s1_cfg =3D NULL; + struct arm_smmu_ctx_desc_cfg *cd_table =3D NULL; struct arm_smmu_s2_cfg *s2_cfg =3D NULL; struct arm_smmu_domain *smmu_domain =3D NULL; struct arm_smmu_cmdq_ent prefetch_cmd =3D { @@ -1294,7 +1291,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - s1_cfg =3D &smmu_domain->s1_cfg; + cd_table =3D &smmu_domain->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -1325,7 +1322,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, val =3D STRTAB_STE_0_V; =20 /* Bypass/fault */ - if (!smmu_domain || !(s1_cfg || s2_cfg)) { + if (!smmu_domain || !(cd_table || s2_cfg)) { if (!smmu_domain && disable_bypass) val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else @@ -1344,7 +1341,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, return; } =20 - if (s1_cfg) { + if (cd_table) { u64 strw =3D smmu->features & ARM_SMMU_FEAT_E2H ? STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; =20 @@ -1360,10 +1357,14 @@ static void arm_smmu_write_strtab_ent(struct arm_sm= mu_master *master, u32 sid, !master->stall_enabled) dst[1] |=3D cpu_to_le64(STRTAB_STE_1_S1STALLD); =20 - val |=3D (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | - FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | - FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); + val |=3D (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | + FIELD_PREP(STRTAB_STE_0_S1CDMAX, + cd_table->max_cds_bits) | + FIELD_PREP(STRTAB_STE_0_S1FMT, + cd_table->l1_desc ? + STRTAB_STE_0_S1FMT_64K_L2 : + STRTAB_STE_0_S1FMT_LINEAR); } =20 if (s2_cfg) { @@ -2082,11 +2083,11 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) =20 /* Free the CD and ASID, if we allocated them */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cfg->cdcfg.cdtab) + if (cdcfg->cdtab) arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); @@ -2106,7 +2107,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, int ret; u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 @@ -2119,7 +2120,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, if (ret) goto out_unlock; =20 - cfg->s1cdmax =3D master->ssid_bits; + cdcfg->max_cds_bits =3D master->ssid_bits; =20 smmu_domain->stall_enabled =3D master->stall_enabled; =20 @@ -2457,7 +2458,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - master->ssid_bits !=3D smmu_domain->s1_cfg.s1cdmax) { + master->ssid_bits !=3D smmu_domain->cd_table.max_cds_bits) { ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index f841383a55a35..35a93e8858872 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -595,12 +595,8 @@ struct arm_smmu_ctx_desc_cfg { dma_addr_t cdtab_dma; struct arm_smmu_l1_ctx_desc *l1_desc; unsigned int num_l1_ents; -}; - -struct arm_smmu_s1_cfg { - struct arm_smmu_ctx_desc_cfg cdcfg; - u8 s1fmt; - u8 s1cdmax; + /* log2 of the maximum number of CDs supported by this table */ + u8 max_cds_bits; }; =20 struct arm_smmu_s2_cfg { @@ -725,7 +721,7 @@ struct arm_smmu_domain { union { struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_ctx_desc_cfg cd_table; }; struct arm_smmu_s2_cfg s2_cfg; }; --=20 2.41.0.585.gd2178a4bd4-goog