From nobody Mon Feb 9 02:51:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0CEEC001DF for ; Mon, 31 Jul 2023 10:49:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231143AbjGaKtF (ORCPT ); Mon, 31 Jul 2023 06:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230240AbjGaKst (ORCPT ); Mon, 31 Jul 2023 06:48:49 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46A51E7D for ; Mon, 31 Jul 2023 03:48:47 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5734d919156so38000427b3.3 for ; Mon, 31 Jul 2023 03:48:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800526; x=1691405326; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=MdBXH3uSphZ3S/DQlu6um4GHYkgyiIe3GudkFMqQ35I=; b=jF5zUKWv+JJPzLJPTCtcIQlx+mDLm7QD217GXBNIJTo0QEZk0MsX7gxdB0vFXrli/U HUK/JgAMF7obKygq2QjjRSbtRqSNCflkgUe5lqzRZrptwfxJmo9xA1zBIEPRa6E3eQiQ YjlDdyI3+WL5aTENdTYwTp/TIRy6frsM8MUnqy+fuJtpE13m4dzIjAMiwwb+CvkA//A8 RTVqcv2qCUqzi49yo/tCk57LukWelKjObQGsVpq2vJ6h/FDTMXqPvRrEjOVpdOpMAUTc c96dvk4lXTWXeYGERHC226xc+FwNYZk7vLSa5jsHAhquww4YHOy4RUdtXWZCz5e3tKOM F/JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800526; x=1691405326; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MdBXH3uSphZ3S/DQlu6um4GHYkgyiIe3GudkFMqQ35I=; b=PPh0c9hMn2C0VSOwWUxJifCfxjMWmdrCVlbhYpEGFRjPoPOZ2wisM5kuFoWL12JUhQ hhMAfSdakQqu1969Yd8cH37qDK80PUPM4uhBoBvoS9dz4aMQfxkWjdw6sOop/W2W8V0O 89RqjjHYt8krBQxOsbeW3tbierwElOfh7OHQyMnEuj30cFhFVDe9o9JLjvYXBRPJgiZt BufvWORBcmf5PDJq3F04W5b4EMi/BMs9Xs6I+g5crRyrVQ8Rxs/KH0iYBeXjlAIQ1XZb dW98UYG8q5E6/xlASQtG4PChsqRUvucD3Cx2xewkUGETr7+jnfih+F0y6twVDKQycxF6 lT+w== X-Gm-Message-State: ABy/qLYfOFvdaKTudUS0c5YORw+brJ48SXS3Dfove94MT+JpWIsofBtK H2QYTT/aDMiqlGbtIfHkU5dnYFgU3fu8 X-Google-Smtp-Source: APBJJlEG/r2pVsOWFbxaqVrz5diXEMVk4QsK+K6m1Jj7ZKfXfB/aOkAHkdiQSmR4kN9l5cJ0pQy8CP0I9VC4 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a81:b623:0:b0:584:4158:7f86 with SMTP id u35-20020a81b623000000b0058441587f86mr64515ywh.1.1690800526554; Mon, 31 Jul 2023 03:48:46 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:11 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.1.I67ab103c18d882aedc8a08985af1fba70bca084e@changeid> Subject: [PATCH v2 1/8] iommu/arm-smmu-v3: Move ctx_desc out of s1_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" s1_cfg describes the CD table that is inserted into an SMMU's STEs. It's weird for s1_cfg to also own ctx_desc which describes a CD that is inserted into that table. It is more appropriate for arm_smmu_domain to own ctx_desc. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Undo over-reaching column alignment change .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 ++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++-- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index a5a63b1c947eb..968559d625c40 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -62,7 +62,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) return cd; } =20 - smmu_domain =3D container_of(cd, struct arm_smmu_domain, s1_cfg.cd); + smmu_domain =3D container_of(cd, struct arm_smmu_domain, cd); smmu =3D smmu_domain->smmu; =20 ret =3D xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9b0dc35056019..bb277ff86f65f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1869,7 +1869,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * careful, 007. */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); + arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); } else { cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -1957,7 +1957,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.asid =3D smmu_domain->cd.asid; } else { cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -2088,7 +2088,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) mutex_lock(&arm_smmu_asid_lock); if (cfg->cdcfg.cdtab) arm_smmu_free_cd_tables(smmu_domain); - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; @@ -2107,13 +2107,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 - refcount_set(&cfg->cd.refs, 1); + refcount_set(&cd->refs, 1); =20 /* Prevent SVA from modifying the ASID until it is written to the CD */ mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd, + ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, cd, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); if (ret) goto out_unlock; @@ -2126,23 +2127,23 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, if (ret) goto out_free_asid; =20 - cfg->cd.asid =3D (u16)asid; - cfg->cd.ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cfg->cd.tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | + cd->asid =3D (u16)asid; + cd->ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cd->tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; - cfg->cd.mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; + cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 /* * Note that this will end up calling arm_smmu_sync_cd() before * the master has been added to the devices list for this domain. * This isn't an issue because the STE hasn't been installed yet. */ - ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, cd); if (ret) goto out_free_cd_tables; =20 @@ -2152,7 +2153,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, out_free_cd_tables: arm_smmu_free_cd_tables(smmu_domain); out_free_asid: - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dcab85698a4e2..f841383a55a35 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -599,7 +599,6 @@ struct arm_smmu_ctx_desc_cfg { =20 struct arm_smmu_s1_cfg { struct arm_smmu_ctx_desc_cfg cdcfg; - struct arm_smmu_ctx_desc cd; u8 s1fmt; u8 s1cdmax; }; @@ -724,7 +723,10 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct arm_smmu_s1_cfg s1_cfg; + struct { + struct arm_smmu_ctx_desc cd; + struct arm_smmu_s1_cfg s1_cfg; + }; struct arm_smmu_s2_cfg s2_cfg; }; =20 --=20 2.41.0.585.gd2178a4bd4-goog