From nobody Tue Feb 10 00:24:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4108BC001DE for ; Mon, 31 Jul 2023 14:50:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233089AbjGaOux (ORCPT ); Mon, 31 Jul 2023 10:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232501AbjGaOup (ORCPT ); Mon, 31 Jul 2023 10:50:45 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96FDB1BC for ; Mon, 31 Jul 2023 07:50:43 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bb9e6c2a90so36502935ad.1 for ; Mon, 31 Jul 2023 07:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690815043; x=1691419843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ORkdSUboiT8QANjRcMWUstawFwsHxB8PmOCD2FE6rOU=; b=Tpxs9iTsmJkVJjfJuMGB90N1ogwlgVyJ9DLcP7HBjIH/E2wtMvsHutqXyArMbHMNDn JN9yqrTnSTq3804Q0naOZoIaPLQJkQpjuF2kRV9Jhpp0AdMarufAXhz9G98Pb24rsUv1 yzNSiqFUwUgYKUUMqpAbMHN+dYMilFqxRUflU32/8HNopRr15sZo6X8AhbJxkovwYiak 8XVd88CXAadmZotMQMPEfdIWVxCa31/pG0RjKnZkvjAbXG1ZMrXfocBLXHWae4+CZjXG KAYKSKugV2c43krnaWT+9HWhF33kKwlLUruC+xfQabcpAHyRapJPXbZ80ZMgK8TgZCZw dntQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690815043; x=1691419843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ORkdSUboiT8QANjRcMWUstawFwsHxB8PmOCD2FE6rOU=; b=V+IYBg46guY29NhbOBOiEwHhkdfxwjGBoFqrOrSD+LV6Znh7glwLnhyJvitd/Qzah0 +SFX/o73mijEfUVo/3Q0T2bQ/AVY87svD6kmrJ9LMADOVArqCw9vLRuakor0yrHNDlb8 NA66NvTk1OBioX4tTpwbb6VhFdzCl4JSTNbJIi4oyUdW/vKhdwAvjszR2haJMzB67mZb aymp3dMe9Mclv/tuAJmnRr1KuEp0EYvw4OyGNbwMxKLWqh0Dg/L/0pHn23DCA6bI0br0 YfnUiaPTShAyI0xeglY2UgMADhVQ8TiJf4qsfDbohd+8jUyqYQLkhrJEB3QJckQCFnbu VGfQ== X-Gm-Message-State: ABy/qLZUhkq2Ush6AibFTvzWrVhu/bGTnHmHVNGUqHRtORdomGCftD4x mSbD/+E+lPBOXfI+PCv9audy X-Google-Smtp-Source: APBJJlHPC0AAoqyJNDvJijDAa7dATI3ejtagf3v1wKhGX6u8ghNI94wntjasu9HYIQU73LPhySdYHQ== X-Received: by 2002:a17:902:e847:b0:1b8:b41a:d4be with SMTP id t7-20020a170902e84700b001b8b41ad4bemr12535286plg.10.1690815043085; Mon, 31 Jul 2023 07:50:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.129]) by smtp.gmail.com with ESMTPSA id y4-20020a170902ed4400b001b06c106844sm8730185plb.151.2023.07.31.07.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 07:50:42 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/2] scsi: ufs: core: Add enums for UFS lanes Date: Mon, 31 Jul 2023 20:20:19 +0530 Message-Id: <20230731145020.41262-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731145020.41262-1-manivannan.sadhasivam@linaro.org> References: <20230731145020.41262-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since there are enums available for UFS gears, let's add enums for lanes as well to maintain uniformity. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/core/ufshcd.c | 4 ++-- drivers/ufs/host/ufshcd-pltfrm.c | 4 ++-- include/ufs/unipro.h | 6 ++++++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 90a7c817b7be..3839b58dc892 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -4375,8 +4375,8 @@ static void ufshcd_init_pwr_info(struct ufs_hba *hba) { hba->pwr_info.gear_rx =3D UFS_PWM_G1; hba->pwr_info.gear_tx =3D UFS_PWM_G1; - hba->pwr_info.lane_rx =3D 1; - hba->pwr_info.lane_tx =3D 1; + hba->pwr_info.lane_rx =3D UFS_LANE_1; + hba->pwr_info.lane_tx =3D UFS_LANE_1; hba->pwr_info.pwr_rx =3D SLOWAUTO_MODE; hba->pwr_info.pwr_tx =3D SLOWAUTO_MODE; hba->pwr_info.hs_rate =3D 0; diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-plt= frm.c index 0b7430033047..7005046e8a69 100644 --- a/drivers/ufs/host/ufshcd-pltfrm.c +++ b/drivers/ufs/host/ufshcd-pltfrm.c @@ -305,8 +305,8 @@ EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param); void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param) { *dev_param =3D (struct ufs_dev_params){ - .tx_lanes =3D 2, - .rx_lanes =3D 2, + .tx_lanes =3D UFS_LANE_2, + .rx_lanes =3D UFS_LANE_2, .hs_rx_gear =3D UFS_HS_G3, .hs_tx_gear =3D UFS_HS_G3, .pwm_rx_gear =3D UFS_PWM_G4, diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h index dc9dd1d23f0f..256eb3a43f54 100644 --- a/include/ufs/unipro.h +++ b/include/ufs/unipro.h @@ -230,6 +230,12 @@ enum ufs_hs_gear_tag { UFS_HS_G5 /* HS Gear 5 */ }; =20 +enum ufs_lanes { + UFS_LANE_DONT_CHANGE, /* Don't change Lane */ + UFS_LANE_1, /* Lane 1 (default for reset) */ + UFS_LANE_2, /* Lane 2 */ +}; + enum ufs_unipro_ver { UFS_UNIPRO_VER_RESERVED =3D 0, UFS_UNIPRO_VER_1_40 =3D 1, /* UniPro version 1.40 */ --=20 2.25.1 From nobody Tue Feb 10 00:24:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 504FCC001DE for ; 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Mon, 31 Jul 2023 07:50:45 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.129]) by smtp.gmail.com with ESMTPSA id y4-20020a170902ed4400b001b06c106844sm8730185plb.151.2023.07.31.07.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 07:50:45 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Brian Masney Subject: [PATCH 2/2] scsi: ufs: qcom: Add support for scaling interconnects Date: Mon, 31 Jul 2023 20:20:20 +0530 Message-Id: <20230731145020.41262-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731145020.41262-1-manivannan.sadhasivam@linaro.org> References: <20230731145020.41262-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom SoCs require scaling the interconnect paths for proper working of the peripherals connected through interconnects. Even for accessing the UFS controller, someone should setup the interconnect paths. So far, the bootloaders used to setup the interconnect paths before booting linux as they need to access the UFS storage for things like fetching boot firmware. But with the advent of multi boot options, bootloader nowadays like in SA8540p SoC do not setup the interconnect paths at all. So trying to configure UFS in the absence of the interconnect path configuration, results in boot crash. To fix this issue and also to dynamically scale the interconnects (UFS-DDR and CPU-UFS), interconnect API support is added to the Qcom UFS driver. With this support, the interconnect paths are scaled dynamically based on the gear configuration. During the early stage of ufs_qcom_init(), ufs_qcom_icc_init() will setup the paths to max bandwidth to allow configuring the UFS registers. Touching the registers without configuring the icc paths would result in a crash. However, we don't really need to set max vote for the icc paths as any minimal vote would suffice. But the max value would allow initialization to be done faster. After init, the bandwidth will get updated using ufs_qcom_icc_update_bw() based on the gear and lane configuration. The bandwidth values defined in ufs_qcom_bw_table struct are taken from Qcom downstream vendor devicetree source and are calculated as per the UFS3.1 Spec, Section 6.4.1, HS Gear Rates. So it is fixed across platforms. Cc: Brian Masney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 131 +++++++++++++++++++++++++++++++++++- drivers/ufs/host/ufs-qcom.h | 3 + 2 files changed, 133 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 5728e94b6527..75a1fd295f34 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,49 @@ enum { TSTBUS_MAX, }; =20 +#define QCOM_UFS_MAX_GEAR 4 +#define QCOM_UFS_MAX_LANE 2 + +enum { + MODE_MIN, + MODE_PWM, + MODE_HS_RA, + MODE_HS_RB, + MODE_MAX, +}; + +struct __ufs_qcom_bw_table { + u32 mem_bw; + u32 cfg_bw; +} ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE= + 1] =3D { + [MODE_MIN][0][0] =3D { 0, 0 }, /* Bandwidth values in KB/s */ + [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] =3D { 922, 1000 }, + [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] =3D { 1844, 1000 }, + [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] =3D { 3688, 1000 }, + [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] =3D { 7376, 1000 }, + [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] =3D { 1844, 1000 }, + [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] =3D { 3688, 1000 }, + [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] =3D { 7376, 1000 }, + [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] =3D { 14752, 1000 }, + [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] =3D { 127796, 1000 }, + [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] =3D { 255591, 1000 }, + [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] =3D { 1492582, 102400 }, + [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] =3D { 2915200, 204800 }, + [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] =3D { 255591, 1000 }, + [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] =3D { 511181, 1000 }, + [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] =3D { 1492582, 204800 }, + [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] =3D { 2915200, 409600 }, + [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] =3D { 149422, 1000 }, + [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] =3D { 298189, 1000 }, + [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] =3D { 1492582, 102400 }, + [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] =3D { 2915200, 204800 }, + [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] =3D { 298189, 1000 }, + [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] =3D { 596378, 1000 }, + [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] =3D { 1492582, 204800 }, + [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] =3D { 2915200, 409600 }, + [MODE_MAX][0][0] =3D { 7643136, 307200 }, +}; + static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; =20 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); @@ -789,6 +833,51 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_= host *host, bool enable) } } =20 +static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32= cfg_bw) +{ + struct device *dev =3D host->hba->dev; + int ret; + + ret =3D icc_set_bw(host->icc_ddr, 0, mem_bw); + if (ret < 0) { + dev_err(dev, "failed to set bandwidth request: %d\n", ret); + return ret; + } + + ret =3D icc_set_bw(host->icc_cpu, 0, cfg_bw); + if (ret < 0) { + dev_err(dev, "failed to set bandwidth request: %d\n", ret); + return ret; + } + + return 0; +} + +static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_ho= st *host) +{ + struct ufs_pa_layer_attr *p =3D &host->dev_req_params; + int gear =3D max_t(u32, p->gear_rx, p->gear_tx); + int lane =3D max_t(u32, p->lane_rx, p->lane_tx); + + if (ufshcd_is_hs_mode(p)) { + if (p->hs_rate =3D=3D PA_HS_MODE_B) + return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; + else + return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; + } else { + return ufs_qcom_bw_table[MODE_PWM][gear][lane]; + } +} + +static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) +{ + struct __ufs_qcom_bw_table bw_table; + + bw_table =3D ufs_qcom_get_bw_table(host); + + return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); +} + static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, struct ufs_pa_layer_attr *dev_max_params, @@ -852,6 +941,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); =20 + ufs_qcom_icc_update_bw(host); + /* disable the device ref clock if entered PWM mode */ if (ufshcd_is_hs_mode(&hba->pwr_info) && !ufshcd_is_hs_mode(dev_req_params)) @@ -981,7 +1072,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, = bool on, =20 switch (status) { case PRE_CHANGE: - if (!on) { + if (on) { + ufs_qcom_icc_update_bw(host); + } else { if (!ufs_qcom_is_link_active(hba)) { /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); @@ -993,6 +1086,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, = bool on, /* enable the device ref clock for HS mode*/ if (ufshcd_is_hs_mode(&hba->pwr_info)) ufs_qcom_dev_ref_clk_ctrl(host, true); + } else { + ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, + ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); } break; } @@ -1031,6 +1127,34 @@ static const struct reset_control_ops ufs_qcom_reset= _ops =3D { .deassert =3D ufs_qcom_reset_deassert, }; =20 +static int ufs_qcom_icc_init(struct ufs_qcom_host *host) +{ + struct device *dev =3D host->hba->dev; + int ret; + + host->icc_ddr =3D devm_of_icc_get(dev, "ufs-ddr"); + if (IS_ERR(host->icc_ddr)) + return dev_err_probe(dev, PTR_ERR(host->icc_ddr), + "failed to acquire interconnect path\n"); + + host->icc_cpu =3D devm_of_icc_get(dev, "cpu-ufs"); + if (IS_ERR(host->icc_cpu)) + return dev_err_probe(dev, PTR_ERR(host->icc_cpu), + "failed to acquire interconnect path\n"); + + /* + * Set Maximum bandwidth vote before initializing the UFS controller and + * device. Ideally, a minimal interconnect vote would suffice for the + * initialization, but a max vote would allow faster initialization. + */ + ret =3D ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_b= w, + ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); + + return 0; +} + /** * ufs_qcom_init - bind phy with controller * @hba: host controller instance @@ -1085,6 +1209,10 @@ static int ufs_qcom_init(struct ufs_hba *hba) } } =20 + err =3D ufs_qcom_icc_init(host); + if (err) + goto out_variant_clear; + host->device_reset =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(host->device_reset)) { @@ -1282,6 +1410,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, dev_req_params->pwr_rx, dev_req_params->hs_rate, false); + ufs_qcom_icc_update_bw(host); ufshcd_uic_hibern8_exit(hba); } =20 diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 729240367e70..d6f8e74bd538 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -206,6 +206,9 @@ struct ufs_qcom_host { struct clk *tx_l1_sync_clk; bool is_lane_clks_enabled; =20 + struct icc_path *icc_ddr; + struct icc_path *icc_cpu; + #ifdef CONFIG_SCSI_UFS_CRYPTO struct qcom_ice *ice; #endif --=20 2.25.1