From nobody Fri Sep 20 14:38:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C97EC001DC for ; Mon, 31 Jul 2023 13:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232713AbjGaNFb (ORCPT ); Mon, 31 Jul 2023 09:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231991AbjGaNFL (ORCPT ); Mon, 31 Jul 2023 09:05:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF6811723 for ; Mon, 31 Jul 2023 06:04:57 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 607156607186; Mon, 31 Jul 2023 14:04:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808696; bh=JyiXp46HkBH9WpMUqKvCDJPiZ8ZADL6pJeyaAgpHTPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZVXhalDl1WIW+iMpTN24xPmdb/ngijVWmOxfIKgCRiWCiMEJ6rx2i5KSXZj7UTaWF O2gXayCb5nZ2cBc2mMXcN+i1t7j4ma5fxURbmCl/83omsDbkRMlcoFXqBU2pQLsWUH BBtG+ZczQLNOsU7zeObcpmg/pGlKrb/tTb4eZZoyf3zuSlyAbYnZc9FS54RxJu8Ax2 X/vP0E2Xjok6TGFncAb2HhOx5KJIk6YLR8XSnP0Os1+ceHEGRe8ud3kaMlA8jRt7xa yqgSS8znUh0gRTa0zppT8SVLia5WKzR8TITeJJ5TYVh8dhMVBu2gyHLjFkVGG4CRgC QMP0Rpzd4XV/g== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 11/13] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Mon, 31 Jul 2023 15:04:39 +0200 Message-ID: <20230731130441.173960-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 659d5c512238..6fa3f583f8a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -86,6 +87,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -193,6 +204,14 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } } =20 + if (gamma && gamma->data && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.41.0