From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16D11C00528 for ; Mon, 31 Jul 2023 13:04:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232154AbjGaNEx (ORCPT ); Mon, 31 Jul 2023 09:04:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231453AbjGaNEt (ORCPT ); Mon, 31 Jul 2023 09:04:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08E3D10E9 for ; Mon, 31 Jul 2023 06:04:48 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F02CB6606FCD; Mon, 31 Jul 2023 14:04:45 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808686; bh=yEFNmriytfzFlnNR03nQnEhTvtOxc2/EEUJg2NG5628=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OtmQQL+XpI7BW6TN4SDxP70Jz6+P0pcn8Y2VumodGS0FgBRC8PiSbnqNdaKGJjdHd Ux23Lyln6vT2/Oca42FVswayUMKCiIp3QjzTYg7xbtADpnZ1U8Gif+rFanN86p+6pP P9wjixqsOBb7Mln7SaPRSyXL90iHJX+tDyLK1gRzUBfh3k8xZDPuHWXN7f8StaOlbB suA3P1T4nOd+w6+yltafI5WY/FiKevMwJXgQacTnkmK3QE2BEGRfqXwWaRl6ueFYBm HQneAQYlqnN5F8kd/Oxaza/jLd82mIPJli4t8/njg+M8GALgAOrxm1FwxYtOf/pjon iW5+U1nfsn9zg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH.Lin" , Alexandre Mergnat Subject: [PATCH v7 01/13] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Mon, 31 Jul 2023 15:04:29 +0200 Message-ID: <20230731130441.173960-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index cdbec79474d1..2f602f1f1c49 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -66,7 +66,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state) struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); =20 if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } =20 void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 7746dceadb20..d42cc0698d83 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,24 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { + struct mtk_disp_gamma *gamma; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] =3D {0}; =20 + /* If we're called from AAL, dev is NULL */ + gamma =3D dev ? dev_get_drvdata(dev) : NULL; + + if (gamma && gamma->data) + lut_diff =3D gamma->data->lut_diff; + else + lut_diff =3D false; + if (state->gamma_lut) { reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; @@ -91,12 +101,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct dr= m_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - bool lut_diff =3D false; - - if (gamma->data) - lut_diff =3D gamma->data->lut_diff; =20 - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } =20 void mtk_gamma_config(struct device *dev, unsigned int w, --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84517C001E0 for ; Mon, 31 Jul 2023 13:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232650AbjGaNE5 (ORCPT ); Mon, 31 Jul 2023 09:04:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjGaNEt (ORCPT ); Mon, 31 Jul 2023 09:04:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0028B0 for ; Mon, 31 Jul 2023 06:04:48 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E11856606FD9; Mon, 31 Jul 2023 14:04:46 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808687; bh=kYeyT6HbEedO1YRPTVJsJxzagOYrnms3xwsfF+B40oU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l8c1y3zC/lWm5krDtOFSjzYWODsuXyoNNopnvjbO7aBCMCugzrO995ZfSXjAjNhlF pl0YV5ygpXOzlu/PDQ8V6uUzPYS+zsHjfETwH17XzNI26oTpX8+fK+x0ZRKoFgAeVU yNX83VBuJiBYji/nN4D01cBhIQMNGxKeWZQBLoHnPVnsAdGuMQSRHtC1OiYNtEKDMR jN3qSLPiYV5c+fz/iw8yC3/g4WnhIhJXGfY/vxkZtvZ0EESlL/12dsUL89jA2trBo0 QgYQSr3m4ER4WiGvjFH2MLPgeLPa3nAsEBtkNRiWbiLkYOXL53Gn5iiq8pcZ+oOvh5 0KkP4TMVa1XhA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 02/13] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Mon, 31 Jul 2023 15:04:30 +0200 Message-ID: <20230731130441.173960-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index d42cc0698d83..47751864bd5c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -64,6 +64,10 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt u32 word; u32 diff[3] =3D {0}; =20 + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + /* If we're called from AAL, dev is NULL */ gamma =3D dev ? dev_get_drvdata(dev) : NULL; =20 @@ -72,29 +76,26 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt else lut_diff =3D false; =20 - if (state->gamma_lut) { - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; - lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg =3D readl(regs + DISP_GAMMA_CFG); + reg =3D reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base =3D regs + DISP_GAMMA_LUT; + lut =3D (struct drm_color_lut *)state->gamma_lut->data; + for (i =3D 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } =20 --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A79FC001DC for ; Mon, 31 Jul 2023 13:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232828AbjGaNFA (ORCPT ); Mon, 31 Jul 2023 09:05:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbjGaNEv (ORCPT ); Mon, 31 Jul 2023 09:04:51 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C471210E3 for ; Mon, 31 Jul 2023 06:04:49 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D1AAE66070F7; Mon, 31 Jul 2023 14:04:47 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808688; bh=dRCUBSAJhyuAuYLj+KM0no1asegc1IsekM6rzVKVlw8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lV5WgdN1JlNDhedIKv1Q2b34sNqF7+DiDQRxpZIwCtQIQP0pr8H+x+rUbfJD+BZuN t4FQBtAOrcusjDxs01dZ0vypuY7bx73lD1HjgmA9uPc2ifVnyE7bLwIjSu/loxS1bN fQo5HhRhJmbNd4Dks/zK9bgwvqRvtVg8Mtzv9CY4dPkB3Ve4vbuMoL19qisZ1a68+C rlNBYWjDXwVvuyj9QJpd2QcXgGvCwDBa7MuFMKp9rT5eMbZ2fWr0EgnpS8P8+yYzsG vuRZz+tNjMSEZaQBWmU3DFGdmJdPwR404Q9VcDBG2hVWkVM+2//f3uGLMCMvHwYaYA 56ClMSdXXqYaA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 03/13] drm/mediatek: gamma: Support SoC specific LUT size Date: Mon, 31 Jul 2023 15:04:31 +0200 Message-ID: <20230731130441.173960-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 17 ++++++++++++++- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 23 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 +++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++++++++ 7 files changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 2f602f1f1c49..e2e4155faf01 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -19,7 +19,7 @@ #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_OUTPUT_SIZE 0x04d8 - +#define DISP_AAL_LUT_SIZE 512 =20 struct mtk_disp_aal_data { bool has_gamma; @@ -61,6 +61,21 @@ void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_= OUTPUT_SIZE); } =20 +/** + * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL + * @dev: Pointer to struct device + * + * Return: 0 if gamma control not supported in AAL or gamma LUT size + */ +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); + + if (aal->data && aal->data->has_gamma) + return DISP_AAL_LUT_SIZE; + return 0; +} + void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 75045932353e..ca377265e5eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,7 @@ void mtk_aal_clk_disable(struct device *dev); void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev); void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); @@ -53,6 +54,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 47751864bd5c..7575237625d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,10 +24,12 @@ #define DISP_GAMMA_LUT 0x0700 =20 #define LUT_10BIT_MASK 0x03ff +#define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; =20 /* @@ -54,6 +56,15 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + + if (gamma && gamma->data) + return gamma->data->lut_size; + return LUT_SIZE_DEFAULT; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma; @@ -61,6 +72,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u16 lut_size; u32 word; u32 diff[3] =3D {0}; =20 @@ -71,17 +83,20 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt /* If we're called from AAL, dev is NULL */ gamma =3D dev ? dev_get_drvdata(dev) : NULL; =20 - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; - else + lut_size =3D gamma->data->lut_size; + } else { lut_diff =3D false; + lut_size =3D LUT_SIZE_DEFAULT; + } =20 reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { + for (i =3D 0; i < lut_size; i++) { if (!lut_diff || (i % 2 =3D=3D 0)) { word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -198,10 +213,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { .lut_diff =3D true, + .lut_size =3D 512, }; =20 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index 8a43656ecc30..ebe0cc3a1a4c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -959,8 +959,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] =3D comp; =20 if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size =3D MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { + unsigned int lut_sz =3D mtk_ddp_gamma_get_lut_size(comp); + + if (lut_sz) + gamma_lut_size =3D lut_sz; + } =20 if (comp->funcs->ctm_set) has_ctm =3D true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" =20 -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index f114da4d36a9..f3212e08f2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -271,6 +271,7 @@ static void mtk_ufoe_start(struct device *dev) static const struct mtk_ddp_comp_funcs ddp_aal =3D { .clk_enable =3D mtk_aal_clk_enable, .clk_disable =3D mtk_aal_clk_disable, + .gamma_get_lut_size =3D mtk_aal_gamma_get_lut_size, .gamma_set =3D mtk_aal_gamma_set, .config =3D mtk_aal_config, .start =3D mtk_aal_start, @@ -322,6 +323,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi =3D { static const struct mtk_ddp_comp_funcs ddp_gamma =3D { .clk_enable =3D mtk_gamma_clk_enable, .clk_disable =3D mtk_gamma_clk_disable, + .gamma_get_lut_size =3D mtk_gamma_get_lut_size, .gamma_set =3D mtk_gamma_set, .config =3D mtk_gamma_config, .start =3D mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mt= k_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } =20 +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp = *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFAB6C001DC for ; Mon, 31 Jul 2023 13:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbjGaNFE (ORCPT ); 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b=TUmLNvZGZL9lGCqA4MRBWifBlAWNO7+tiJJIOGW4bL1wl7h0KqpUTtsPXyVmHkQnC FMW8O+PAMLUOrCZ/T7Lv+fa3UvKf5k3wSuM3Ov6T2SXLCBL72eeLQ7QNsaWlDpV7Ru mZb5QlsgTLejSzpb0kI84O6k7Ckc4NrEctFpqZRrsZscIGE1jIbuBAmmkOBcjgslOu hOxNxxBy3kLUUItMwh1BcPauAtpHmY0RgGE5H6KCkR0v88j9XES6kQmB53f3xJyEh3 4cLOSVw4SsZXBHwtOMKHhf3iSpnKhrOWjcQXXxorcYrCDEj7Y67BcC6I46x9zSAFC4 6ut8+6qqJf0lQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 04/13] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Mon, 31 Jul 2023 15:04:32 +0200 Message-ID: <20230731130441.173960-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 7575237625d2..fd6a75a64a9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -74,7 +74,6 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt bool lut_diff; u16 lut_size; u32 word; - u32 diff[3] =3D {0}; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -97,18 +96,29 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); + hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word =3D hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red =3D lut[i].red - lut[i - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, 10); + + diff.green =3D lut[i].green - lut[i - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, 10); + + diff.blue =3D lut[i].blue - lut[i - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, 10); =20 - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word =3D diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69E8DC41513 for ; Mon, 31 Jul 2023 13:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbjGaNFI (ORCPT ); Mon, 31 Jul 2023 09:05:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231626AbjGaNEw (ORCPT ); Mon, 31 Jul 2023 09:04:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A766210EB for ; Mon, 31 Jul 2023 06:04:51 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B31C2660710D; Mon, 31 Jul 2023 14:04:49 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808690; bh=jQ1ukxJYhgqz3VRiaaOzbMrQXLA2ENp1Hjs7vpajFxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gOw9PS5P/p8lyy95aWK13qA0Y9of/ZPlfhrniaS/yKcPm4KtAgyLt+fU4K61ORRXA 9BmaNiyohXn7igHtssMjEOZAVbth9fptvV0sQ2IlkGNIKTIEC1KkD2Mh3CLqW5cj0y GIeSHH3aRYBPn3hKCkwu6br1J7ZdPS1lDc/rXSiOrabR3G58Xgg4zdT9LMcu2lwTCg QRc++U3T0wj+AzVv/ll0ScPNbkU9CSHZNcr+LPq6A5Kq2ynPQdV26jVaxA+eH5h/To 2GhIIqusCzsnu0rNF22+RJd29t6XpaPw3ATd0IDEFZPurtcbauLryMOJqrPG0Kz5ao Do6qUfPfnOdVg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 05/13] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Mon, 31 Jul 2023 15:04:33 +0200 Message-ID: <20230731130441.173960-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index fd6a75a64a9f..18b102bef370 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -68,12 +68,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt lut_size =3D LUT_SIZE_DEFAULT; } =20 - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val =3D cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1226C001DF for ; Mon, 31 Jul 2023 13:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232558AbjGaNFL (ORCPT ); Mon, 31 Jul 2023 09:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232114AbjGaNEx (ORCPT ); Mon, 31 Jul 2023 09:04:53 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A56EE10F2 for ; Mon, 31 Jul 2023 06:04:52 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A87A5660707D; Mon, 31 Jul 2023 14:04:50 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808691; bh=0Ced9zHqXOE8csCfTU84KdtIY5YMgWKarAWvRB7Z5c0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XDXUDt7K1kSIaUhC9K1XmvqmJn71QL51mmmpax4Y05DaenmpHtr2DWrDL3lJ3M8xK g0aa/nF3M6ivkC4h9SwMlz3FtdGC1jhYU31Z+GNj8BJapIvG/cgn4CW4oRXNCXEtED qbxGSMhoer24/ljfRR5egiiDfL8LqxBlQTJ6GH+rHnfOBbEvFAStjxJ3E6nGFd4ogx gZfSV8y9WxFoJwVE5mPDjweq2iN4Qj3ES7P+YNS+gmKOpoKKg/jDzaEE/JRDXg7DJ4 gdgnG/Q1/9/w2SxXocGwJ8+myQZ8cLX0HjsaKBMOdhSIfzWGV8e1NHa/Y2RFH/eTjm x9dj8mnZ1tBvw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 06/13] drm/mediatek: gamma: Use bitfield macros Date: Mon, 31 Jul 2023 15:04:34 +0200 Message-ID: <20230731130441.173960-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 18b102bef370..ea91d3619716 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -21,9 +22,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 =20 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { @@ -96,33 +104,33 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt for (i =3D 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); - hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, 10); + diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, 10); + diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, 10); + diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); =20 - word =3D diff.blue << 20 + - diff.green << 10 + - diff.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ - cfg_val =3D cfg_val | GAMMA_LUT_EN; + cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -139,9 +147,12 @@ void mtk_gamma_config(struct device *dev, unsigned int= w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + u32 sz; + + sz =3D FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |=3D FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); =20 - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZ= E); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D00E0C00528 for ; Mon, 31 Jul 2023 13:05:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbjGaNFP (ORCPT ); Mon, 31 Jul 2023 09:05:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232164AbjGaNEy (ORCPT ); Mon, 31 Jul 2023 09:04:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C947E78 for ; Mon, 31 Jul 2023 06:04:53 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9BB0C6606FD9; Mon, 31 Jul 2023 14:04:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808692; bh=H4ZBSh9kNegCse5QzFRAMY+FZwOpupGhU+7vtU2T9X8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JoBYB4XLyS6CqH8q14qwpY/f1D5fQ1zJU9GPsQIsjFXLh9qkfmO5PKHFTeLGNqAo6 j55AvrwuYl0fWTvxnL5tkKCXUVZGKTRGHxkczbzmYzcyaUNxF/LVlzwSSTASkiuHUv AN8B7phpTyPzNWsGbQNM/0KrM6IxMgcYCR0HiYcba+TJryG1YpZCWeFK4Iefr8AXXg OoZFk5PIMGlvL8sJrt4VavdIuYmFJ17+B7runQbtOavmuLkmztU2CggAOBZDkX+BeK PAC6O22Vz6AxI9WLNNMwwggBL+IqEUB3nsZg6W5tyUK1lsXyGEcipw1bTZGji+06JS X5B1q+cGOlfZA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 07/13] drm/mediatek: gamma: Support specifying number of bits per LUT component Date: Mon, 31 Jul 2023 15:04:35 +0200 Message-ID: <20230731130441.173960-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index ea91d3619716..8a45eac53875 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -38,6 +38,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; =20 /* @@ -81,6 +82,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt void __iomem *lut_base; bool lut_diff; u16 lut_size; + u8 lut_bits; u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ @@ -92,9 +94,11 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt =20 if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; + lut_bits =3D gamma->data->lut_bits; lut_size =3D gamma->data->lut_size; } else { lut_diff =3D false; + lut_bits =3D LUT_BITS_DEFAULT; lut_size =3D LUT_SIZE_DEFAULT; } =20 @@ -104,9 +108,9 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt for (i =3D 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); - hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); + hwlut.red =3D drm_color_lut_extract(lut[i].red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[i].green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, lut_bits); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); @@ -114,13 +118,13 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); + diff.red =3D drm_color_lut_extract(diff.red, lut_bits); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); + diff.green =3D drm_color_lut_extract(diff.green, lut_bits); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); + diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); @@ -237,10 +241,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, }; --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F511C001DF for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808693; bh=JPjjG2QuZmeysV616cmfgYvud3Z5xrxzJr7h2Ftv49o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i+Roxdh4itWI5pmDZ2gel4FwjItXoIteJQMPZvJNE/bNTxmU1uatMiMhdUKJITFRK aoNkwA3uAzW8pJ8J2KuSctQ/40WrD4941ZN+JCfXv/ZcybdIQNNIk/mTwAJm7losj4 IduN1Qz+sTgNLAnJcwUV0oTpINjRCnzkBjcFinCDcmaQFdHpdYBOA2QBqPLqbdiF7z l5qb+gaInpZ+xKYmPR59kpEmi5+AXA0Ji8QpHmUvCTas6qoOiEHlk/mvvd8Afyg6WJ NKvKeiN4J4Vgblg2lKugq0x0fFwLi9Sw+Z3I2ieFjjZkQV+67lWjysUCnZTzdEHLDL FEckK3wT8lPRA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 08/13] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Mon, 31 Jul 2023 15:04:36 +0200 Message-ID: <20230731130441.173960-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 ++++++++++++++--------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 8a45eac53875..65b90e1831c5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,6 +24,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 =20 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -37,6 +39,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -81,9 +84,10 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u16 lut_size; + u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -94,43 +98,57 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt =20 if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; + lut_bank_size =3D gamma->data->lut_bank_size; lut_bits =3D gamma->data->lut_bits; lut_size =3D gamma->data->lut_size; } else { lut_diff =3D false; + lut_bank_size =3D LUT_SIZE_DEFAULT; lut_bits =3D LUT_BITS_DEFAULT; lut_size =3D LUT_SIZE_DEFAULT; } + num_lut_banks =3D lut_size / lut_bank_size; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red =3D drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, lut_bits); - - diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, lut_bits); - - diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); - - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i =3D 0; i < lut_bank_size; i++) { + int n =3D (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red =3D lut[n].red - lut[n - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, lut_bits); + + diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, lut_bits); + + diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); + + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ @@ -241,11 +259,13 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82296C04FDF for ; Mon, 31 Jul 2023 13:05:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229803AbjGaNFU (ORCPT ); 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b=H/7+Lkgo1LqXdetdmxd+xS06ByeTvXhuRX8g5wNsDllR2fEgTYdqiKe2G0kC4CXFg 3lPTs6kLJK3f51APxrJe5gBPJzP/HBNP0ZKS13OAHlxe7cLpSXo9FRyhKPVbR7WE/W w0EJsbzIzeyH4N3T8Fcz3HiBi2ZkwljxKkle2VPM/ZPAVbbFa1mGRh1ryNUr1aopKP V3O5aKG3g0VPzZaf26aTNGel3gUOsPOOZKc8dqxW6lISBppEGXSX1Q7dJIF1WZoKpq HBo1i87Qfm7v2hVQpNg8BDCs/dQ6b+ljyJ1Z1SGXxkJy56/Pjle3c+cAxmq+a3zQOB VOJtAxhGKVr6g== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 09/13] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Mon, 31 Jul 2023 15:04:37 +0200 Message-ID: <20230731130441.173960-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 76 +++++++++++++++++++---- 1 file changed, 63 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 65b90e1831c5..a846d0dbaa69 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,12 +26,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 =20 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) =20 +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 @@ -77,17 +85,33 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 +/* + * SoCs supporting 12-bits LUTs are using a new register layout that does + * always support (by HW) both 12-bits and 10-bits LUT but, on those, we + * ignore the support for 10-bits in this driver and always use 12-bits. + * + * Summarizing: + * - SoC HW support 9/10-bits LUT only + * - Old register layout + * - 10-bits LUT supported + * - 9-bits LUT not supported + * - SoC HW support both 10/12bits LUT + * - New register layout + * - 12-bits LUT supported + * - 10-its LUT not supported + */=20 void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i; + void __iomem *lut0_base =3D regs + DISP_GAMMA_LUT; + void __iomem *lut1_base =3D regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; + int cur_bank, num_lut_banks; + u16 lut_bank_size, lut_size; struct drm_color_lut *lut; - void __iomem *lut_base; + unsigned int i; bool lut_diff; - u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, lbank_val, word; - int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -110,14 +134,17 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt num_lut_banks =3D lut_size / lut_bank_size; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 + /* Switch to 12 bits data mode if supported */ + data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits =3D=3D 12= )); + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { =20 /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |=3D data_mode; writel(lbank_val, regs + DISP_GAMMA_BANK); } =20 @@ -130,9 +157,15 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red =3D lut[n].red - lut[n - 1].red; diff.red =3D drm_color_lut_extract(diff.red, lut_bits); @@ -143,11 +176,19 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt diff.blue =3D lut[n].blue - lut[n - 1].blue; diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (lut_bits =3D=3D 12) + writel(word[1], (lut1_base + i * 4)); } } =20 @@ -271,11 +312,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_= driver_data =3D { .lut_size =3D 512, }; =20 +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data =3D { + .lut_bank_size =3D 256, + .lut_bits =3D 12, + .lut_diff =3D true, + .lut_size =3D 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt8173-disp-gamma", .data =3D &mt8173_gamma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-gamma", .data =3D &mt8183_gamma_driver_data}, + { .compatible =3D "mediatek,mt8195-disp-gamma", + .data =3D &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA184C001DC for ; Mon, 31 Jul 2023 13:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229799AbjGaNFW (ORCPT ); Mon, 31 Jul 2023 09:05:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232827AbjGaNE6 (ORCPT ); Mon, 31 Jul 2023 09:04:58 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FD1B1709 for ; Mon, 31 Jul 2023 06:04:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6ED3666070F7; Mon, 31 Jul 2023 14:04:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808695; bh=ku3saUJmkxnMvFquNrLcvYui7sCcvn9fbu+KQWEoQ/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lcyrATkc+TEKSOg4PgIF2EfzSGDC+xLhHA8q5zRAIl+rwklu+l4nJskht8U17VmIV vZK7cjeSoYK+wLz0/1KsZcFid0bZnqCTLBpzJBjt2Irzx293MIDWLkcNJJjkShYQR7 YBhHz17sZI55I2kfx6KN2GFNQsboVrFvD3dHo7Utfovqp7MuGUaF5T+kzEU6BRxsVc 3gX28ifHDhByecdtOp/C6pL8sExcrriURNLKk9mJjqA+FXDKCo5Tu3WLgaPbQIQipN 7mtdM9rohkCX4n+nDxqvOsKweYvCwao/72ZwcrT7ELm+5bHevGb7F1ropoHLE2aqQo fJrSESViVMlxA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 10/13] drm/mediatek: gamma: Make sure relay mode is disabled Date: Mon, 31 Jul 2023 15:04:38 +0200 Message-ID: <20230731130441.173960-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Disable relay mode at the end of LUT programming to make sure that the processed image goes through. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index a846d0dbaa69..659d5c512238 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -195,6 +196,9 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 + /* Disable RELAY mode to pass the processed image */ + cfg_val &=3D ~GAMMA_RELAY_MODE; + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C97EC001DC for ; Mon, 31 Jul 2023 13:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232713AbjGaNFb (ORCPT ); Mon, 31 Jul 2023 09:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231991AbjGaNFL (ORCPT ); Mon, 31 Jul 2023 09:05:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF6811723 for ; Mon, 31 Jul 2023 06:04:57 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 607156607186; Mon, 31 Jul 2023 14:04:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808696; bh=JyiXp46HkBH9WpMUqKvCDJPiZ8ZADL6pJeyaAgpHTPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZVXhalDl1WIW+iMpTN24xPmdb/ngijVWmOxfIKgCRiWCiMEJ6rx2i5KSXZj7UTaWF O2gXayCb5nZ2cBc2mMXcN+i1t7j4ma5fxURbmCl/83omsDbkRMlcoFXqBU2pQLsWUH BBtG+ZczQLNOsU7zeObcpmg/pGlKrb/tTb4eZZoyf3zuSlyAbYnZc9FS54RxJu8Ax2 X/vP0E2Xjok6TGFncAb2HhOx5KJIk6YLR8XSnP0Os1+ceHEGRe8ud3kaMlA8jRt7xa yqgSS8znUh0gRTa0zppT8SVLia5WKzR8TITeJJ5TYVh8dhMVBu2gyHLjFkVGG4CRgC QMP0Rpzd4XV/g== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v7 11/13] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Mon, 31 Jul 2023 15:04:39 +0200 Message-ID: <20230731130441.173960-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 659d5c512238..6fa3f583f8a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -86,6 +87,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -193,6 +204,14 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } } =20 + if (gamma && gamma->data && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D355CC00528 for ; Mon, 31 Jul 2023 13:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232674AbjGaNFg (ORCPT ); Mon, 31 Jul 2023 09:05:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjGaNFM (ORCPT ); Mon, 31 Jul 2023 09:05:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA4EB1729 for ; Mon, 31 Jul 2023 06:04:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 516F46607109; Mon, 31 Jul 2023 14:04:56 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808697; bh=Ty0rQR9CismILWHOJ9rVqiJlfrfqryVc5J0W+SMm8aw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lJ/qBrIlNdzyNH5lU1jL2PV4Di/QpqJC8xTyJ26kc6HThEVPaX3hFrajMuBrZk8fi Ca/ts09vEPNXLg1Y9D/Udxbk3uS42IgWEn6LKqI8SbYqWPXiOJ5+i2TBXlWth6eFul bCLUGFuBRNZj/4oHQ9ztdljuAXvdqyK9VcqsALMFk8pA5Tc97iZKU0a6s/EXyYx+sU wiWuQqfwbU8GRUvQ+zGGjHJRlFC+prditImZKDWO7oEQhJHS8pvFgwk8FR28SkGLMu 8NuIXr3Fq+fPyxGE/xwg49ZfP8nMCDmUCCZcbVffcKyjqqON/DW8rgfOBB7EllmyjD EJTRjRJd+wQ2A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v7 12/13] drm/mediatek: aal: Rewrite kerneldoc for struct mtk_disp_aal Date: Mon, 31 Jul 2023 15:04:40 +0200 Message-ID: <20230731130441.173960-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kerneldoc for struct mtk_disp_aal was entirely wrong: rewrite it to actually document the structure. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index e2e4155faf01..2b51d6f79bfe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -26,9 +26,11 @@ struct mtk_disp_aal_data { }; =20 /** - * struct mtk_disp_aal - DISP_AAL driver structure - * @ddp_comp - structure containing type enum and hardware resources - * @crtc - associated crtc to report irq events to + * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure + * @clk: clock for DISP_AAL controller + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform specific data for DISP_AAL */ struct mtk_disp_aal { struct clk *clk; --=20 2.41.0 From nobody Fri Sep 20 12:23:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E9F0C001DF for ; Mon, 31 Jul 2023 13:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbjGaNFj (ORCPT ); Mon, 31 Jul 2023 09:05:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230095AbjGaNFP (ORCPT ); Mon, 31 Jul 2023 09:05:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9579F1735 for ; Mon, 31 Jul 2023 06:04:59 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3240D6607190; Mon, 31 Jul 2023 14:04:57 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690808697; bh=oi90BFzw+vRNJ7SDlZut9Au2BJmQDV5m4O2v1GmjzUo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Neol1ctUBENvx71Ht4UmmXxdW4B/HmSgfgO4UrxYzk4nyv5+yBqiYSWym7rWoplHb 1wU0NRRTIHt6lmJKxNLd4tzRfL6rYn9YHIlmIX4yQBKeYdFKQcAojop057QAv1/J7x i5KysVJ6F8zps4h31ahGBaNvUsxc+Q+HtynSjyFj5hIJptL7lt/1GtXXKqPvHhLe/6 GEdUPRHMyIyrq8vErVGJt3YDJN/iFNlr2T0ZVd/VjRHWJwetfRD1ingh4+RKimn33v qaIVou/udg7UvsjkZHosSSc3lpn70Fi5zc9gmAd5QRJHLkmbc8ddyW/s6YwuJOn93c gjRLJSOgg8jCA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v7 13/13] drm/mediatek: gamma: Add kerneldoc for struct mtk_disp_gamma Date: Mon, 31 Jul 2023 15:04:41 +0200 Message-ID: <20230731130441.173960-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 6fa3f583f8a1..ee6b06223291 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,8 +54,12 @@ struct mtk_disp_gamma_data { u8 lut_bits; }; =20 -/* - * struct mtk_disp_gamma - DISP_GAMMA driver structure +/** + * struct mtk_disp_gamma - Display Gamma driver structure + * @clk: clock for DISP_GAMMA block + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform data for DISP_GAMMA */ struct mtk_disp_gamma { struct clk *clk; --=20 2.41.0