From nobody Mon Feb 9 05:58:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01D06C001E0 for ; Mon, 31 Jul 2023 12:21:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232543AbjGaMVO (ORCPT ); Mon, 31 Jul 2023 08:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232516AbjGaMU5 (ORCPT ); Mon, 31 Jul 2023 08:20:57 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BF3A19B7; Mon, 31 Jul 2023 05:20:44 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-686ea67195dso3102015b3a.2; Mon, 31 Jul 2023 05:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690806043; x=1691410843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s4prFBDtTDxUhVTvO99EFoP9a0PGrs/5AlOq53YLHt8=; b=T43latipwf94hNdA1OWOFkZdX+hSvZUKnEZAfWAP09DbiklwluJTIReHjB9SIGIgJC JaNB/apsa+4NKVKC3al5IJe7YRtuIof4R7lEQm4kF0nVhIVMwmSNlaUXhQo8Ks4WXsBc C57mm2GlmWZuDmV+D2pxDr1wLloS0Q5msRgjb5XdgMpmP/XySli+o6TkG/UjrtEjWuGl ZNK05Ke1eANaodr3kkhBBYzVTfrmlq0uDXSvxPebUcw+vTAYTTUGpWj/zUyrHMA6AEM3 M+jRDCqZ7/3sU0o1efa1/KvL50z/9k8BAmm5n1sTrvwo2dSAWZTABuZUj08PNbrmaWbX bntQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690806043; x=1691410843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s4prFBDtTDxUhVTvO99EFoP9a0PGrs/5AlOq53YLHt8=; b=C5O47rEPgFnom/s+OaKjAl98k8eLvBbgl8ZW2FPo/JdANC9YlBFFB0Ll2vqxKKHoik XFlq54t9O0Vs7cG+lyWIOIHfE4HKrTQfiwn+mmiRlL9FcoOY72+hIdKluSUJVWuVZK7Q XegI8/iQ+izYW7AanfpU9ho6Dt2BD+qRlf+c5rqRQ6C3KvuBVwUEBEGd9DeAa/033IBc 83F/E4Z1OVQRC0LoDB9kLfSl5HRV8T7YaVdgLppJVbBXg106zDjFtvOxyiwMJdhC6Lu5 840xR1/rDjHV3iZcMHyA4tASiFzCbKexCx6Ca/GC34gpfMHIxKk3eC4qxQ/dcRk/Brf8 7cQA== X-Gm-Message-State: ABy/qLb91B64KlWgRR2q51Nt8KEhEYT0XNa8DVF4R0avO6FMpE1EafZC 8XahZa9Djv79oZljJwbFhW2hose8mBWSSsZl X-Google-Smtp-Source: APBJJlEqfgau5oZPZTE0yUkkq7tTU0dh2HLrdhVD+ojWpaJfmrmDQHufL5nhDUEnegJguQfzrrXHZQ== X-Received: by 2002:a05:6a00:1410:b0:67d:22a6:2f54 with SMTP id l16-20020a056a00141000b0067d22a62f54mr10757976pfu.31.1690806043525; Mon, 31 Jul 2023 05:20:43 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.199]) by smtp.gmail.com with ESMTPSA id y23-20020aa78557000000b00687227dd8f1sm3529559pfn.122.2023.07.31.05.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 05:20:43 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v6 07/13] clk: hisilicon: hi3660: Convert into module Date: Mon, 31 Jul 2023 20:18:07 +0800 Message-Id: <20230731121821.22242-8-mmyangfl@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230731121821.22242-1-mmyangfl@gmail.com> References: <20230731121821.22242-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3660.c | 192 ++++++++--------------------- 1 file changed, 53 insertions(+), 139 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk= -hi3660.c index 41f61726ab19..9ece1d57cbe6 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -5,9 +5,13 @@ */ =20 #include + #include +#include +#include #include #include + #include "clk.h" =20 static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] =3D { @@ -469,169 +473,79 @@ static const struct hisi_gate_clock hi3660_iomcu_gat= e_sep_clks[] =3D { CLK_SET_RATE_PARENT, 0x90, 0, 0, }, }; =20 -static struct hisi_clock_data *clk_crgctrl_data; - -static void hi3660_clk_iomcu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3660_iomcu_gate_sep_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks, - ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), - clk_data); -} - -static void hi3660_clk_pmuctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3660_pmu_gate_clks); - - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - - hisi_clk_register_gate(hi3660_pmu_gate_clks, - ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data); -} +static const struct hisi_clocks hi3660_clk_iomcu_clks =3D { + .gate_sep_clks =3D hi3660_iomcu_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), +}; =20 -static void hi3660_clk_pctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3660_pctrl_gate_clks); +static const struct hisi_clocks hi3660_clk_pmuctrl_clks =3D { + .gate_clks =3D hi3660_pmu_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3660_pmu_gate_clks), +}; =20 - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3660_pctrl_gate_clks, - ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); -} +static const struct hisi_clocks hi3660_clk_pctrl_clks =3D { + .gate_clks =3D hi3660_pctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3660_pctrl_gate_clks), +}; =20 -static void hi3660_clk_sctrl_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi3660_sctrl_gate_clks) + - ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) + - ARRAY_SIZE(hi3660_sctrl_mux_clks) + - ARRAY_SIZE(hi3660_sctrl_divider_clks); +static const struct hisi_clocks hi3660_clk_sctrl_clks =3D { + .mux_clks =3D hi3660_sctrl_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3660_sctrl_mux_clks), + .divider_clks =3D hi3660_sctrl_divider_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3660_sctrl_divider_clks), + .gate_clks =3D hi3660_sctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3660_sctrl_gate_clks), + .gate_sep_clks =3D hi3660_sctrl_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3660_sctrl_gate_sep_clks), +}; =20 - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; - hisi_clk_register_gate(hi3660_sctrl_gate_clks, - ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data); - hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks, - ARRAY_SIZE(hi3660_sctrl_gate_sep_clks), - clk_data); - hisi_clk_register_mux(hi3660_sctrl_mux_clks, - ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data); - hisi_clk_register_divider(hi3660_sctrl_divider_clks, - ARRAY_SIZE(hi3660_sctrl_divider_clks), - clk_data); -} +static const struct hisi_clocks hi3660_clk_crgctrl_clks =3D { + .fixed_rate_clks =3D hi3660_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3660_fixed_rate_clks), + .fixed_factor_clks =3D hi3660_crg_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi3660_crg_fixed_factor_clks), + .mux_clks =3D hi3660_crgctrl_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3660_crgctrl_mux_clks), + .divider_clks =3D hi3660_crgctrl_divider_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3660_crgctrl_divider_clks), + .gate_clks =3D hi3660_crgctrl_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3660_crgctrl_gate_clks), + .gate_sep_clks =3D hi3660_crgctrl_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), +}; =20 static void hi3660_clk_crgctrl_early_init(struct device_node *np) { - int nr =3D ARRAY_SIZE(hi3660_fixed_rate_clks) + - ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + - ARRAY_SIZE(hi3660_crgctrl_gate_clks) + - ARRAY_SIZE(hi3660_crgctrl_mux_clks) + - ARRAY_SIZE(hi3660_crg_fixed_factor_clks) + - ARRAY_SIZE(hi3660_crgctrl_divider_clks); - int i; - - clk_crgctrl_data =3D hisi_clk_init(np, nr); - if (!clk_crgctrl_data) - return; - - for (i =3D 0; i < nr; i++) - clk_crgctrl_data->clk_data.clks[i] =3D ERR_PTR(-EPROBE_DEFER); - - hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, - ARRAY_SIZE(hi3660_fixed_rate_clks), - clk_crgctrl_data); + hisi_clk_early_init(np, &hi3660_clk_crgctrl_clks); } CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl", hi3660_clk_crgctrl_early_init); =20 -static void hi3660_clk_crgctrl_init(struct device_node *np) -{ - struct clk **clks; - int i; - - if (!clk_crgctrl_data) - hi3660_clk_crgctrl_early_init(np); - - /* clk_crgctrl_data initialization failed */ - if (!clk_crgctrl_data) - return; - - hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, - ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), - clk_crgctrl_data); - hisi_clk_register_gate(hi3660_crgctrl_gate_clks, - ARRAY_SIZE(hi3660_crgctrl_gate_clks), - clk_crgctrl_data); - hisi_clk_register_mux(hi3660_crgctrl_mux_clks, - ARRAY_SIZE(hi3660_crgctrl_mux_clks), - clk_crgctrl_data); - hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, - ARRAY_SIZE(hi3660_crg_fixed_factor_clks), - clk_crgctrl_data); - hisi_clk_register_divider(hi3660_crgctrl_divider_clks, - ARRAY_SIZE(hi3660_crgctrl_divider_clks), - clk_crgctrl_data); - - clks =3D clk_crgctrl_data->clk_data.clks; - for (i =3D 0; i < clk_crgctrl_data->clk_data.clk_num; i++) { - if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) !=3D -EPROBE_DEFER) - pr_err("Failed to register crgctrl clock[%d] err=3D%ld\n", - i, PTR_ERR(clks[i])); - } -} - static const struct of_device_id hi3660_clk_match_table[] =3D { { .compatible =3D "hisilicon,hi3660-crgctrl", - .data =3D hi3660_clk_crgctrl_init }, + .data =3D &hi3660_clk_crgctrl_clks }, { .compatible =3D "hisilicon,hi3660-pctrl", - .data =3D hi3660_clk_pctrl_init }, + .data =3D &hi3660_clk_pctrl_clks }, { .compatible =3D "hisilicon,hi3660-pmuctrl", - .data =3D hi3660_clk_pmuctrl_init }, + .data =3D &hi3660_clk_pmuctrl_clks }, { .compatible =3D "hisilicon,hi3660-sctrl", - .data =3D hi3660_clk_sctrl_init }, + .data =3D &hi3660_clk_sctrl_clks }, { .compatible =3D "hisilicon,hi3660-iomcu", - .data =3D hi3660_clk_iomcu_init }, + .data =3D &hi3660_clk_iomcu_clks }, { } }; - -static int hi3660_clk_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *np =3D pdev->dev.of_node; - void (*init_func)(struct device_node *np); - - init_func =3D of_device_get_match_data(dev); - if (!init_func) - return -ENODEV; - - init_func(np); - - return 0; -} +MODULE_DEVICE_TABLE(of, hi3660_clk_match_table); =20 static struct platform_driver hi3660_clk_driver =3D { - .probe =3D hi3660_clk_probe, + .probe =3D hisi_clk_probe, + .remove_new =3D hisi_clk_remove, .driver =3D { .name =3D "hi3660-clk", .of_match_table =3D hi3660_clk_match_table, }, }; =20 -static int __init hi3660_clk_init(void) -{ - return platform_driver_register(&hi3660_clk_driver); -} -core_initcall(hi3660_clk_init); +module_platform_driver(hi3660_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi3660 Clock Driver"); --=20 2.40.1