From nobody Mon Feb 9 14:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF596EB64DD for ; Mon, 31 Jul 2023 01:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjGaBSa (ORCPT ); Sun, 30 Jul 2023 21:18:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229600AbjGaBSZ (ORCPT ); Sun, 30 Jul 2023 21:18:25 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C9DDA1A4; Sun, 30 Jul 2023 18:18:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3080168F; Sun, 30 Jul 2023 18:19:06 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDD283F5A1; Sun, 30 Jul 2023 18:18:21 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT Date: Mon, 31 Jul 2023 02:17:23 +0100 Message-Id: <20230731011725.7228-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.8 In-Reply-To: <20230731011725.7228-1-andre.przywara@arm.com> References: <20230731011725.7228-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some DT nodes with the Zero 2, but comes with a different PMIC. Move the common parts (except the PMIC) into a new shared file, and include that from the existing board .dts file. No functional change, the generated DTB is the same, except some phandle numbering differences. Signed-off-by: Andre Przywara --- .../allwinner/sun50i-h616-orangepi-zero2.dts | 119 +--------------- .../allwinner/sun50i-h616-orangepi-zerox.dtsi | 131 ++++++++++++++++++ 2 files changed, 132 insertions(+), 118 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero= x.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index cb8600d0ea1ef..c786b170fb9a8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -5,95 +5,19 @@ =20 /dts-v1/; =20 -#include "sun50i-h616.dtsi" - -#include -#include -#include +#include "sun50i-h616-orangepi-zerox.dtsi" =20 / { model =3D "OrangePi Zero2"; compatible =3D "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; - - aliases { - ethernet0 =3D &emac0; - serial0 =3D &uart0; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - leds { - compatible =3D "gpio-leds"; - - led-0 { - function =3D LED_FUNCTION_POWER; - color =3D ; - gpios =3D <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state =3D "on"; - }; - - led-1 { - function =3D LED_FUNCTION_STATUS; - color =3D ; - gpios =3D <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vcc-5v"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible =3D "regulator-fixed"; - regulator-name =3D "usb1-vbus"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - vin-supply =3D <®_vcc5v>; - enable-active-high; - gpio =3D <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; }; =20 -&ehci1 { - status =3D "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - &emac0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ext_rgmii_pins>; - phy-mode =3D "rgmii"; - phy-handle =3D <&ext_rgmii_phy>; phy-supply =3D <®_dcdce>; - allwinner,rx-delay-ps =3D <3100>; - allwinner,tx-delay-ps =3D <700>; - status =3D "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <1>; - }; }; =20 &mmc0 { vmmc-supply =3D <®_dcdce>; - cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width =3D <4>; - status =3D "okay"; -}; - -&ohci1 { - status =3D "okay"; }; =20 &r_rsb { @@ -211,44 +135,3 @@ &pio { vcc-ph-supply =3D <®_aldo1>; vcc-pi-supply =3D <®_aldo1>; }; - -&spi0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "jedec,spi-nor"; - reg =3D <0>; - spi-max-frequency =3D <40000000>; - }; -}; - -&uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&uart0_ph_pins>; - status =3D "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode =3D "peripheral"; - status =3D "okay"; -}; - -&usbphy { - usb1_vbus-supply =3D <®_usb1_vbus>; - status =3D "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi = b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi new file mode 100644 index 0000000000000..56c7e1d87bd95 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zerox.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + aliases { + ethernet0 =3D &emac0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_POWER; + color =3D ; + gpios =3D <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state =3D "on"; + }; + + led-1 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + enable-active-high; + gpio =3D <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; +}; + +&ehci1 { + status =3D "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ext_rgmii_pins>; + phy-mode =3D "rgmii"; + phy-handle =3D <&ext_rgmii_phy>; + allwinner,rx-delay-ps =3D <3100>; + allwinner,tx-delay-ps =3D <700>; + status =3D "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb1_vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; --=20 2.35.8