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([178.197.222.183]) by smtp.gmail.com with ESMTPSA id h2-20020aa7c602000000b00522536c2e6esm4045756edq.38.2023.07.30.04.15.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jul 2023 04:15:44 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] ARM: dts: microchip: split interrupts per cells Date: Sun, 30 Jul 2023 13:15:41 +0200 Message-Id: <20230730111542.98238-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Each interrupt should be in its own cell. This is much more readable. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/microchip/at91rm9200.dtsi | 12 +++--- arch/arm/boot/dts/microchip/at91sam9260.dtsi | 12 +++--- arch/arm/boot/dts/microchip/sama5d2.dtsi | 6 +-- arch/arm/boot/dts/microchip/sama7g5.dtsi | 40 ++++++++++---------- 4 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dt= s/microchip/at91rm9200.dtsi index 37b500f6f395..16c675e3a890 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -135,9 +135,9 @@ tcb0: timer@fffa0000 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0xfffa0000 0x100>; - interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18= >, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -147,9 +147,9 @@ tcb1: timer@fffa4000 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0xfffa4000 0x100>; - interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0 - 21 IRQ_TYPE_LEVEL_HIGH 0 - 22 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>, + <21 IRQ_TYPE_LEVEL_HIGH 0>, + <22 IRQ_TYPE_LEVEL_HIGH 0>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21= >, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/d= ts/microchip/at91sam9260.dtsi index 27b4a21f13c1..e56d5546554c 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -148,9 +148,9 @@ tcb0: timer@fffa0000 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0xfffa0000 0x100>; - interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18= >, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -160,9 +160,9 @@ tcb1: timer@fffdc000 { #address-cells =3D <1>; #size-cells =3D <0>; reg =3D <0xfffdc000 0x100>; - interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0 - 27 IRQ_TYPE_LEVEL_HIGH 0 - 28 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>, + <27 IRQ_TYPE_LEVEL_HIGH 0>, + <28 IRQ_TYPE_LEVEL_HIGH 0>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27= >, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names =3D "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/m= icrochip/sama5d2.dtsi index daeeb24e5f4d..5f8e297e19ed 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -382,9 +382,9 @@ AT91_XDMAC_DT_PERID(21))>, macb0: ethernet@f8008000 { compatible =3D "atmel,sama5d2-gem"; reg =3D <0xf8008000 0x1000>; - interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ - 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ - 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <66 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names =3D "hclk", "pclk"; status =3D "disabled"; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/m= icrochip/sama7g5.dtsi index 9642a42d84e6..269e0a3ca269 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -366,8 +366,8 @@ can0: can@e0828000 { compatible =3D "bosch,m_can"; reg =3D <0xe0828000 0x100>, <0x100000 0x7800>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; clock-names =3D "hclk", "cclk"; @@ -382,8 +382,8 @@ can1: can@e082c000 { compatible =3D "bosch,m_can"; reg =3D <0xe082c000 0x100>, <0x100000 0xbc00>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; clock-names =3D "hclk", "cclk"; @@ -398,8 +398,8 @@ can2: can@e0830000 { compatible =3D "bosch,m_can"; reg =3D <0xe0830000 0x100>, <0x100000 0x10000>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; clock-names =3D "hclk", "cclk"; @@ -414,8 +414,8 @@ can3: can@e0834000 { compatible =3D "bosch,m_can"; reg =3D <0xe0834000 0x100>, <0x110000 0x4400>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; clock-names =3D "hclk", "cclk"; @@ -430,8 +430,8 @@ can4: can@e0838000 { compatible =3D "bosch,m_can"; reg =3D <0xe0838000 0x100>, <0x110000 0x8800>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; clock-names =3D "hclk", "cclk"; @@ -446,8 +446,8 @@ can5: can@e083c000 { compatible =3D "bosch,m_can"; reg =3D <0xe083c000 0x100>, <0x110000 0xcc00>; reg-names =3D "m_can", "message_ram"; - interrupts =3D ; + interrupts =3D , + ; interrupt-names =3D "int0", "int1"; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; clock-names =3D "hclk", "cclk"; @@ -845,12 +845,12 @@ uart7: serial@200 { gmac0: ethernet@e2800000 { compatible =3D "microchip,sama7g5-gem"; reg =3D <0xe2800000 0x1000>; - interrupts =3D ; + interrupts =3D , + , + , + , + , + ; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>= , <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; clock-names =3D "pclk", "hclk", "tx_clk", "tsu_clk"; assigned-clocks =3D <&pmc PMC_TYPE_GCK 51>; @@ -861,8 +861,8 @@ GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH gmac1: ethernet@e2804000 { compatible =3D "microchip,sama7g5-emac"; reg =3D <0xe2804000 0x1000>; - interrupts =3D ; + interrupts =3D , + ; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; clock-names =3D "pclk", "hclk"; status =3D "disabled"; --=20 2.34.1