From nobody Wed Sep 17 05:51:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9909DC04FDF for ; Sat, 29 Jul 2023 01:36:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237455AbjG2Bfz (ORCPT ); Fri, 28 Jul 2023 21:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236363AbjG2Bfs (ORCPT ); Fri, 28 Jul 2023 21:35:48 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40B8D2D5D for ; Fri, 28 Jul 2023 18:35:47 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id 41be03b00d2f7-55c7bb27977so2436040a12.0 for ; Fri, 28 Jul 2023 18:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690594547; x=1691199347; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=YXSv3END2Klqtx+yY5wHfQk5zXL7nBePduqABQQ83FM=; b=xjh6WzfpEV1RIRBvrT6h0mWl/5NIXPREobuFZQi3RL9n9nfwT6WhJvboZ8uGRKYk64 Yt/NZx5iAq6LD2P8zJHcShyTuWnPPVAVwZ7s5UC7Ub38emeW2tPRPJWKNGPu0pOkOcRv 1hnqHWplD7S1lZ1bCLN8v1C7cg1OH5GJqLo1C/8fkmlsMCsLdOJhDbw0CMJSdIRvVJSd eSi31mjewEiAOjxoaWcFuJKjZhphR7SfyJeyKlx97pU2Ypr8ZdeKlp1SikYc9bVLuZnN FNKKGK64OIfOQQ1MnZM7dkBH/oHzh1inoFZnUulrkWaGD5+xpzezsSD+aykKUifV/NYd Pk6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690594547; x=1691199347; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=YXSv3END2Klqtx+yY5wHfQk5zXL7nBePduqABQQ83FM=; b=TCkxq/LGAzhFmj0fngrPwmmo64yQC1He/Ue66g07ecnZMaFZ+2gkV/qY7C7zn693Z/ ay4HfEjgf/uJZVJ4eYAebDFvTFTYJW3RhG8nBtVbd7+fZZtbnZnRflBjCMvJ06+5/nY7 gtXG/jg3QbRIQgB9TnOEZ+9fIIEt0uLMWPKxCUn7655+j+OWAA+kl7w93/aykkqnV1fg 4GFBVrltHhkB3xptQgKHFBzWBq6fFy1BkUWeSSTBnOC+yV8/gDntR6HZYs2pxlo7MrS2 madkL5lx8gIzkxftYOEtEQK2Bf6ucTmn+TwmnvETySG/vROlPJmokQ7eLlXlEsojZwcg KK3w== X-Gm-Message-State: ABy/qLaLUb0jPFuM31owiHHQQx0cYImq8m1icegDZ34dKlib7j/x+KEj URSwPc7qQXTwJIjRiv/7QsIMhoe5UhQ= X-Google-Smtp-Source: APBJJlE04anqFJHsZ9xRSAXjata30eLPyNsuSxyxD1HAJrkEtTHP+UsU3nIWi5hxRkWaA/cKbC5UTvclk9Y= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:ce84:b0:1b8:2cee:946b with SMTP id f4-20020a170902ce8400b001b82cee946bmr15038plg.11.1690594546523; Fri, 28 Jul 2023 18:35:46 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 28 Jul 2023 18:35:08 -0700 In-Reply-To: <20230729013535.1070024-1-seanjc@google.com> Mime-Version: 1.0 References: <20230729013535.1070024-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.487.g6d72f3e995-goog Message-ID: <20230729013535.1070024-3-seanjc@google.com> Subject: [PATCH v4 02/29] drm/i915/gvt: remove interface intel_gvt_is_valid_gfn From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Zhenyu Wang , Zhi Wang Cc: kvm@vger.kernel.org, intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yan Zhao , Yongwei Ma , Ben Gardon Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yan Zhao Currently intel_gvt_is_valid_gfn() is called in two places: (1) shadowing guest GGTT entry (2) shadowing guest PPGTT leaf entry, which was introduced in commit cc753fbe1ac4 ("drm/i915/gvt: validate gfn before set shadow page entry"). However, now it's not necessary to call this interface any more, because a. GGTT partial write issue has been fixed by commit bc0686ff5fad ("drm/i915/gvt: support inconsecutive partial gtt entry write") commit 510fe10b6180 ("drm/i915/gvt: fix a bug of partially write ggtt enties") b. PPGTT resides in normal guest RAM and we only treat 8-byte writes as valid page table writes. Any invalid GPA found is regarded as an error, either due to guest misbehavior/attack or bug in host shadow code. So,rather than do GFN pre-checking and replace invalid GFNs with scratch GFN and continue silently, just remove the pre-checking and abort PPGTT shadowing on error detected. c. GFN validity check is still performed in intel_gvt_dma_map_guest_page() --> gvt_pin_guest_page(). It's more desirable to call VFIO interface to do both validity check and mapping. Calling intel_gvt_is_valid_gfn() to do GFN validity check from KVM side while later mapping the GFN through VFIO interface is unnecessarily fragile and confusing for unaware readers. Signed-off-by: Yan Zhao [sean: remove now-unused local variables] Acked-by: Zhi Wang Tested-by: Yongwei Ma Signed-off-by: Sean Christopherson --- drivers/gpu/drm/i915/gvt/gtt.c | 36 +--------------------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 58b9b316ae46..f30922c55a0c 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -49,22 +49,6 @@ static bool enable_out_of_sync =3D false; static int preallocated_oos_pages =3D 8192; =20 -static bool intel_gvt_is_valid_gfn(struct intel_vgpu *vgpu, unsigned long = gfn) -{ - struct kvm *kvm =3D vgpu->vfio_device.kvm; - int idx; - bool ret; - - if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) - return false; - - idx =3D srcu_read_lock(&kvm->srcu); - ret =3D kvm_is_visible_gfn(kvm, gfn); - srcu_read_unlock(&kvm->srcu, idx); - - return ret; -} - /* * validate a gm address and related range size, * translate it to host gm address @@ -1333,11 +1317,9 @@ static int ppgtt_populate_shadow_entry(struct intel_= vgpu *vgpu, static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt) { struct intel_vgpu *vgpu =3D spt->vgpu; - struct intel_gvt *gvt =3D vgpu->gvt; - const struct intel_gvt_gtt_pte_ops *ops =3D gvt->gtt.pte_ops; struct intel_vgpu_ppgtt_spt *s; struct intel_gvt_gtt_entry se, ge; - unsigned long gfn, i; + unsigned long i; int ret; =20 trace_spt_change(spt->vgpu->id, "born", spt, @@ -1354,13 +1336,6 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgt= t_spt *spt) ppgtt_generate_shadow_entry(&se, s, &ge); ppgtt_set_shadow_entry(spt, &se, i); } else { - gfn =3D ops->get_pfn(&ge); - if (!intel_gvt_is_valid_gfn(vgpu, gfn)) { - ops->set_pfn(&se, gvt->gtt.scratch_mfn); - ppgtt_set_shadow_entry(spt, &se, i); - continue; - } - ret =3D ppgtt_populate_shadow_entry(vgpu, spt, i, &ge); if (ret) goto fail; @@ -2335,14 +2310,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu= *vgpu, unsigned int off, m.val64 =3D e.val64; m.type =3D e.type; =20 - /* one PTE update may be issued in multiple writes and the - * first write may not construct a valid gfn - */ - if (!intel_gvt_is_valid_gfn(vgpu, gfn)) { - ops->set_pfn(&m, gvt->gtt.scratch_mfn); - goto out; - } - ret =3D intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE, &dma_addr); if (ret) { @@ -2359,7 +2326,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu = *vgpu, unsigned int off, ops->clear_present(&m); } =20 -out: ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index); =20 ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index); --=20 2.41.0.487.g6d72f3e995-goog