From nobody Tue Sep 9 22:25:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C05C05051 for ; Thu, 27 Jul 2023 21:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230204AbjG0V1F (ORCPT ); Thu, 27 Jul 2023 17:27:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230076AbjG0V0z (ORCPT ); Thu, 27 Jul 2023 17:26:55 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C45C1B8 for ; Thu, 27 Jul 2023 14:26:53 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-686fc0d3c92so711446b3a.0 for ; Thu, 27 Jul 2023 14:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690493212; x=1691098012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L3MSUXAZDlHxvJw5XBpFpvl/fyG6WFk9gov0cKUKQOU=; b=WUyJwKJPX1jLH0ROd0fzWsfMZAkoQJ/zQofoMYk2lYdpobktAenlvABnk4JZwHpjY5 WvDq42U+gPL5MSTDxgvDRE6dXZTLh2FU/It8UyINzwEmymclonR4Y0AOvW5Z9Q/HA+hP UlAqHQbkeq1NLlVumQpfaDTbUcBjZ9pc/asdJ/p2EJm3zv0/rShcn1MU94GGVB8bsh+p rAkAcX9PQ06tbc6DdqNHbIa9qN4MoDe9IOgqU293iqT+rn1hHXDprtEdFDmsD5goGQnb KHFXw3D3dfM3/81YOre3JxqvqQjO5sIPW33VQ3yHsa9UPrEKTcSMpZBUp1PjeVpohIQh IUuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690493212; x=1691098012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L3MSUXAZDlHxvJw5XBpFpvl/fyG6WFk9gov0cKUKQOU=; b=lO5ZcDiEcgOCj773M8Zg+8l2LsRISpvSBwl+YFHGqNX0T/ib9qE9zc/4QMSEL7CZ1g 1GHFWY0+2MXtBPSM50Szkg1WPGMrdBnc8O8z2wKkAREYyTVEtEnN2VTuzaJaxYB+3jZ9 T8EckZfqRRIuPII5cs/Am1mrOFSJ9MZuSrLKW0f9x+MtSQFiHgG16SHrIxQGQMfG98xJ 1mf6lSyZ2p3qwDP9L80tjaxMTX+1gC+PqmB5JzBDeRb+7mV0onED7EGK6Dg7YBsxPiWq sBllkNx06TUTwjrUyKuPDb650w0RAClogDdMn7TksYj42pDKZseGfUxht4WZykjqlGaw Y09g== X-Gm-Message-State: ABy/qLZYIPwMWCB8uLEe4C9RRbFKMCW1BSa+ZgpgB3skCBpYvdGZX2oR vtgVvekabSKWiedhVQHuJ+rw9A== X-Google-Smtp-Source: APBJJlGaUoECRIux0BUm3diAsqoj6PNZLuLLwkdpIzX5n1LpY2mGSBcBTtHRABOlgGcWfWQnA6vSiQ== X-Received: by 2002:a05:6a21:6d87:b0:137:68c3:c86f with SMTP id wl7-20020a056a216d8700b0013768c3c86fmr324290pzb.55.1690493212471; Thu, 27 Jul 2023 14:26:52 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id c5-20020aa78c05000000b00682562b1549sm1912312pfd.24.2023.07.27.14.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:26:52 -0700 (PDT) From: Charlie Jenkins To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v8 1/4] RISC-V: mm: Restrict address space for sv39,sv48,sv57 Date: Thu, 27 Jul 2023 14:26:26 -0700 Message-ID: <20230727212647.4182407-2-charlie@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212647.4182407-1-charlie@rivosinc.com> References: <20230727212647.4182407-1-charlie@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make sv48 the default address space for mmap as some applications currently depend on this assumption. A hint address passed to mmap will cause the largest address space that fits entirely into the hint to be used. If the hint is less than or equal to 1<<38, an sv39 address will be used. An exception is that if the hint address is 0, then a sv48 address will be used. After an address space is completely full, the next smallest address space will be used. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/pgtable.h | 20 +++++++++++- arch/riscv/include/asm/processor.h | 52 ++++++++++++++++++++++++++---- 3 files changed, 66 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index c24280774caf..5d3368d5585c 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -49,7 +49,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * the loader. We need to make sure that it is out of the way of the prog= ram * that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) +#define ELF_ET_DYN_BASE ((DEFAULT_MAP_WINDOW / 3) * 2) =20 #ifdef CONFIG_64BIT #ifdef CONFIG_COMPAT diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 75970ee2bda2..c76a1ef094a4 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -63,8 +63,26 @@ * position vmemmap directly below the VMALLOC region. */ #ifdef CONFIG_64BIT +#define VA_BITS_SV39 39 +#define VA_BITS_SV48 48 +#define VA_BITS_SV57 57 + +#define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) +#define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) +#define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) + #define VA_BITS (pgtable_l5_enabled ? \ - 57 : (pgtable_l4_enabled ? 48 : 39)) + VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) + +#ifdef CONFIG_COMPAT +#define MMAP_VA_BITS_64 ((VA_BITS >=3D VA_BITS_SV48) ? VA_BITS_SV48 : VA_B= ITS) +#define MMAP_MIN_VA_BITS_64 ((VA_BITS >=3D VA_BITS_SV39) ? VA_BITS_SV39 : = VA_BITS) +#define MMAP_VA_BITS (test_thread_flag(TIF_32BIT) ? 32 : MMAP_VA_BITS_64) +#define MMAP_MIN_VA_BITS (test_thread_flag(TIF_32BIT) ? 32 : MMAP_MIN_VA_B= ITS_64) +#else +#define MMAP_VA_BITS ((VA_BITS >=3D VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) +#define MMAP_MIN_VA_BITS ((VA_BITS >=3D VA_BITS_SV39) ? VA_BITS_SV39 : VA_= BITS) +#endif #else #define VA_BITS 32 #endif diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index c950a8d9edef..e810244ea951 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,19 +13,59 @@ =20 #include =20 +#ifdef CONFIG_64BIT +#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) +#define STACK_TOP_MAX TASK_SIZE_64 + +#define arch_get_mmap_end(addr, len, flags) \ +({ \ + unsigned long mmap_end; \ + typeof(addr) _addr =3D (addr); \ + if ((_addr) =3D=3D 0 || (IS_ENABLED(CONFIG_COMPAT) && test_thread_flag(TI= F_32BIT))) \ + mmap_end =3D DEFAULT_MAP_WINDOW; \ + else if ((_addr) >=3D VA_USER_SV57) \ + mmap_end =3D STACK_TOP_MAX; \ + else if ((((_addr) >=3D VA_USER_SV48)) && (VA_BITS >=3D VA_BITS_SV48)) \ + mmap_end =3D VA_USER_SV48; \ + else \ + mmap_end =3D VA_USER_SV39; \ + mmap_end; \ +}) + +#define arch_get_mmap_base(addr, base) \ +({ \ + unsigned long mmap_base; \ + typeof(addr) _addr =3D (addr); \ + typeof(base) _base =3D (base); \ + unsigned long rnd_gap =3D (_base) - DEFAULT_MAP_WINDOW; \ + if ((_addr) =3D=3D 0 || (IS_ENABLED(CONFIG_COMPAT) && test_thread_flag(TI= F_32BIT))) \ + mmap_base =3D (_base); \ + else if (((_addr) >=3D VA_USER_SV57) && (VA_BITS >=3D VA_BITS_SV57)) \ + mmap_base =3D VA_USER_SV57 + rnd_gap; \ + else if ((((_addr) >=3D VA_USER_SV48)) && (VA_BITS >=3D VA_BITS_SV48)) \ + mmap_base =3D VA_USER_SV48 + rnd_gap; \ + else \ + mmap_base =3D VA_USER_SV39 + rnd_gap; \ + mmap_base; \ +}) + +#else +#define DEFAULT_MAP_WINDOW TASK_SIZE +#define STACK_TOP_MAX TASK_SIZE +#endif +#define STACK_ALIGN 16 + +#define STACK_TOP DEFAULT_MAP_WINDOW + /* * This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) - -#define STACK_TOP TASK_SIZE #ifdef CONFIG_64BIT -#define STACK_TOP_MAX TASK_SIZE_64 +#define TASK_UNMAPPED_BASE PAGE_ALIGN((UL(1) << MMAP_MIN_VA_BITS) / 3) #else -#define STACK_TOP_MAX TASK_SIZE +#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) #endif -#define STACK_ALIGN 16 =20 #ifndef __ASSEMBLY__ =20 --=20 2.41.0 From nobody Tue Sep 9 22:25:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E28DAC00528 for ; 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Thu, 27 Jul 2023 14:26:53 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id c5-20020aa78c05000000b00682562b1549sm1912312pfd.24.2023.07.27.14.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:26:53 -0700 (PDT) From: Charlie Jenkins To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v8 2/4] RISC-V: mm: Add tests for RISC-V mm Date: Thu, 27 Jul 2023 14:26:27 -0700 Message-ID: <20230727212647.4182407-3-charlie@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212647.4182407-1-charlie@rivosinc.com> References: <20230727212647.4182407-1-charlie@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add tests that enforce mmap hint address behavior. mmap should default to sv48. mmap will provide an address at the highest address space that can fit into the hint address, unless the hint address is less than sv39 and not 0, then it will return a sv39 address. These tests are split into two files: mmap_default.c and mmap_bottomup.c because a new process must be exec'd in order to change the mmap layout. The run_mmap.sh script sets the stack to be unlimited for the mmap_bottomup.c test which triggers a bottomup layout. Signed-off-by: Charlie Jenkins --- tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/mm/.gitignore | 2 + tools/testing/selftests/riscv/mm/Makefile | 15 +++++ .../riscv/mm/testcases/mmap_bottomup.c | 35 ++++++++++ .../riscv/mm/testcases/mmap_default.c | 35 ++++++++++ .../selftests/riscv/mm/testcases/mmap_test.h | 64 +++++++++++++++++++ .../selftests/riscv/mm/testcases/run_mmap.sh | 12 ++++ 7 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/mm/.gitignore create mode 100644 tools/testing/selftests/riscv/mm/Makefile create mode 100644 tools/testing/selftests/riscv/mm/testcases/mmap_bottomu= p.c create mode 100644 tools/testing/selftests/riscv/mm/testcases/mmap_default= .c create mode 100644 tools/testing/selftests/riscv/mm/testcases/mmap_test.h create mode 100755 tools/testing/selftests/riscv/mm/testcases/run_mmap.sh diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftes= ts/riscv/Makefile index f4b3d5c9af5b..4a9ff515a3a0 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?=3D $(shell uname -m 2>/dev/null || echo not) =20 ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?=3D hwprobe vector +RISCV_SUBTARGETS ?=3D hwprobe vector mm else RISCV_SUBTARGETS :=3D endif diff --git a/tools/testing/selftests/riscv/mm/.gitignore b/tools/testing/se= lftests/riscv/mm/.gitignore new file mode 100644 index 000000000000..5c2c57cb950c --- /dev/null +++ b/tools/testing/selftests/riscv/mm/.gitignore @@ -0,0 +1,2 @@ +mmap_bottomup +mmap_default diff --git a/tools/testing/selftests/riscv/mm/Makefile b/tools/testing/self= tests/riscv/mm/Makefile new file mode 100644 index 000000000000..11e0f0568923 --- /dev/null +++ b/tools/testing/selftests/riscv/mm/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +# Additional include paths needed by kselftest.h and local headers +CFLAGS +=3D -D_GNU_SOURCE -std=3Dgnu99 -I. + +TEST_GEN_FILES :=3D testcases/mmap_default testcases/mmap_bottomup + +TEST_PROGS :=3D testcases/run_mmap.sh + +include ../../lib.mk + +$(OUTPUT)/mm: testcases/mmap_default.c testcases/mmap_bottomup.c testcases= /mmap_tests.h + $(CC) -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/mm/testcases/mmap_bottomup.c b/t= ools/testing/selftests/riscv/mm/testcases/mmap_bottomup.c new file mode 100644 index 000000000000..b29379f7e478 --- /dev/null +++ b/tools/testing/selftests/riscv/mm/testcases/mmap_bottomup.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include + +#include "../../kselftest_harness.h" + +TEST(infinite_rlimit) +{ +// Only works on 64 bit +#if __riscv_xlen =3D=3D 64 + struct addresses mmap_addresses; + + EXPECT_EQ(BOTTOM_UP, memory_layout()); + + do_mmaps(&mmap_addresses); + + EXPECT_NE(MAP_FAILED, mmap_addresses.no_hint); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_37_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_38_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_46_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_47_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_55_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_56_addr); + + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.no_hint); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_37_addr); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_38_addr); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_46_addr); + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_47_addr); + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_55_addr); + EXPECT_GT(1UL << 56, (unsigned long)mmap_addresses.on_56_addr); +#endif +} + +TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/mm/testcases/mmap_default.c b/to= ols/testing/selftests/riscv/mm/testcases/mmap_default.c new file mode 100644 index 000000000000..d1accb91b726 --- /dev/null +++ b/tools/testing/selftests/riscv/mm/testcases/mmap_default.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include + +#include "../../kselftest_harness.h" + +TEST(default_rlimit) +{ +// Only works on 64 bit +#if __riscv_xlen =3D=3D 64 + struct addresses mmap_addresses; + + EXPECT_EQ(TOP_DOWN, memory_layout()); + + do_mmaps(&mmap_addresses); + + EXPECT_NE(MAP_FAILED, mmap_addresses.no_hint); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_37_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_38_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_46_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_47_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_55_addr); + EXPECT_NE(MAP_FAILED, mmap_addresses.on_56_addr); + + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.no_hint); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_37_addr); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_38_addr); + EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_46_addr); + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_47_addr); + EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_55_addr); + EXPECT_GT(1UL << 56, (unsigned long)mmap_addresses.on_56_addr); +#endif +} + +TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/mm/testcases/mmap_test.h b/tools= /testing/selftests/riscv/mm/testcases/mmap_test.h new file mode 100644 index 000000000000..98a892de5d19 --- /dev/null +++ b/tools/testing/selftests/riscv/mm/testcases/mmap_test.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _TESTCASES_MMAP_TEST_H +#define _TESTCASES_MMAP_TEST_H +#include +#include +#include + +#define TOP_DOWN 0 +#define BOTTOM_UP 1 + +struct addresses { + int *no_hint; + int *on_37_addr; + int *on_38_addr; + int *on_46_addr; + int *on_47_addr; + int *on_55_addr; + int *on_56_addr; +}; + +void do_mmaps(struct addresses *mmap_addresses) +{ + /* + * Place all of the hint addresses on the boundaries of mmap + * sv39, sv48, sv57 + * User addresses end at 1<<38, 1<<47, 1<<56 respectively + */ + void *on_37_bits =3D (void *)(1UL << 37); + void *on_38_bits =3D (void *)(1UL << 38); + void *on_46_bits =3D (void *)(1UL << 46); + void *on_47_bits =3D (void *)(1UL << 47); + void *on_55_bits =3D (void *)(1UL << 55); + void *on_56_bits =3D (void *)(1UL << 56); + + int prot =3D PROT_READ | PROT_WRITE; + int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; + + mmap_addresses->no_hint =3D + mmap(NULL, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_37_addr =3D + mmap(on_37_bits, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_38_addr =3D + mmap(on_38_bits, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_46_addr =3D + mmap(on_46_bits, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_47_addr =3D + mmap(on_47_bits, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_55_addr =3D + mmap(on_55_bits, 5 * sizeof(int), prot, flags, 0, 0); + mmap_addresses->on_56_addr =3D + mmap(on_56_bits, 5 * sizeof(int), prot, flags, 0, 0); +} + +int memory_layout(void) +{ + int prot =3D PROT_READ | PROT_WRITE; + int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; + + void *value1 =3D mmap(NULL, sizeof(int), prot, flags, 0, 0); + void *value2 =3D mmap(NULL, sizeof(int), prot, flags, 0, 0); + + return value2 > value1; +} +#endif /* _TESTCASES_MMAP_TEST_H */ diff --git a/tools/testing/selftests/riscv/mm/testcases/run_mmap.sh b/tools= /testing/selftests/riscv/mm/testcases/run_mmap.sh new file mode 100755 index 000000000000..ca5ad7c48bad --- /dev/null +++ b/tools/testing/selftests/riscv/mm/testcases/run_mmap.sh @@ -0,0 +1,12 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +original_stack_limit=3D$(ulimit -s) + +./mmap_default + +# Force mmap_bottomup to be ran with bottomup memory due to +# the unlimited stack +ulimit -s unlimited +./mmap_bottomup +ulimit -s $original_stack_limit --=20 2.41.0 From nobody Tue Sep 9 22:25:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A8E3EB64DD for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org sv57 is supported in the kernel so pgtable.h should reflect that. Signed-off-by: Charlie Jenkins Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/pgtable.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index c76a1ef094a4..b551467a1dd8 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -848,14 +848,16 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. * Task size is: - * - 0x9fc00000 (~2.5GB) for RV32. - * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu - * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x9fc00000 (~2.5GB) for RV32. + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu * * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V * Instruction Set Manual Volume II: Privileged Architecture" states that * "load and store effective addresses, which are 64bits, must have bits * 63=E2=80=9348 all equal to bit 47, or else a page-fault exception will = occur." + * Similarly for SV57, bits 63=E2=80=9357 must be equal to bit 56. */ #ifdef CONFIG_64BIT #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) --=20 2.41.0 From nobody Tue Sep 9 22:25:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 734CBC00528 for ; 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Thu, 27 Jul 2023 14:26:56 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id c5-20020aa78c05000000b00682562b1549sm1912312pfd.24.2023.07.27.14.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:26:56 -0700 (PDT) From: Charlie Jenkins To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v8 4/4] RISC-V: mm: Document mmap changes Date: Thu, 27 Jul 2023 14:26:29 -0700 Message-ID: <20230727212647.4182407-5-charlie@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212647.4182407-1-charlie@rivosinc.com> References: <20230727212647.4182407-1-charlie@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The behavior of mmap is modified with this patch series, so explain the changes to the mmap hint address behavior. Signed-off-by: Charlie Jenkins Reviewed-by: Alexandre Ghiti --- Documentation/riscv/vm-layout.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/riscv/vm-layout.rst b/Documentation/riscv/vm-lay= out.rst index 5462c84f4723..69ff6da1dbf8 100644 --- a/Documentation/riscv/vm-layout.rst +++ b/Documentation/riscv/vm-layout.rst @@ -133,3 +133,25 @@ RISC-V Linux Kernel SV57 ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, B= PF ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel __________________|____________|__________________|_________|___________= _________________________________________________ + + +Userspace VAs +-------------------- +To maintain compatibility with software that relies on the VA space with a +maximum of 48 bits the kernel will, by default, return virtual addresses to +userspace from a 48-bit range (sv48). This default behavior is achieved by +passing 0 into the hint address parameter of mmap. On CPUs with an address= space +smaller than sv48, the CPU maximum supported address space will be the def= ault. + +Software can "opt-in" to receiving VAs from another VA space by providing +a hint address to mmap. A hint address passed to mmap will cause the large= st +address space that fits entirely into the hint to be used, unless there is= no +space left in the address space. If there is no space available in the req= uested +address space, an address in the next smallest available address space wil= l be +returned. + +For example, in order to obtain 48-bit VA space, a hint address greater th= an +:code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspa= ce +ending at :code:`1 << 47` and the addresses beyond this are reserved for t= he +kernel. Similarly, to obtain 57-bit VA space addresses, a hint address gre= ater +than or equal to :code:`1 << 56` must be provided. --=20 2.41.0