From nobody Fri Sep 20 15:43:40 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0185C001DC for ; Thu, 27 Jul 2023 16:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234478AbjG0QaX (ORCPT ); Thu, 27 Jul 2023 12:30:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233700AbjG0QaQ (ORCPT ); Thu, 27 Jul 2023 12:30:16 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A76C02D4B; Thu, 27 Jul 2023 09:30:15 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 2B20C83929; Thu, 27 Jul 2023 18:30:14 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Duje=20Mihanovi=C4=87?= , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH v2 4/9] dt-bindings: clock: Add Marvell PXA1908 clock bindings Date: Thu, 27 Jul 2023 18:29:02 +0200 Message-ID: <20230727162909.6031-5-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727162909.6031-1-duje.mihanovic@skole.hr> References: <20230727162909.6031-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dt bindings and documentation for the Marvell PXA1908 clock controller. Signed-off-by: Duje Mihanovi=C4=87 --- .../bindings/clock/marvell,pxa1908.yaml | 47 ++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908= .yaml create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..a5af7992b1b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanovi=C4=87 + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, = MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible =3D "marvell,pxa1908-apmu"; + reg =3D <0xd4282800 0x400>; + #clock-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindi= ngs/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..dbb487baf65f --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 +#define PXA1908_MPMU_NR_CLKS 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 17 +#define PXA1908_CLK_SSP2 20 +#define PXA1908_CLK_TWSI1 25 +#define PXA1908_CLK_THERMAL 28 +#define PXA1908_CLK_TWSI3 29 +#define PXA1908_APBC_NR_CLKS 48 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 7 +#define PXA1908_CLK_TWSI2 10 +#define PXA1908_CLK_AICER 14 +#define PXA1908_APBCP_NR_CLKS 14 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 9 +#define PXA1908_CLK_ISP 14 +#define PXA1908_CLK_GATE_CTRL 16 +#define PXA1908_CLK_DSI1 17 +#define PXA1908_CLK_DISP1 19 +#define PXA1908_CLK_CCIC0 20 +#define PXA1908_CLK_SDH0 21 +#define PXA1908_CLK_SDH1 22 +#define PXA1908_CLK_SDH2 56 +#define PXA1908_CLK_USB 23 +#define PXA1908_CLK_NF 24 +#define PXA1908_CLK_CORE_DEBUG 36 +#define PXA1908_CLK_VPU 41 +#define PXA1908_CLK_GC 81 +#define PXA1908_CLK_GC2D 61 +#define PXA1908_CLK_TRACE 66 +#define PXA1908_CLK_DVC_DFC_DEBUG 81 +#define PXA1908_APMU_NR_CLKS 96 + +#endif --=20 2.41.0