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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id y18-20020a5d6212000000b003143c6e09ccsm2266885wru.16.2023.07.27.07.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 07:27:15 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v4 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Date: Thu, 27 Jul 2023 16:14:26 +0200 Message-Id: <20230727141428.962286-9-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727141428.962286-1-alexghiti@rivosinc.com> References: <20230727141428.962286-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv now uses this sysctl so document its usage for this architecture. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- Documentation/admin-guide/sysctl/kernel.rst | 27 ++++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/ad= min-guide/sysctl/kernel.rst index 3800fab1619b..8019103aac10 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -941,16 +941,35 @@ enabled, otherwise writing to this file will return `= `-EBUSY``. The default value is 8. =20 =20 -perf_user_access (arm64 only) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +perf_user_access (arm64 and riscv only) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Controls user space access for reading perf event counters. =20 -Controls user space access for reading perf event counters. When set to 1, -user space can read performance monitor counter registers directly. +arm64 +=3D=3D=3D=3D=3D =20 The default value is 0 (access disabled). =20 +When set to 1, user space can read performance monitor counter registers +directly. + See Documentation/arch/arm64/perf.rst for more information. =20 +riscv +=3D=3D=3D=3D=3D + +When set to 0, user space access is disabled. + +The default value is 1, user space can read performance monitor counter +registers through perf, any direct access without perf intervention will t= rigger +an illegal instruction. + +When set to 2, which enables legacy mode (user space has direct access to = cycle +and insret CSRs only). Note that this legacy value is deprecated and will = be +removed once all user space applications are fixed. + +Note that the time CSR is always directly accessible to all modes. =20 pid_max =3D=3D=3D=3D=3D=3D=3D --=20 2.39.2