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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id q10-20020a1cf30a000000b003fbb618f7adsm1985627wmq.15.2023.07.27.07.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 07:23:19 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti , Atish Patra Subject: [PATCH v4 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Date: Thu, 27 Jul 2023 16:14:24 +0200 Message-Id: <20230727141428.962286-7-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727141428.962286-1-alexghiti@rivosinc.com> References: <20230727141428.962286-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the needed callbacks in the legacy driver so that we can directly access the counters through perf in userspace. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Atish Patra --- drivers/perf/riscv_pmu_legacy.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legac= y.c index 6a000abc28bb..79fdd667922e 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -71,6 +71,29 @@ static void pmu_legacy_ctr_start(struct perf_event *even= t, u64 ival) local64_set(&hwc->prev_count, initial_val); } =20 +static uint8_t pmu_legacy_csr_index(struct perf_event *event) +{ + return event->hw.idx; +} + +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_st= ruct *mm) +{ + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags |=3D PERF_EVENT_FLAG_USER_READ_CNT; +} + +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_= struct *mm) +{ + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags &=3D ~PERF_EVENT_FLAG_USER_READ_CNT; +} + /* * This is just a simple implementation to allow legacy implementations * compatible with new RISC-V PMU driver framework. @@ -91,6 +114,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) pmu->ctr_get_width =3D NULL; pmu->ctr_clear_idx =3D NULL; pmu->ctr_read =3D pmu_legacy_read_ctr; + pmu->event_mapped =3D pmu_legacy_event_mapped; + pmu->event_unmapped =3D pmu_legacy_event_unmapped; + pmu->csr_index =3D pmu_legacy_csr_index; =20 perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); } --=20 2.39.2