From nobody Mon Feb 9 17:58:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 562ADC001E0 for ; Thu, 27 Jul 2023 05:37:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjG0Fhu (ORCPT ); Thu, 27 Jul 2023 01:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232149AbjG0Fh0 (ORCPT ); Thu, 27 Jul 2023 01:37:26 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EC5E3582 for ; Wed, 26 Jul 2023 22:36:33 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b89d47ffb6so3422455ad.2 for ; Wed, 26 Jul 2023 22:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1690436131; x=1691040931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2eV7FwAQnhqmKgtMd0G6R4TLPgqzhAKhV6ZHHlFmK5M=; b=mra48eD2kN04BmlLuyAEvoEKjENVGmX08ZtHeBWV3TrnVT8w9cDYeNjDK+3LTUo9pg BMHCmE8isRPu0hr1Br50C0+6Dv3T1FQvw1R3Q8iGjbu3mc/1+ctEz37Hto6vI34nn3sd VsXpIHD3auMSYQzDlH6e7Adai3jRYKt3dzxNDWJiXRZirk2k2a8qfbAkGGu/j3PTbjaV RQlKgl8oI8g/eOIUdKJN6x+RB9Xw6gDIQIMDr9WnyydaJv2Kbu3CHdWPztkN7nX+ojDg OKx8pcW2FkGy6WlJPOOYqbUG26xl+6B1LY9oqVX0mutOICzTvJ0lyzsyLfOxgT58bqc6 vf1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690436131; x=1691040931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2eV7FwAQnhqmKgtMd0G6R4TLPgqzhAKhV6ZHHlFmK5M=; b=VFb0OBwfpE0HE83EWgCcB8FnQYdqTRN+sKN1ZsBoxr8cnEifDYK19kCidpmyI2qYMf SwzM9py6ZovIA+4Qn9Hm7B/Zchd5qBTkPlLJ1YJYVsykQ2mRABIahpmhOEE0NXa8NQl4 IPF0GQ3C0ZMyBlViZECuhVjZVw9CkTs6IKcjIqWjFLPcrRocdk32dv3uz8GnzXa2GS5D nQaSOYWKDpiASP8Kmq+/wX6j1cTCzQqROndQhSbHPTgvD1swtUXhZ702crkJJi74SbKr nTnoTPzPHxDfJTj84WgQhgEK0uw6I76KXwQ3fU8j8966SzplZtio5RVF8mdPH175JQrt XA/Q== X-Gm-Message-State: ABy/qLbMEIEO6h6ne1CQOp+I0zF4bwp/FhMuzwD2RwJRG8ERu129H5fw Vw+4BxMZ0pxTicNbHIUT0tNJxw== X-Google-Smtp-Source: APBJJlHvImL9nMGYwJO3XtrJzHDpD8HPaM0PRBf1WB8LD5lptPCb27jBcnAi8tB4UrHR6TMuogusIA== X-Received: by 2002:a17:903:11d1:b0:1bb:7b0a:374 with SMTP id q17-20020a17090311d100b001bb7b0a0374mr4165915plh.4.1690436131299; Wed, 26 Jul 2023 22:35:31 -0700 (PDT) Received: from localhost.localdomain ([82.78.167.79]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c11500b001bb889530adsm319059pli.217.2023.07.26.22.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 22:35:31 -0700 (PDT) From: Claudiu Beznea To: mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, mripard@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, varshini.rajendran@microchip.com, Claudiu Beznea Subject: [PATCH 25/42] clk: at91: at91sam9rl: switch to parent_hw Date: Thu, 27 Jul 2023 08:31:39 +0300 Message-Id: <20230727053156.13587-26-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727053156.13587-1-claudiu.beznea@tuxon.dev> References: <20230727053156.13587-1-claudiu.beznea@tuxon.dev> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch AT91SAM9RL clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/at91sam9rl.c | 70 +++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 0e8657aac491..29f24a5b1fef 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include #include @@ -28,13 +29,13 @@ static const struct clk_pll_characteristics sam9rl_plla= _characteristics =3D { .out =3D sam9rl_plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; } at91sam9rl_systemck[] =3D { - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct { @@ -67,23 +68,25 @@ static const struct { =20 static void __init at91sam9rl_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + struct clk_hw *parent_hws[5], *hw, *slow_clk_hw, *main_xtal_hw; + const char *main_xtal_name =3D "main_xtal"; struct pmc_data *at91sam9rl_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; + struct clk *clk; int i; =20 - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) + clk =3D of_clk_get_by_name(np, "slow_clk"); + if (IS_ERR(clk)) return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) + slow_clk_hw =3D __clk_get_hw(clk); + if (!slow_clk_hw) + return; + clk =3D of_clk_get_by_name(np, main_xtal_name); + if (IS_ERR(clk)) + return; + main_xtal_hw =3D __clk_get_hw(clk); + if (!main_xtal_hw) return; - mainxtal_name =3D of_clk_get_parent_name(np, i); =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -95,13 +98,13 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) if (!at91sam9rl_pmc) return; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NUL= L); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, main_xtal_hw= ); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, at91sam9rl_pmc->chws= [PMC_MAIN], 0, &at91rm9200_pll_layout, &sam9rl_plla_characteristics); if (IS_ERR(hw)) @@ -109,18 +112,18 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, at91sam9rl_pm= c->chws[PMC_MAIN]); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; + parent_hws[0] =3D slow_clk_hw; + parent_hws[1] =3D at91sam9rl_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D at91sam9rl_pmc->chws[PMC_PLLACK]; + parent_hws[3] =3D at91sam9rl_pmc->chws[PMC_UTMI]; hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_hws, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock); @@ -128,7 +131,7 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, hw, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); @@ -137,18 +140,18 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_hws[0] =3D slow_clk_hw; + parent_hws[1] =3D at91sam9rl_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D at91sam9rl_pmc->chws[PMC_PLLACK]; + parent_hws[3] =3D at91sam9rl_pmc->chws[PMC_UTMI]; + parent_hws[4] =3D at91sam9rl_pmc->chws[PMC_MCK]; for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_hws, 5, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -157,9 +160,12 @@ static void __init at91sam9rl_pmc_setup(struct device_= node *np) at91sam9rl_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9rl_systemck[0].parent_hw =3D at91sam9rl_pmc->pchws[0]; + at91sam9rl_systemck[1].parent_hw =3D at91sam9rl_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) { hw =3D at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, - at91sam9rl_systemck[i].p, NULL, + NULL, at91sam9rl_systemck[i].parent_hw, at91sam9rl_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -170,7 +176,7 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { hw =3D at91_clk_register_peripheral(regmap, at91sam9rl_periphck[i].n, - "masterck_div", NULL, + NULL, at91sam9rl_pmc->chws[PMC_MCK], at91sam9rl_periphck[i].id); if (IS_ERR(hw)) goto err_free; --=20 2.39.2