From nobody Mon Feb 9 17:58:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEF86C001DC for ; Thu, 27 Jul 2023 05:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231931AbjG0FfQ (ORCPT ); Thu, 27 Jul 2023 01:35:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231911AbjG0Feq (ORCPT ); Thu, 27 Jul 2023 01:34:46 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 611472D7D for ; Wed, 26 Jul 2023 22:34:21 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-563f752774fso285577a12.1 for ; Wed, 26 Jul 2023 22:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1690436058; x=1691040858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vv/BMVL/ZNeEbINcL/4raUcc3c4bebGIY3s5gcWMzMg=; b=AwhaRTb2XGZ8++zthKDFi0GoOgt4+AVSjoTKSwiALiQQfTPGrPlFN+zCC8OWvcLTbq MfvVbI0dWwjGzIUIpdfqUWOoDD7RfOuW1jr4X0z1bxyzLoZp+QhMiemlaWzsQ92tzTDl HWr1XP4mnBkJMuq8q5Mdow078dYC7uM8hw4ZEqpNUfi17JkcwscH3UuKakFdKk9soN45 uowuT5dCIe0i391ceDEtUOH4lCXXGgwceVzTOCS31daBC+Mfz8N42/z8HsQ8hh9RMKu3 D/EsXHz2kOh9f0k48Wi93ky423/BsO7uWgWKY/S76mc+QuPCTTwelVeweANl3HkRimjS /c6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690436058; x=1691040858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vv/BMVL/ZNeEbINcL/4raUcc3c4bebGIY3s5gcWMzMg=; b=br8vjz5XJecjYjFCTZEQZqtJwIH9xxguOBLJ7gFLq/ZJqoun2CPgYcM25ynnbW3SIA 9loblRjtP7ACbU/t321iGunbHiautiCaZzUD0jpfVLbXrYq3F+C9Yqb++0y3TnSOPPjB mv6WEQjE8kgM+DM55+BaCuUnbmEHtXx18lrED1JqMOS88czLmSVUGZCDNSwwnUcvxUA3 RBIbReEbJcnUrayYWT3C4imDTW1yVI7KdyD8YyqGOJQFvx0ir3mYimHpLF6++EktBvaJ 33AbcHucAKdq6MWMExty+YDGP0cGtb54bODxB83EnAqNZos/J/wQVNoD5ya00iStOS4l VCKw== X-Gm-Message-State: ABy/qLboc/OIaJZDzAX/p58ZVjq3zzdGuu9IEaMQQAsHVTvqqx4umtav tJf4cCrooHWuc5TLXaJzuMrWlw== X-Google-Smtp-Source: APBJJlELQG6oURUodMw1YgwQCG0dIqzVNWhe4qROJGNFhczx0pxHNp2MdbJMh+cQ5ErPIWttcG8Dug== X-Received: by 2002:a17:902:8210:b0:1b8:9552:2249 with SMTP id x16-20020a170902821000b001b895522249mr3216329pln.43.1690436058098; Wed, 26 Jul 2023 22:34:18 -0700 (PDT) Received: from localhost.localdomain ([82.78.167.79]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c11500b001bb889530adsm319059pli.217.2023.07.26.22.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 22:34:17 -0700 (PDT) From: Claudiu Beznea To: mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, mripard@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, varshini.rajendran@microchip.com, Claudiu Beznea Subject: [PATCH 15/42] clk: at91: at91sam9x5: switch to parent_hw and parent_data Date: Thu, 27 Jul 2023 08:31:29 +0300 Message-Id: <20230727053156.13587-16-claudiu.beznea@tuxon.dev> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727053156.13587-1-claudiu.beznea@tuxon.dev> References: <20230727053156.13587-1-claudiu.beznea@tuxon.dev> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch AT91SAM9X5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/at91sam9x5.c | 123 +++++++++++++++++++--------------- 1 file changed, 68 insertions(+), 55 deletions(-) diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 13331e015dd7..8b2747091b03 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include #include @@ -38,9 +39,9 @@ static const struct clk_pll_characteristics plla_characte= ristics =3D { .out =3D plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9x5_systemck[] =3D { @@ -48,12 +49,12 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct clk_pcr_layout at91sam9x5_pcr_layout =3D { @@ -133,25 +134,29 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, const struct pck *extra_pcks, bool has_lcdck) { + struct clk_hw *slow_clk_hw, *main_xtal_hw, *main_rc_hw, *main_osc_hw; + struct clk_hw *parent_hws[6], *smdck_hw, *usbck_hw, *hw; + static struct clk_parent_data parent_data; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + const char *main_xtal_name =3D "main_xtal"; struct pmc_data *at91sam9x5_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; + struct clk *clk; int i; bool bypass; =20 - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) + clk =3D of_clk_get_by_name(np, "slow_clk"); + if (IS_ERR(clk)) return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) + slow_clk_hw =3D __clk_get_hw(clk); + if (!slow_clk_hw) + return; + clk =3D of_clk_get_by_name(np, main_xtal_name); + if (IS_ERR(clk)) + return; + main_xtal_hw =3D __clk_get_hw(clk); + if (!main_xtal_hw) return; - mainxtal_name =3D of_clk_get_parent_name(np, i); =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -162,56 +167,57 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, if (!at91sam9x5_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + parent_data.name =3D main_xtal_name; + parent_data.fw_name =3D main_xtal_name; + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &par= ent_data, + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_hws[0] =3D main_rc_hw; + parent_hws[1] =3D main_osc_hw; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, at91sam9x5_pmc->chws= [PMC_MAIN], 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, hw); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, at91sam9x5_pm= c->chws[PMC_MAIN]); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_hws[0] =3D slow_clk_hw; + parent_hws[1] =3D at91sam9x5_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D at91sam9x5_pmc->chws[PMC_PLLACK]; + parent_hws[3] =3D at91sam9x5_pmc->chws[PMC_UTMI]; hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_hws, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, hw, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -220,28 +226,28 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, =20 at91sam9x5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_hws[0] =3D at91sam9x5_pmc->chws[PMC_PLLACK]; + parent_hws[1] =3D at91sam9x5_pmc->chws[PMC_UTMI]; + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_hw= s, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); - if (IS_ERR(hw)) + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_h= ws, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_hws[0] =3D slow_clk_hw; + parent_hws[1] =3D at91sam9x5_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D at91sam9x5_pmc->chws[PMC_PLLACK]; + parent_hws[3] =3D at91sam9x5_pmc->chws[PMC_UTMI]; + parent_hws[4] =3D at91sam9x5_pmc->chws[PMC_MCK]; for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_hws, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -250,9 +256,16 @@ static void __init at91sam9x5_pmc_setup(struct device_= node *np, at91sam9x5_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9x5_systemck[0].parent_hw =3D at91sam9x5_pmc->chws[PMC_MCK]; + at91sam9x5_systemck[1].parent_hw =3D smdck_hw; + at91sam9x5_systemck[2].parent_hw =3D usbck_hw; + at91sam9x5_systemck[3].parent_hw =3D usbck_hw; + at91sam9x5_systemck[4].parent_hw =3D at91sam9x5_pmc->pchws[0]; + at91sam9x5_systemck[5].parent_hw =3D at91sam9x5_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) { hw =3D at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, - at91sam9x5_systemck[i].p, NULL, + NULL, at91sam9x5_systemck[i].parent_hw, at91sam9x5_systemck[i].id, at91sam9x5_systemck[i].flags); if (IS_ERR(hw)) @@ -262,8 +275,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, } =20 if (has_lcdck) { - hw =3D at91_clk_register_system(regmap, "lcdck", "masterck_div", - NULL, 3, 0); + hw =3D at91_clk_register_system(regmap, "lcdck", NULL, + at91sam9x5_pmc->chws[PMC_MCK], 3, 0); if (IS_ERR(hw)) goto err_free; =20 @@ -274,7 +287,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, - "masterck_div", NULL, + NULL, at91sam9x5_pmc->chws[PMC_MCK], at91sam9x5_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) @@ -287,7 +300,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, - "masterck_div", NULL, + NULL, at91sam9x5_pmc->chws[PMC_MCK], extra_pcks[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) --=20 2.39.2