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[75.172.111.252]) by smtp.gmail.com with ESMTPSA id f25-20020a633819000000b0055bf13811f5sm240782pga.15.2023.07.26.19.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 19:50:11 -0700 (PDT) From: Luke Nelson X-Google-Original-From: Luke Nelson To: bpf@vger.kernel.org Cc: Luke Nelson , kernel test robot , Xi Wang , Daniel Borkmann , Alexei Starovoitov , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next] riscv/bpf: Fix truncated immediate warning in rv_s_insn Date: Wed, 26 Jul 2023 19:49:31 -0700 Message-Id: <20230727024931.17156-1-luke.r.nels@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sparse warns that a cast in rv_s_insn truncates bits from the constant 0x7ff to 0xff. The warning originates from the use of a constant offset of -8 in a store instruction in bpf_jit_comp64.c: emit(rv_sd(RV_REG_SP, -8, RV_REG_RA), &ctx); rv_sd then calls rv_s_insn, with imm11_0 equal to (u16)(-8), or 0xfff8. Here's the current implementation of rv_s_insn: static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 op= code) { u8 imm11_5 =3D imm11_0 >> 5, imm4_0 =3D imm11_0 & 0x1f; return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 1= 2) | (imm4_0 << 7) | opcode; } imm11_0 is a signed 12-bit immediate offset of the store instruction. The instruction encoding requires splitting the immediate into bits 11:5 and bits 4:0. In this case, imm11_0 >> 5 =3D 0x7ff, which then gets truncated to 0xff when cast to u8, causing the warning from sparse. However, this is not actually an issue because the immediate offset is signed---truncating upper bits that are all set to 1 has no effect on the value of the immediate. There is another subtle quirk with this code, which is imm11_5 is supposed to be the upper 7 bits of the 12-bit signed immediate, but its type is u8 with no explicit mask to select out only the bottom 7 bits. This happens to be okay here because imm11_5 is the left-most field in the instruction and the "extra" bit will be shifted out when imm11_5 is shifted left by 25. This commit fixes the warning by changing the type of imm11_5 and imm4_0 to be u32 instead of u8, and adding an explicit mask to compute imm11_5 instead of relying on truncation + shifting. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307260704.dUElCrWU-lkp@int= el.com/ In-Reply-To: <202307260704.dUElCrWU-lkp@intel.com> Signed-off-by: Luke Nelson Cc: Xi Wang Cc: Daniel Borkmann Acked-by: Bj=C3=B6rn T=C3=B6pel Reviewed-by: Pu Lehui --- arch/riscv/net/bpf_jit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index 2717f5490428..e159c6e3ff43 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -238,7 +238,7 @@ static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 fun= ct3, u8 rd, u8 opcode) static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opc= ode) { - u8 imm11_5 =3D imm11_0 >> 5, imm4_0 =3D imm11_0 & 0x1f; + u32 imm11_5 =3D (imm11_0 >> 5) & 0x7f, imm4_0 =3D imm11_0 & 0x1f; return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | (imm4_0 << 7) | opcode; -- 2.34.1