From nobody Tue Sep 9 22:45:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E122C04A6A for ; Wed, 26 Jul 2023 16:46:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230184AbjGZQqm (ORCPT ); Wed, 26 Jul 2023 12:46:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231172AbjGZQqg (ORCPT ); Wed, 26 Jul 2023 12:46:36 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E882704 for ; Wed, 26 Jul 2023 09:46:31 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1b9ecf0cb4cso41055755ad.2 for ; Wed, 26 Jul 2023 09:46:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690389991; x=1690994791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9I72PoBRKXLvHktmcrje1n02ixRw/D4fAolrg/chvlw=; b=2Jz16VlHfoEFfZ3AFSLSXY8u2g8fiZbPZUwm9PJbLRY7gk6jqF0t0jiYlXi7TSGAYF 3zubxHuOcq7inKRub1IH2maTkPsOZAxyx6PORG91v3QJLBcTa/dZMQOYbMdbNUouInY2 7xzKDWuWhLszpWjh3LQHwMz6C55JKbegov2VqNbT1ZtA9nhipvVWBFdoo8sQqQIN350e D0wMU5CYHIqplbYqQ9tt0g/RjLzgREP1Ls4ss+Rt/p1Xz9F2SIvJNR5F90mAfc/fCnKK cIeKdrmuE9jvExtAHXgaqbGU9cdsmnL7Rerg9I1/qayP5aEnKEIwJ3CwtCTUbx2Qm+FI ugLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690389991; x=1690994791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9I72PoBRKXLvHktmcrje1n02ixRw/D4fAolrg/chvlw=; b=R27Iu4+NeAXcg3gkIBrRpsIbXnZ35GGEjVkge/Fh/G3nARD3T3pBNWdEHvxizQKN2B pkI0rNN46+tvTEoZ24gD8f1vq5xsKiTv/y1dliBJ5YbuCuF/uSmoEkLTM0KMveGbK8jn CpOCBYpM+CPIc8mSaE0Wi+G/7b6ssJWvZsv0d0dMRenYMWlG5hG4JO4u2GjRZ/3qGLZC Dza3bDpAazExHg+No3tFBOm74TdrOe/y1RKscLr0Be+d1J43kegshZDn/9m8EDXWDqpz 4S7w9dSVPCpA3SSDBU8UNX9jLdCiXYaqztcllZGn1Uv5GP/ipeTJUVQfB65H/0DY7zBq EkMg== X-Gm-Message-State: ABy/qLbbCl9ZfV8qNPftKixWbK5TSyX8dNJFK6Fi/xqq+3N6VvWrwN6f YRbCNkPtxsP3ixqhgWPUTdELig== X-Google-Smtp-Source: APBJJlGp1GY/W4RE/89gp/16eB2AGE/qHe+6+KWmHQWy/wMthtq4d82Q6nwr43YclX/zAw9dQWmddw== X-Received: by 2002:a17:902:d501:b0:1b6:9551:e297 with SMTP id b1-20020a170902d50100b001b69551e297mr2620057plg.44.1690389990886; Wed, 26 Jul 2023 09:46:30 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id h5-20020a170902f54500b001bb6c5ff4edsm11628870plf.173.2023.07.26.09.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:46:30 -0700 (PDT) From: Charlie Jenkins To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v7 1/4] RISC-V: mm: Restrict address space for sv39,sv48,sv57 Date: Wed, 26 Jul 2023 09:45:55 -0700 Message-ID: <20230726164620.717288-2-charlie@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726164620.717288-1-charlie@rivosinc.com> References: <20230726164620.717288-1-charlie@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make sv48 the default address space for mmap as some applications currently depend on this assumption. A hint address passed to mmap will cause the largest address space that fits entirely into the hint to be used. If the hint is less than or equal to 1<<38, an sv39 address will be used. An exception is that if the hint address is 0, then a sv48 address will be used. After an address space is completely full, the next smallest address space will be used. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/pgtable.h | 13 ++++++++- arch/riscv/include/asm/processor.h | 47 +++++++++++++++++++++++++----- 3 files changed, 53 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index c24280774caf..5d3368d5585c 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -49,7 +49,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * the loader. We need to make sure that it is out of the way of the prog= ram * that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) +#define ELF_ET_DYN_BASE ((DEFAULT_MAP_WINDOW / 3) * 2) =20 #ifdef CONFIG_64BIT #ifdef CONFIG_COMPAT diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 75970ee2bda2..530f6a171a2b 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -63,12 +63,23 @@ * position vmemmap directly below the VMALLOC region. */ #ifdef CONFIG_64BIT +#define VA_BITS_SV39 39 +#define VA_BITS_SV48 48 +#define VA_BITS_SV57 57 + +#define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) +#define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) +#define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) + #define VA_BITS (pgtable_l5_enabled ? \ - 57 : (pgtable_l4_enabled ? 48 : 39)) + VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) #else #define VA_BITS 32 #endif =20 +#define MMAP_VA_BITS ((VA_BITS >=3D VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) +#define MMAP_MIN_VA_BITS ((VA_BITS >=3D VA_BITS_SV39) ? VA_BITS_SV39 : VA_= BITS) + #define VMEMMAP_SHIFT \ (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index c950a8d9edef..050e27577419 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,20 +13,53 @@ =20 #include =20 -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) - -#define STACK_TOP TASK_SIZE #ifdef CONFIG_64BIT +#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) #define STACK_TOP_MAX TASK_SIZE_64 + +#define arch_get_mmap_end(addr, len, flags) \ +({ \ + unsigned long mmap_end; \ + if ((addr) =3D=3D 0) \ + mmap_end =3D DEFAULT_MAP_WINDOW; \ + else if ((addr) >=3D VA_USER_SV57) \ + mmap_end =3D STACK_TOP_MAX; \ + else if ((((addr) >=3D VA_USER_SV48)) && (VA_BITS >=3D VA_BITS_SV48)) \ + mmap_end =3D VA_USER_SV48; \ + else \ + mmap_end =3D VA_USER_SV39; \ + mmap_end; \ +}) + +#define arch_get_mmap_base(addr, base) \ +({ \ + unsigned long mmap_base; \ + unsigned long rnd_gap =3D (base) - DEFAULT_MAP_WINDOW; \ + if ((addr) =3D=3D 0) \ + mmap_base =3D (base); \ + else if (((addr) >=3D VA_USER_SV57) && (VA_BITS >=3D VA_BITS_SV57)) \ + mmap_base =3D VA_USER_SV57 + rnd_gap; \ + else if ((((addr) >=3D VA_USER_SV48)) && (VA_BITS >=3D VA_BITS_SV48)) \ + mmap_base =3D VA_USER_SV48 + rnd_gap; \ + else \ + mmap_base =3D VA_USER_SV39 + rnd_gap; \ + mmap_base; \ +}) + #else +#define DEFAULT_MAP_WINDOW TASK_SIZE #define STACK_TOP_MAX TASK_SIZE #endif #define STACK_ALIGN 16 =20 +#define STACK_TOP DEFAULT_MAP_WINDOW + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE PAGE_ALIGN(MMAP_MIN_VA_BITS / 3) + #ifndef __ASSEMBLY__ =20 struct task_struct; --=20 2.41.0