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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:08 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 04/11] mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset Date: Wed, 26 Jul 2023 10:52:50 +0300 Message-Id: <20230726075257.12985-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3009; i=tudor.ambarus@linaro.org; h=from:subject; bh=mCXnzZObQc2zhfJufj3cA5z2xujPAjIEucaG9JmkqZU=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYDwwoqDn25kns6GQbu0V+TxM1w1CZcl4Rj xe+vM3yTYuJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6fVSB/0X+AC60NMt+0iVr9T0QiN63zOwAHa4aMnsmWYJfYuZXMlZjXotN+TvdgZV2x1/iRkEKz0 Z9OitjSmE1sl625kHEt9REkbAJSLlVPlGD9QYiOkcgzAhu6pECnXZmpQ3K7+tlvC8GUPMuKwGqj uNA/4iLiFJ8WxXy+BbTW9GU/ts8E5LM7ZuGYDRzRvMch669wzq/3lM0fKVvDWPK1EGPy3fYw4IU 5bUvLljF86BYpxhjmWFvPyvLFMxjXe4/oNjD4oizCummI26MAtv1ZxaKxj7KXP3rZZp0rXxgO2d gUNWRYOdwBBaymo8K2wg0pe7L7Dsj7nffpxf5g3wgDgepeVB X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano All the Infineon flashes that currently support octal DTR mode define the optional SCCR SFDP table, thus all retrieve vreg_offset. Switch all the available octal DTR Infineon flashes to use the volatile register offset to set the configuration registers. The goal is to have a single pair of methods for both single/multi-chip package devices. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 51eabddf2b16..94d98b5b0ff1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "core.h" @@ -37,8 +38,6 @@ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 -#define SPINOR_REG_CYPRESS_CFR5V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR5) #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) @@ -202,14 +201,18 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_= nor *nor, u64 addr) =20 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; + ret =3D cypress_nor_set_memlat(nor, addr); if (ret) return ret; =20 - ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); if (ret) return ret; =20 @@ -247,9 +250,11 @@ static int cypress_nor_set_single_spi_bits(struct spi_= nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_single_spi_bits(nor, addr); if (ret) return ret; =20 @@ -714,7 +719,15 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s28hx_t_late_init(struct spi_nor *nor) { - nor->params->set_octal_dtr =3D cypress_nor_set_octal_dtr; + struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + params->set_octal_dtr =3D cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); =20 return 0; --=20 2.34.1