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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:07 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 03/11] mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support Date: Wed, 26 Jul 2023 10:52:49 +0300 Message-Id: <20230726075257.12985-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3820; i=tudor.ambarus@linaro.org; h=from:subject; bh=xpyv1UNUOm+7WUBWb0Vl59R+HvbIVKf4klrF0ttDcrA=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYcL1Tyl84sNIYkyBfq2rFtCaH7yjWfYS7u dc1OqqEJMiJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6QMLCACDjtW+TDGGiTS92Jsl6Uk3LbCGtuLZY2zAlHX4QCj3TU4Qt6wzONyOAiZ13yx3a0BiKX7 bgPVNwx70THRRo9pXuw/jM30cQKvhv7fDqDCJt7YrVCW/5deEjgZbw/rAHognAO5JWebQbnz1/y ZNmKBYivfOSoi8ABV84JjXxQQ3XgQlilQLim+XpAw5NNJHoDxgylv19QSaKrddaTak0BOuOd8x9 KVzhxIvba2pr7FPhqUeCN18YfDMkZ58r5pbVjo15JzcrfaDe5Kj1qXt9jqoXg0JgKAGuCGA0v9S qPPsLiTAWlOsSVM3AVgqzxmtDwDnmwT3TXXkUCNcpk/EQuPd X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon's multi-chip package (MCP) devices require the octal DTR configuration to be set for each die. Split common code in dedicated methods to ease the octal DDR MCP support addition. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6460d2247bdf..51eabddf2b16 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_no= r *nor) return 1; } =20 -static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; @@ -164,8 +164,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) u8 addr_mode_nbytes =3D nor->params->addr_mode_nbytes; =20 op =3D (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 0, buf); + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); =20 ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) @@ -176,8 +175,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) *buf |=3D FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); =20 ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) @@ -185,13 +183,33 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) =20 nor->read_dummy =3D 24; =20 + return 0; +} + +static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + /* Set the octal and DTR enable bits. */ buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, + addr, 1, buf); =20 - ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); +} + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + if (ret) + return ret; + + ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 @@ -209,11 +227,10 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) return 0; } =20 -static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; - int ret; =20 /* * The register is 1-byte wide, but 1-byte transactions are not allowed @@ -223,9 +240,16 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *n= or) buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] =3D 0; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 2, buf); - ret =3D spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); + return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); +} + +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 --=20 2.34.1