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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:17 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v4 10/11] mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable() Date: Wed, 26 Jul 2023 10:52:56 +0300 Message-Id: <20230726075257.12985-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2125; i=tudor.ambarus@linaro.org; h=from:subject; bh=QdB1CqYeo+E0vRmCT5AKj+737qFOif1g4DSnqlL1Z6o=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYWzzJw8YDhGmjAHNiDSE8hUDVOK83EN137 yf6F7ibY/aJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6TaBB/9OD4NAVj0Ze+yCwu+WLSTy9opP6fNQcZ6JV8WDN5h11aIzOo2vW3Lt1VPTKpL8Fxpr/7U 7syEMtg2iTm3aBOjM/4B73+vwAxFd4xon9PDcZ2f8YOOgiuOhKeyhA+r4JK/qFmEE1usbf6ssof wtXJast8GMQqjx8rD6jO0KDx6CZeG5vnw4XvpO+SWb361znYdbRxFtmWFJ5jCMaawhh12k4z9au Bw6QnJz1PO5u05Jzwi0sD4gBX5dGBFm9/cWWspuSFT8hpiq3B+2gkZ+wt34v7dcUpPnsH8LHzmG ixoMeoAoLpMMtAlETLwlXqiO1JV6JhWpwv6PqPdqFzlLkjXV X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All s25hx_t flashes have single or multi chip flavors and already use n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t to always use vreg_offset for the quad_enable() method, so that we use the same code base for both single and multi chip package flashes. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 30a3ffbfa381..6abef5b515a1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -24,8 +24,6 @@ #define SPINOR_REG_CYPRESS_STR1V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) #define SPINOR_REG_CYPRESS_CFR1 0x2 -#define SPINOR_REG_CYPRESS_CFR1V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR1) #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ @@ -348,10 +346,6 @@ static int cypress_nor_quad_enable_volatile(struct spi= _nor *nor) u8 i; int ret; =20 - if (!params->n_dice) - return cypress_nor_quad_enable_volatile_reg(nor, - SPINOR_REG_CYPRESS_CFR1V); - for (i =3D 0; i < params->n_dice; i++) { addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; ret =3D cypress_nor_quad_enable_volatile_reg(nor, addr); @@ -657,15 +651,17 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; - + params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 - /* Replace ready() with multi die version */ - if (params->n_dice) - params->ready =3D cypress_nor_sr_ready_and_clear; - return 0; } =20 --=20 2.34.1