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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:04 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 01/11] mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR Date: Wed, 26 Jul 2023 10:52:47 +0300 Message-Id: <20230726075257.12985-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15492; i=tudor.ambarus@linaro.org; h=from:subject; bh=abt/KuEBLk/2uHPj4mik4XS7fR2pRwv3tmtN9KYUxeY=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDXvmmbTvWhjt87EjyA0hTvCArKszPFUvy7G 1BYCiNskOSJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ1wAKCRBLVU9HpY0U 6e3aCAC9X6JOO4LA2xqfWzRDqXDBas+VpB++82rBDoG0Hp+kbCZ7Oie7W/5unTsnRu0wFPL2lqd xjr7kNe+aWKylz7EW6bluVvMi9YJCb4h34EgBH56TiBQIcTNuRzqw4xr9X/l8C+K3CpS920Nk6y yC5ptkt24vIQ2MJi4dbZ6ZfNYwaJSuM0YViPXQWBVxtdx1WCZQTu66cCSV84CGblCyR5lB5tzjB upNT3f1+DjC6W4+FJXoVcrI5KT1RwoYbFEAaFNDfzdOSsNEj+6F1n2miBcdqEU8nlEkjICpdvMx 5MzGgRYIFUqjRUx46Cy/wP/leiXal9Tay3gn1kfkB9Jm6e30 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/atmel.c | 8 +++- drivers/mtd/spi-nor/core.c | 23 +++++++---- drivers/mtd/spi-nor/core.h | 4 +- drivers/mtd/spi-nor/issi.c | 4 +- drivers/mtd/spi-nor/macronix.c | 4 +- drivers/mtd/spi-nor/micron-st.c | 4 +- drivers/mtd/spi-nor/spansion.c | 72 ++++++++++++++++++++++++++------- drivers/mtd/spi-nor/sst.c | 8 +++- drivers/mtd/spi-nor/winbond.c | 4 +- drivers/mtd/spi-nor/xilinx.c | 4 +- 10 files changed, 103 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 656dd80a0be7..58968c1e7d2f 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -48,9 +48,11 @@ static const struct spi_nor_locking_ops at25fs_nor_locki= ng_ops =3D { .is_locked =3D at25fs_nor_is_locked, }; =20 -static void at25fs_nor_late_init(struct spi_nor *nor) +static int at25fs_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &at25fs_nor_locking_ops; + + return 0; } =20 static const struct spi_nor_fixups at25fs_nor_fixups =3D { @@ -149,9 +151,11 @@ static const struct spi_nor_locking_ops atmel_nor_glob= al_protection_ops =3D { .is_locked =3D atmel_nor_is_global_protected, }; =20 -static void atmel_nor_global_protection_late_init(struct spi_nor *nor) +static int atmel_nor_global_protection_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &atmel_nor_global_protection_ops; + + return 0; } =20 static const struct spi_nor_fixups atmel_nor_global_protection_fixups =3D { diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 273258f7e77f..614960c7d22c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2900,16 +2900,23 @@ static void spi_nor_init_fixup_flags(struct spi_nor= *nor) * SFDP standard, or where SFDP tables are not defined at all. * Will replace the spi_nor_manufacturer_init_params() method. */ -static void spi_nor_late_init_params(struct spi_nor *nor) +static int spi_nor_late_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; + int ret; =20 if (nor->manufacturer && nor->manufacturer->fixups && - nor->manufacturer->fixups->late_init) - nor->manufacturer->fixups->late_init(nor); + nor->manufacturer->fixups->late_init) { + ret =3D nor->manufacturer->fixups->late_init(nor); + if (ret) + return ret; + } =20 - if (nor->info->fixups && nor->info->fixups->late_init) - nor->info->fixups->late_init(nor); + if (nor->info->fixups && nor->info->fixups->late_init) { + ret =3D nor->info->fixups->late_init(nor); + if (ret) + return ret; + } =20 /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) @@ -2927,6 +2934,8 @@ static void spi_nor_late_init_params(struct spi_nor *= nor) =20 if (nor->info->n_banks > 1) params->bank_size =3D div64_u64(params->size, nor->info->n_banks); + + return 0; } =20 /** @@ -3085,9 +3094,7 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } =20 - spi_nor_late_init_params(nor); - - return 0; + return spi_nor_late_init_params(nor); } =20 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f2fc2cf78e55..9217379b9cfe 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -378,6 +378,7 @@ struct spi_nor_otp { * than reading the status register to indicate they * are ready for a new command * @locking_ops: SPI NOR locking methods. + * @priv: flash's private data. */ struct spi_nor_flash_parameter { u64 bank_size; @@ -406,6 +407,7 @@ struct spi_nor_flash_parameter { int (*ready)(struct spi_nor *nor); =20 const struct spi_nor_locking_ops *locking_ops; + void *priv; }; =20 /** @@ -432,7 +434,7 @@ struct spi_nor_fixups { const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); int (*post_sfdp)(struct spi_nor *nor); - void (*late_init)(struct spi_nor *nor); + int (*late_init)(struct spi_nor *nor); }; =20 /** diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 400e2b42f45a..accdf7aa2bfd 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,7 +29,7 @@ static const struct spi_nor_fixups is25lp256_fixups =3D { .post_bfpt =3D is25lp256_post_bfpt_fixups, }; =20 -static void pm25lv_nor_late_init(struct spi_nor *nor) +static int pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map =3D &nor->params->erase_map; int i; @@ -38,6 +38,8 @@ static void pm25lv_nor_late_init(struct spi_nor *nor) for (i =3D 0; i < SNOR_ERASE_TYPE_MAX; i++) if (map->erase_type[i].size =3D=3D 4096) map->erase_type[i].opcode =3D SPINOR_OP_BE_4K_PMC; + + return 0; } =20 static const struct spi_nor_fixups pm25lv_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 04888258e891..eb149e517c1f 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -110,10 +110,12 @@ static void macronix_nor_default_init(struct spi_nor = *nor) nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; } =20 -static void macronix_nor_late_init(struct spi_nor *nor) +static int macronix_nor_late_init(struct spi_nor *nor) { if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; + + return 0; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index f79e71d99124..6ad080c52ab5 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -429,7 +429,7 @@ static void micron_st_nor_default_init(struct spi_nor *= nor) nor->params->quad_enable =3D NULL; } =20 -static void micron_st_nor_late_init(struct spi_nor *nor) +static int micron_st_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -438,6 +438,8 @@ static void micron_st_nor_late_init(struct spi_nor *nor) =20 if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex= 4b; + + return 0; } =20 static const struct spi_nor_fixups micron_st_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 314667d4b8a8..6b2532ed053c 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,14 +4,17 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ =20 +#include #include =20 #include "core.h" =20 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ #define USE_CLSR BIT(0) +#define USE_CLPEF BIT(1) =20 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -57,22 +60,32 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(1, buf, 0)) =20 -#define SPANSION_CLSR_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ +#define SPANSION_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 +/** + * struct spansion_nor_params - Spansion private parameters. + * @clsr: Clear Status Register or Clear Program and Erase Failure Flag + * opcode. + */ +struct spansion_nor_params { + u8 clsr; +}; + /** * spansion_nor_clear_sr() - Clear the Status Register. * @nor: pointer to 'struct spi_nor'. */ static void spansion_nor_clear_sr(struct spi_nor *nor) { + const struct spansion_nor_params *priv_params =3D nor->params->priv; int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPANSION_CLSR_OP; + struct spi_mem_op op =3D SPANSION_OP(priv_params->clsr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -528,9 +541,11 @@ static int s25fs256t_post_sfdp_fixup(struct spi_nor *n= or) return 0; } =20 -static void s25fs256t_late_init(struct spi_nor *nor) +static int s25fs256t_late_init(struct spi_nor *nor) { cypress_nor_ecc_init(nor); + + return 0; } =20 static struct spi_nor_fixups s25fs256t_fixups =3D { @@ -586,7 +601,7 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) return cypress_nor_get_page_size(nor); } =20 -static void s25hx_t_late_init(struct spi_nor *nor) +static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -598,6 +613,8 @@ static void s25hx_t_late_init(struct spi_nor *nor) /* Replace ready() with multi die version */ if (params->n_dice) params->ready =3D cypress_nor_sr_ready_and_clear; + + return 0; } =20 static struct spi_nor_fixups s25hx_t_fixups =3D { @@ -659,10 +676,12 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *no= r, return cypress_nor_set_addr_mode_nbytes(nor); } =20 -static void s28hx_t_late_init(struct spi_nor *nor) +static int s28hx_t_late_init(struct spi_nor *nor) { nor->params->set_octal_dtr =3D cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); + + return 0; } =20 static const struct spi_nor_fixups s28hx_t_fixups =3D { @@ -786,47 +805,54 @@ static const struct flash_info spansion_nor_parts[] = =3D { FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25fs256t_fixups }, { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, }; @@ -870,17 +896,35 @@ static int spansion_nor_sr_ready_and_clear(struct spi= _nor *nor) return !(nor->bouncebuf[0] & SR_WIP); } =20 -static void spansion_nor_late_init(struct spi_nor *nor) +static int spansion_nor_late_init(struct spi_nor *nor) { - if (nor->params->size > SZ_16M) { + struct spi_nor_flash_parameter *params =3D nor->params; + struct spansion_nor_params *priv_params; + u8 mfr_flags =3D nor->info->mfr_flags; + + if (params->size > SZ_16M) { nor->flags |=3D SNOR_F_4B_OPCODES; /* No small sector erase for 4-byte command set */ nor->erase_opcode =3D SPINOR_OP_SE; nor->mtd.erasesize =3D nor->info->sector_size; } =20 - if (nor->info->mfr_flags & USE_CLSR) - nor->params->ready =3D spansion_nor_sr_ready_and_clear; + if (mfr_flags & (USE_CLSR | USE_CLPEF)) { + priv_params =3D devm_kmalloc(nor->dev, sizeof(*priv_params), + GFP_KERNEL); + if (!priv_params) + return -ENOMEM; + + if (mfr_flags & USE_CLSR) + priv_params->clsr =3D SPINOR_OP_CLSR; + else if (mfr_flags & USE_CLPEF) + priv_params->clsr =3D SPINOR_OP_CLPEF; + + params->priv =3D priv_params; + params->ready =3D spansion_nor_sr_ready_and_clear; + } + + return 0; } =20 static const struct spi_nor_fixups spansion_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 688eb20c763e..09fdc7023e09 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -49,9 +49,11 @@ static const struct spi_nor_locking_ops sst26vf_nor_lock= ing_ops =3D { .is_locked =3D sst26vf_nor_is_locked, }; =20 -static void sst26vf_nor_late_init(struct spi_nor *nor) +static int sst26vf_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &sst26vf_nor_locking_ops; + + return 0; } =20 static const struct spi_nor_fixups sst26vf_nor_fixups =3D { @@ -203,10 +205,12 @@ static int sst_nor_write(struct mtd_info *mtd, loff_t= to, size_t len, return ret; } =20 -static void sst_nor_late_init(struct spi_nor *nor) +static int sst_nor_late_init(struct spi_nor *nor) { if (nor->info->mfr_flags & SST_WRITE) nor->mtd._write =3D sst_nor_write; + + return 0; } =20 static const struct spi_nor_fixups sst_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 63ba8e3a96f5..cd99c9a1c568 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -217,7 +217,7 @@ static const struct spi_nor_otp_ops winbond_nor_otp_ops= =3D { .is_locked =3D spi_nor_otp_is_locked_sr2, }; =20 -static void winbond_nor_late_init(struct spi_nor *nor) +static int winbond_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -233,6 +233,8 @@ static void winbond_nor_late_init(struct spi_nor *nor) * from BFPT, if any. */ params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; + + return 0; } =20 static const struct spi_nor_fixups winbond_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 7175de8aa336..00d53eae5ee8 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -155,10 +155,12 @@ static int xilinx_nor_setup(struct spi_nor *nor, return 0; } =20 -static void xilinx_nor_late_init(struct spi_nor *nor) +static int xilinx_nor_late_init(struct spi_nor *nor) { nor->params->setup =3D xilinx_nor_setup; nor->params->ready =3D xilinx_nor_sr_ready; + + return 0; } =20 static const struct spi_nor_fixups xilinx_nor_fixups =3D { --=20 2.34.1 From nobody Tue Sep 9 01:01:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA351C001DC for ; Wed, 26 Jul 2023 08:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233062AbjGZIB7 (ORCPT ); Wed, 26 Jul 2023 04:01:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232587AbjGZIBO (ORCPT ); Wed, 26 Jul 2023 04:01:14 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F933A84 for ; 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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:05 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano , stable@vger.kernel.org Subject: [PATCH v4 02/11] mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT Date: Wed, 26 Jul 2023 10:52:48 +0300 Message-Id: <20230726075257.12985-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1944; i=tudor.ambarus@linaro.org; h=from:subject; bh=kVZ7aQId7ERSbIGrhSxOKuGFZinAOtskWkM0179Q9K8=; b=owGbwMvMwMXoHervvrRX5CXjabUkhpQDF657tM2J2u3zateCRqbvR/N9o4sVnHQOfA0s2Pm+w 138zsSYTkZjFgZGLgZZMUUWWSetU+f5TuTGyf67DzOIlQlkCgMXpwBMpPAA+/+ckoQ31xSlePsW SdUvdJtreiBl1928qPwPBxxn73n6JmVvsiZ3SsHGvSGWSS3XRNbw/C5V3bR338nN0x2mL/DLbEo RfcUm72IhOTfsM7+2B4Omq9j5P97d/X1OW8+WhJbJvdO69W+Z3ArWl+3Jbzb9XBzsV+EbrO2qYe Lxs1PkDYfB1BX+s+fGHZoSXNO3R6OrhV3sRtDvM7dvTjnuPtlBzTW58pF3y5r8NIu/rW1n57JKf eKq4p69vMAo8Fjrgcu6a46JcptVCooefnJYUF7w05Il5d0CniVBOS4fWjK7rY3Ewg/Wslkr5S91 7tzOwvNznbDed55S2+LfvzgvbFtluXPyvyqeD5tj/DgdAA== X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read, update, write back fashion. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Sempe= r flash") Signed-off-by: Takahiro Kuwano Cc: stable@vger.kernel.org --- drivers/mtd/spi-nor/spansion.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6b2532ed053c..6460d2247bdf 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ =20 +#include #include #include =20 @@ -28,6 +29,7 @@ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 @@ -161,8 +163,18 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *no= r) int ret; u8 addr_mode_nbytes =3D nor->params->addr_mode_nbytes; =20 + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, + SPINOR_REG_CYPRESS_CFR2V, 0, buf); + + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + /* Use 24 dummy cycles for memory array reads. */ - *buf =3D SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; + *buf &=3D ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; + *buf |=3D FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, + SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op =3D (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR2V, 1, buf); --=20 2.34.1 From nobody Tue Sep 9 01:01:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64C18C001DC for ; Wed, 26 Jul 2023 08:02:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233070AbjGZICB (ORCPT ); Wed, 26 Jul 2023 04:02:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbjGZIBO (ORCPT ); Wed, 26 Jul 2023 04:01:14 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D2A3A8F for ; Wed, 26 Jul 2023 00:53:09 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3fbd33a57ddso54977625e9.1 for ; Wed, 26 Jul 2023 00:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357987; x=1690962787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eOW1ZpE6/v2ajQK+LnlqMKJQMOzTE7yoF7vscLDu6Gs=; b=XjXRddzUgX6ZCB8WxKJ71CHiJz8AfBWByZoyYDJe/1RT9PyHRc/i+xMcMqseM5LHeg mQSD0D/DK8HwqZsoX7qtM6QrZgBEa7xrup7xaGl6u1u8o6ayJlqlv/9pAfLCgLDzMamj XZcHBsPswOlfxWwAFdXr7UplJkiifIYL+auN5D6AK/liqnc7KIh3u+mWcqQSK/LJFVpk M0Xpxyhq2+XD2jPEt8XTjRO8ysvj6v/dvgFTg7XR2K/+hH7vpNSL/FV64bHTY9Bb7jsa iTkm9kYkNKv7fC4Ww8iei4mSFKLjjd9OMuHj7ook6nfL5613f1VVdvXrZ17OWgl8GyPh TcYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357987; x=1690962787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eOW1ZpE6/v2ajQK+LnlqMKJQMOzTE7yoF7vscLDu6Gs=; b=eU1ZRPkyc5C5mnNTkd6616P+8X7gBMtqnbkXU0lHtSyEtuApu12RJSolWlQk60jMUK bwOkXU0Lhz7Tk9eUu1gPHkGkAKU9iveIx0aMB9FGexYFUr01etNw5DTSv0zcxkcjTtL0 nRJ/eAj9dZCAFhXMzbcfJr4bV1KlopxwGohzqmjD53WZJ2Vd81eiuRm3MVNDKtXKmW6X +3HnY7ipXZasmWMQZbIY8ahdMf9QGTRz54WdujsS3yfDhCXfAo+l2CZfkaU4uxoQ12K7 Ss2/mtZ68YLHj+IHQ3tQXwYZ6XU1uRq5r+1qmyX0zC7b4Ilp96p2BMaeV9XOJo1LjVMd kNGg== X-Gm-Message-State: ABy/qLbXJtDFKucUanI9rqjgMehQtktGm8h14MsKvbqY2yNPDJcPdXCs FDG05pepPgCnDqpkBElvw3lmQw== X-Google-Smtp-Source: APBJJlHM56jl+RXg0QnhlAvXgWKnfJquOVPifN3XCGThqumelXHC+MBthB7m2Q0oAw01PuuCFUBsbQ== X-Received: by 2002:a1c:7903:0:b0:3fb:b008:1ff6 with SMTP id l3-20020a1c7903000000b003fbb0081ff6mr748287wme.0.1690357987512; Wed, 26 Jul 2023 00:53:07 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:07 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 03/11] mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support Date: Wed, 26 Jul 2023 10:52:49 +0300 Message-Id: <20230726075257.12985-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3820; i=tudor.ambarus@linaro.org; h=from:subject; bh=xpyv1UNUOm+7WUBWb0Vl59R+HvbIVKf4klrF0ttDcrA=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYcL1Tyl84sNIYkyBfq2rFtCaH7yjWfYS7u dc1OqqEJMiJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6QMLCACDjtW+TDGGiTS92Jsl6Uk3LbCGtuLZY2zAlHX4QCj3TU4Qt6wzONyOAiZ13yx3a0BiKX7 bgPVNwx70THRRo9pXuw/jM30cQKvhv7fDqDCJt7YrVCW/5deEjgZbw/rAHognAO5JWebQbnz1/y ZNmKBYivfOSoi8ABV84JjXxQQ3XgQlilQLim+XpAw5NNJHoDxgylv19QSaKrddaTak0BOuOd8x9 KVzhxIvba2pr7FPhqUeCN18YfDMkZ58r5pbVjo15JzcrfaDe5Kj1qXt9jqoXg0JgKAGuCGA0v9S qPPsLiTAWlOsSVM3AVgqzxmtDwDnmwT3TXXkUCNcpk/EQuPd X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon's multi-chip package (MCP) devices require the octal DTR configuration to be set for each die. Split common code in dedicated methods to ease the octal DDR MCP support addition. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6460d2247bdf..51eabddf2b16 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_no= r *nor) return 1; } =20 -static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; @@ -164,8 +164,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) u8 addr_mode_nbytes =3D nor->params->addr_mode_nbytes; =20 op =3D (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 0, buf); + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); =20 ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) @@ -176,8 +175,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) *buf |=3D FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); =20 ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) @@ -185,13 +183,33 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) =20 nor->read_dummy =3D 24; =20 + return 0; +} + +static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + /* Set the octal and DTR enable bits. */ buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, + addr, 1, buf); =20 - ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); +} + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + if (ret) + return ret; + + ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 @@ -209,11 +227,10 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) return 0; } =20 -static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; - int ret; =20 /* * The register is 1-byte wide, but 1-byte transactions are not allowed @@ -223,9 +240,16 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *n= or) buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] =3D 0; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 2, buf); - ret =3D spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); + return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); +} + +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 --=20 2.34.1 From nobody Tue Sep 9 01:01:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 834E5C001DC for ; Wed, 26 Jul 2023 08:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231664AbjGZICI (ORCPT ); Wed, 26 Jul 2023 04:02:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232699AbjGZIBO (ORCPT ); Wed, 26 Jul 2023 04:01:14 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DF853A90 for ; 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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:08 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 04/11] mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset Date: Wed, 26 Jul 2023 10:52:50 +0300 Message-Id: <20230726075257.12985-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3009; i=tudor.ambarus@linaro.org; h=from:subject; bh=mCXnzZObQc2zhfJufj3cA5z2xujPAjIEucaG9JmkqZU=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYDwwoqDn25kns6GQbu0V+TxM1w1CZcl4Rj xe+vM3yTYuJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6fVSB/0X+AC60NMt+0iVr9T0QiN63zOwAHa4aMnsmWYJfYuZXMlZjXotN+TvdgZV2x1/iRkEKz0 Z9OitjSmE1sl625kHEt9REkbAJSLlVPlGD9QYiOkcgzAhu6pECnXZmpQ3K7+tlvC8GUPMuKwGqj uNA/4iLiFJ8WxXy+BbTW9GU/ts8E5LM7ZuGYDRzRvMch669wzq/3lM0fKVvDWPK1EGPy3fYw4IU 5bUvLljF86BYpxhjmWFvPyvLFMxjXe4/oNjD4oizCummI26MAtv1ZxaKxj7KXP3rZZp0rXxgO2d gUNWRYOdwBBaymo8K2wg0pe7L7Dsj7nffpxf5g3wgDgepeVB X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano All the Infineon flashes that currently support octal DTR mode define the optional SCCR SFDP table, thus all retrieve vreg_offset. Switch all the available octal DTR Infineon flashes to use the volatile register offset to set the configuration registers. The goal is to have a single pair of methods for both single/multi-chip package devices. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 51eabddf2b16..94d98b5b0ff1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "core.h" @@ -37,8 +38,6 @@ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 -#define SPINOR_REG_CYPRESS_CFR5V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR5) #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) @@ -202,14 +201,18 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_= nor *nor, u64 addr) =20 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; + ret =3D cypress_nor_set_memlat(nor, addr); if (ret) return ret; =20 - ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); if (ret) return ret; =20 @@ -247,9 +250,11 @@ static int cypress_nor_set_single_spi_bits(struct spi_= nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_single_spi_bits(nor, addr); if (ret) return ret; =20 @@ -714,7 +719,15 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s28hx_t_late_init(struct spi_nor *nor) { - nor->params->set_octal_dtr =3D cypress_nor_set_octal_dtr; + struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + params->set_octal_dtr =3D cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); =20 return 0; --=20 2.34.1 From nobody Tue Sep 9 01:01:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 854ABC001DC for ; Wed, 26 Jul 2023 08:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233086AbjGZICL (ORCPT ); Wed, 26 Jul 2023 04:02:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232712AbjGZIBP (ORCPT ); Wed, 26 Jul 2023 04:01:15 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08AFC3AAD for ; Wed, 26 Jul 2023 00:53:12 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b9bb097c1bso860241fa.0 for ; Wed, 26 Jul 2023 00:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357990; x=1690962790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n0Gap5z5HQj+20KA+5rR6ZWXU3MXLJY5RV2SAA/NzIc=; b=JTaUGxTaEzP8WuluF6JI7pcb3FNbQyMdYooHInNRIoD/+m/jyNLdY8PLNgTir7NFNt xxX32PLRCjTkGLkDI+GeSrjtoswcKBjXudphHTpsrrF/+2ZKmjtFkE6mHok1zBbYtL09 YPZGaTsB1yAPTTe0DIVZm2QSRbdLiCrHoANSLFlb2K1sxp2v9psoYQ1Wu9s8mJwGElb6 Md2CKj/rd/oKqURKUF5av1CiVf5kc5Mz34cOXLkPuCvjNQTWSo+hw2lSzrFKNaoYe62M SzfuFAfYA2PmOgKjKKgcV3YcB273IIx7cyqi3HHlU0KuyWOFdh6zsCKGtE5fMPtbRUwa gvxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357990; x=1690962790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n0Gap5z5HQj+20KA+5rR6ZWXU3MXLJY5RV2SAA/NzIc=; b=KdUdqfRFK9m12FIkLCRT/XRq+HtrNISD7yjTGcpOZRiFj80U1Fj4xlLQAuuxZxO+5E HQ3dNmzxny4q4t0Bf3tNhuzY5C9xLobuRFHvqWrVB59011i+E8xMfXmDqQb7lY7j/eky VBPDKKd8D8+3ITbzDRgzu/xrbQ62IO3AyFu6MCVSMCOO/d4e3XLYgtw7Az07EmjXAMVT 5vJ7Au+o84xWDH3r9cIQWpLKrTHAdbNKEUXalXCjzPeWiW1C64vp5x9MnIbPh/oAM6d/ NCYDRyWu6U7wTGc6V+9n08lrwYPO2UEG7ho0HmWT9PmgAW6CSw/uyDQcQSglAeKCaXXc Ybtw== X-Gm-Message-State: ABy/qLaxFDL7tVzuTI48e8flLMQXynCzWpGizYhhG1vqH/N/7eKcwbG4 LDW9jqG8HS8ZuXKcqbjcXrzlGw== X-Google-Smtp-Source: APBJJlGvbeA1bwNEatZegegZYcyw8ZenkB8PdMHec6wLbL3TAmih1qzN2A3UEFv6Rlc8mfMVplU2EA== X-Received: by 2002:a2e:80d3:0:b0:2b6:f009:921a with SMTP id r19-20020a2e80d3000000b002b6f009921amr921837ljg.13.1690357990399; Wed, 26 Jul 2023 00:53:10 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:10 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 05/11] mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset Date: Wed, 26 Jul 2023 10:52:51 +0300 Message-Id: <20230726075257.12985-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=851; i=tudor.ambarus@linaro.org; h=from:subject; bh=q/Qc3k9qz6CGFcYot604zmE6bU9NIV/TJy23m7QhG7U=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYlft4XVdhUmR6ygrhXLxkoNCICvSgBiqvh UqcRB9M36uJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6ecVCAChy9qN/FV0Ep/NahRCUBvsEecWHg3rWVBFRK2+nZiAefeyDXaelwOVrvbB5Lo9Uwj8s/a iLX5lIkS18KbB/29CjxJ7cJXEwKAQFlu+yHMENoGdDrfccdeCv5FlHNSnUomR2oPRaBqoPR7V0k 4ndWXvTUsF1y7+DcPSPtdd0H/MV2TUjc/qA8urT2xYkYlN8uqhDd+Vb3AK2M1Rc5MTIPxJYgV7t f1mi4jVSbQjSgHhoAs+i3ApJRLNwg4BM3e4djHJQwUK+nIZ1pGtUf/kayMgcaXWUjVuPgtsiKWp PQkB3VfmX7citfYlFFZm2tL1KKfBTVYO+3/3oBoil9apeons X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano s28hx is the sole user of cypress_nor_set_octal_dtr, which already uses vreg_offset to set octal DTR. Switch the ready method to use vreg_offset as well. This is a preparation patch. The goal is to use the same s28hx methods for the multi die version of the flash. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 94d98b5b0ff1..6d8dd800ba65 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -728,6 +728,7 @@ static int s28hx_t_late_init(struct spi_nor *nor) } =20 params->set_octal_dtr =3D cypress_nor_set_octal_dtr; + params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 return 0; --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E18B2C001DC for ; Wed, 26 Jul 2023 08:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230453AbjGZICR (ORCPT ); Wed, 26 Jul 2023 04:02:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232734AbjGZIBP (ORCPT ); Wed, 26 Jul 2023 04:01:15 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB194C1C for ; Wed, 26 Jul 2023 00:53:13 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b703a0453fso95362631fa.3 for ; Wed, 26 Jul 2023 00:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357992; x=1690962792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3InCljZqye4eFwsDTu+IODNCfq24t38Cj22eVGkKqxU=; b=SjCV/8xNSkyjqz5FS+Xw75QoV10ooDUJ1MU4dKZfKvJ8elu1NZ+8JLkUjZ1UE09dPW bhVr6aNQ4rUPXYC3R0S6qwidvA4On3ayyYu3ARZ61swT4EPMgxE7j+jshMJ7h21kU6sV XpsuvTsGptgeKeiCtZyvLTksp4dkMibMn1QyuRIH64if7+mfwvQ3Qpa2GYwk6ltN7oFK UXrOVBPgtLwC0ewYXDFv9BN3YI61WM3CdcFG12Tf+JmbODG5NUpsFQbCn3i2BHB/6p48 w0HUb/uWeVgsLCWI14Q8aKNKM4flHeRj/S5eJt82vmoBhmjEN/NFmIvNsc2Rj2AvC19H So3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357992; x=1690962792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3InCljZqye4eFwsDTu+IODNCfq24t38Cj22eVGkKqxU=; b=Fm+MX85BIBD0WL/oTEjN03HlpXI9/yZ5QQVkESnyTWQ0O/JqDkxkf8wXoVudZWIzxQ y5OBnMZfvDkz7d3cS7AMMbne3WO8kvPZ+oOGbFpvuhlG5Az2J3PUfWn9aevWm19WqaYn AOrMEtjqZoxiOQ6++lafviz/P+CBNdyjIk7/xoTo3cVWuIqdpovRjeze8wAvXicjF/Cc 8lEGtnMNvyiv8NVIpdLE/+m9ohaFDckxZ8OPIcjdgM3A5Vl1L0pcQIWMhRSGEIY7tJDV j3MyLvyvWfe0+faflv0VwoW7V0bgw2/TBikB+ZZ19iN6LX+BigXAHOkhicngIJhTNG/C yPZw== X-Gm-Message-State: ABy/qLa2eOlTjo1dL685dl2gpYpjUg/mPGPTsCA8yx+hmcktQgL+XDBY d6orOd+XkJ56JTGnvBgjz7jWrg== X-Google-Smtp-Source: APBJJlEBXqLQv3e010LqDbxJd0efexmnQKBKiXcJ4lUJnBWUHbvBTg9p6Tg94k/lVYJgGJeyc9Q9bA== X-Received: by 2002:a2e:870d:0:b0:2b9:acad:b4b2 with SMTP id m13-20020a2e870d000000b002b9acadb4b2mr828072lji.6.1690357991856; Wed, 26 Jul 2023 00:53:11 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:11 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 06/11] mtd: spi-nor: spansion: add MCP support in set_octal_dtr() Date: Wed, 26 Jul 2023 10:52:52 +0300 Message-Id: <20230726075257.12985-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2370; i=tudor.ambarus@linaro.org; h=from:subject; bh=doE8v18UAwCgNrGgR/vrxrYb2ko5JOoI6sQ8dWotQW4=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDY3mqSfchKqowpgyrLyI3ImYTReUH+R5oS1 Y/KJTj+vbGJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6QyfB/4uuxOaTt48p7ouhOQz71ZZ+86XFAaMCYdjr/yy1lCkCARo5ETZ9JZ0HbsUws1oCCZHr4Z GlQwhLqcDzWomLtFap317Njk3lJcTDVeREJsrGWfd0qajoSDhy67NX6PYbH+Bn43T+uOeWcRqku zrFsnnCnBVxYGQrQNOheDB/9SmWrrb6oGw8wuVKAW5dW9+ch9a1pdqADs7P/9Z58v417M+pDLRA +T5IB2oQjksf0J22I1sDE5L1YhcbDiuejBj426V/iljSonJd2pIv1qLK8pwaLsBgvTKxEGOF5pH eqDOSq3HYievyFVpU7XAejWrJhAovmJIfM8pEIt5ha3ifHJu X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon multi-chip package (MCP) devices require the Octal DTR configuraion to be set on each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] populated from SFDP. Add MCP support in set_octal_dtr(). Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6d8dd800ba65..b3a710985f84 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -204,17 +204,19 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; u64 addr; - int ret; + int i, ret; =20 - addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; - ret =3D cypress_nor_set_memlat(nor, addr); - if (ret) - return ret; + for (i =3D 0; i < params->n_dice; i++) { + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; + ret =3D cypress_nor_set_memlat(nor, addr); + if (ret) + return ret; =20 - addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); - if (ret) - return ret; + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); + if (ret) + return ret; + } =20 /* Read flash ID to make sure the switch was successful. */ ret =3D spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, @@ -249,14 +251,17 @@ static int cypress_nor_set_single_spi_bits(struct spi= _nor *nor, u64 addr) =20 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; u64 addr; - int ret; + int i, ret; =20 - addr =3D nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret =3D cypress_nor_set_single_spi_bits(nor, addr); - if (ret) - return ret; + for (i =3D 0; i < params->n_dice; i++) { + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_single_spi_bits(nor, addr); + if (ret) + return ret; + } =20 /* Read flash ID to make sure the switch was successful. */ ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83B40C001DC for ; Wed, 26 Jul 2023 08:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232814AbjGZICU (ORCPT ); Wed, 26 Jul 2023 04:02:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232753AbjGZIBQ (ORCPT ); Wed, 26 Jul 2023 04:01:16 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEE1B4C22 for ; Wed, 26 Jul 2023 00:53:14 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fbc59de0e2so55516035e9.3 for ; Wed, 26 Jul 2023 00:53:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357993; x=1690962793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uGJKtRw4TvIjPpcEW3YYZgR3twL7SAYz6w/Nk+vj+ZE=; b=w5N02p5SiiYJzQLFwwFAOX+7CvxBIy0/op/fP7rzRTUMU0q9f8p7MQQURBZj4jmMwb ps3gfl6B3efxxCc9Rcm6T0DCVvNrXD60wCEtEg/3dHSkKuI3Wkg8LoEbKuXmJohWUYwd v3n5m5yVcBLJdQbf4gZkS9SaHcbJOn3KVu6ovu+vDqY5U1qLZ3+jUDaxdyLsIHqJAcFd CG9dEpcSmvtCvkrsSU/DkYFOCkGIOE6Sc2zS83joAyacLwSAcf53QJdm8GiQD7scsbbh ncrZnYFIryqFqNh20v0sATflY58Ri13I8pr8jQX4owbRd3imaUsrEdZkZiZ6su2JyQqf 8Gsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357993; x=1690962793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uGJKtRw4TvIjPpcEW3YYZgR3twL7SAYz6w/Nk+vj+ZE=; b=TvXNtcEyMnMIoeqz01ZRKTCFwjCyVxtikcZ+tn6Bz9XSqDHVXLuTizV2rgv02yS/zw LYI4D/8K5Ld3AoKdwsljB/EapY+9gEQKywR7o9x0MmnlzTv2AvU5fuFWxeg7xoAuic9H 5IekzhmdJNqgAF2LA7DjQCErKVat5NmGxkbuHxpzUn62e5a5raYdGic4T0IlvJh4xwgq ycCZctA263SDPherx4rnA17dzYv4KnKz9YhSFaViSMiR/GD2CfmSkpwFCuWaeID8QnDq z/FJZSPLeN76aeqcT3Oc8q0HtCpaqu3Xwivm9s9oK81gZQIxXXPjutjyMHxYy0E0s//+ knEw== X-Gm-Message-State: ABy/qLYA+3XvqImoOynMFX1HJzNsu6tP0Fw0Wgy1e9VN0AFcw3rIjK6I wqhXUJ5eeH0S2nI9XNGPvdoePg== X-Google-Smtp-Source: APBJJlHuqlDegBijDnUs0fV12jGszcpfU+t1gDU97/q7LSp4HP8yLabBB+6uJmrtZfykKzX4uMVLMw== X-Received: by 2002:a1c:4c1a:0:b0:3fc:80a:9948 with SMTP id z26-20020a1c4c1a000000b003fc080a9948mr767283wmf.19.1690357993248; Wed, 26 Jul 2023 00:53:13 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:12 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [PATCH v4 07/11] mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP Date: Wed, 26 Jul 2023 10:52:53 +0300 Message-Id: <20230726075257.12985-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1173; i=tudor.ambarus@linaro.org; h=from:subject; bh=+Z4bxTGyJ9/9zDwMM8hBMtji+B4a+ORn3JZ7mTF+ybY=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYGHy/s6o006qFtWZQ3anN1qewblLvDmIB3 scXS18pCACJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6TWfB/9+5mfv0gOBgUZej7KRxVVtTF0Ls2oliPm9WOBhfe1lEk3zgrtBubIoDbS6zZbhof3gLKf xRCCopSCMllajAXkrKpjHJaieEAP/V6cyndfDmBQDTduen+TPQ5uBJVZ3cXIvH7IE5EhNN41BYq Ad8tF+zawYIicKhuL0ZXsNYASZY0OuSTBuEqatYmyvhqqkRFKMQ8TUK2kXbcZdV+A6CMaSHSsPn Hl9k4cEdF6fnjVn7DARZLc35vf9+J8bmj39cY55Ow2yGhVcDFEKe8w31lznDcv6NDKhSHfTNTOZ GuViUy7bNO3W7ZMFSrVKdRKRq7XY9c2lqVDdtG1JwwxnGvom X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano S28HS02GT uses RD_ANY_REG_OP to read status of each die. In Octal DTR mode, RD_ANY_REG_OP needs dummy cycles (same as params->rdsr_dummy) and data length should be 2. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index b3a710985f84..d7aa0a90949a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -102,11 +102,17 @@ static void spansion_nor_clear_sr(struct spi_nor *nor) =20 static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 add= r) { + struct spi_nor_flash_parameter *params =3D nor->params; struct spi_mem_op op =3D - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, addr, + CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, 0, nor->bouncebuf); int ret; =20 + if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + op.dummy.nbytes =3D params->rdsr_dummy; + op.data.nbytes =3D 2; + } + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) return ret; --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58318C001DC for ; Wed, 26 Jul 2023 08:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233101AbjGZICX (ORCPT ); Wed, 26 Jul 2023 04:02:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232772AbjGZIBQ (ORCPT ); Wed, 26 Jul 2023 04:01:16 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2969B4C23 for ; Wed, 26 Jul 2023 00:53:16 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fbea14700bso52881935e9.3 for ; Wed, 26 Jul 2023 00:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357994; x=1690962794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KRwCsCVO3o3aM9vhw4WDE//m6gXQY0sVfiQwqyQBByI=; b=YXxVeyvyh2kk+2npRszeRvUdhL2tu2M+9pz5dYrvUt3W7dIX7I+BLUZ2D6DZh58eAu X+byLqf53pdHS5MUQgXg87+w48KYO4dt5Io4LhL/u15dIYbx0bNXkFbL0rpmN+VkQ9U4 2Iw6dUen4pZA4/SM/xIvBvo2CAmeCAjQyRKtrY7in5jHPob2qD6w6hD9r0qINF9Fv12Y ygV6Yq3Kl5Ow1+T2WcoZ3C4641u0Z7qls+13hZjZ9VuQZFjv1Z9/zh3j0J4CQVXHvabc zreB7HebJ/y5/5aDBV0KbOqX/1ObTYS7lcuC/z8USf9h71Js4kSGYKiR4H0zr6j8izYa yKqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357994; x=1690962794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KRwCsCVO3o3aM9vhw4WDE//m6gXQY0sVfiQwqyQBByI=; b=Prz9QNZdPHzZdn92Ap8vUSKkEzz1s4xmUmRDr84ggUv2UygNciJj1BTWleWwHAyyIv nehC3ZESKNaaSYPrYayiih1VTc60XKIrEng3cUb89DxywgFtP2oWdBJr5GulTWN6NLqA jRofrw5q97r5kBHMwqe0QXS6C135GzEpBxsNc9PDqy9s6N5FQyQr+QSz9ho/7g1BBfQm Fd9zgQbl5HMrv319lge01ww1KbKD2pOcx6hY5Lm/R2JFavUDlsyiFILWuO/3lcJCkXtH nTkBRmE3yic5+53HSOL3GDnY/1Gyx0FcQuTYcQ7ou2veMznj9NXirQ/XA6rb0x14l+gp g0Aw== X-Gm-Message-State: ABy/qLZiPe1ZP6gOgxHQPJGTacByaBuVwVvaCJmJ89fiagmz02tqj3ue u38sKUapU+48F2fqHLxii/cUeg== X-Google-Smtp-Source: APBJJlF8IgGEtSvq2AwcZD4JVeCePRGhSZj99SgDX4tKedd8NAOTK9iVdemTe03ZncVNXZe13rGCeg== X-Received: by 2002:a1c:ed04:0:b0:3fc:586:ccb4 with SMTP id l4-20020a1ced04000000b003fc0586ccb4mr759069wmh.36.1690357994753; Wed, 26 Jul 2023 00:53:14 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:14 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano , Tudor Ambarus Subject: [PATCH v4 08/11] mtd: spi-nor: spansion: add support for S28HS02GT Date: Wed, 26 Jul 2023 10:52:54 +0300 Message-Id: <20230726075257.12985-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2496; i=tudor.ambarus@linaro.org; h=from:subject; bh=BGQp+yPvPvQ1vo1DVawT4hLAY/tUideX2TLncpyul4o=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYcqZvVLq6lYHgbxnZoNm+XYaMiaT00ViYF o/ZctOKx1OJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6fxICACCwpHJXaHk90+tNOaqFRWA3xj6/36wYT8q1V+U0IXxgHz3ON+5UrMyETEx/KPSHVUDGKm IH/lUMAlKmLTGB4j6OGN+DAS3EHu/kULd7bJo8sBWoj2D7hPLZPMXEdUPRjeiH0HsXNcrmJTx9Q AbPodOoikjjeHmXbjn6BoZvIX96vkZLVgFOeeKniSmXkaK07uOKfj/7qujbGHBeTBa7SstGLZp9 QZ25iwAnT8q1uIswcAh6zLM2clJ6H+p58W59v4Lc7nL5grhRDT7ptZsQRi339j9sp0djHUx1p9k r0iKd8kyL/3iAYvK9KoiZVPvroW0kyDpZOqHUrfdALB6l28k X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb, multi-chip package, Octal SPI Flash. Signed-off-by: Takahiro Kuwano Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index d7aa0a90949a..1c5671a3751a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -693,22 +693,23 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *= nor, bool enable) =20 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. */ - if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D=3D 0) - nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D + if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D=3D 0) + params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D SPINOR_OP_CYPRESS_RD_FAST; =20 /* This flash is also missing the 4-byte Page Program opcode bit. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); /* * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR= ], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); =20 /* @@ -716,7 +717,11 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) * address bytes needed for Read Status Register command as 0 but the * actual value for that is 4. */ - nor->params->rdsr_addr_nbytes =3D 4; + params->rdsr_addr_nbytes =3D 4; + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; =20 return cypress_nor_get_page_size(nor); } @@ -916,6 +921,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, + { "s28hs02gt", INFO(0x345b1c, 0, 0, 0) + PARSE_SFDP + MFR_FLAGS(USE_CLPEF) + .fixups =3D &s28hx_t_fixups, + }, }; =20 /** --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84B74C001DE for ; Wed, 26 Jul 2023 08:02:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233105AbjGZIC1 (ORCPT ); Wed, 26 Jul 2023 04:02:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232806AbjGZIBR (ORCPT ); Wed, 26 Jul 2023 04:01:17 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC0C34C24 for ; Wed, 26 Jul 2023 00:53:17 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3fc02a92dcfso55620465e9.0 for ; Wed, 26 Jul 2023 00:53:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357996; x=1690962796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cU2izS7ltcfKojKR/fjnJHc55e+84FS6l+Y7MexOBa4=; b=tc3ftSFSYfLDFqyNY3lha83ooX0LEVhGmAmfhijWboXT7OL8NEWQo0CgIGiy0Xwbjp R2p2tgbN1InIHYLx1Ks6LLWjZ7vqGk8j60STJvMP4qpdD0nSUR0qly7PncnmmNneXBTB kgTo1LRl0yrJgRFJEYwsZAhcBZm4i2KhMHSAHvB8EBn6yb3PHASy/2uwZZTvdSMyr/1B WjlZ2VP2JPh2+66dgd1RCicPUPkLBa/yRZYetx0KVdJat7xrrxbuzdPLemA8Jx+82ER/ eGXL6GxQKfMTDkF+shdtaUDkPq+D0yOb75mY4330ba5kRoXKLfkNRukgrMkPO+ZaVo3N k+Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357996; x=1690962796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cU2izS7ltcfKojKR/fjnJHc55e+84FS6l+Y7MexOBa4=; b=hEnCEMyx0WCes9sgQgciGZLow2jTzeSowcvGxKBfvcD+vrY7ydcg+/21RzCnA3roTu A9mTcl5UczFePy6PA8MereHuscYUtIBNnTL9VJTsFqZvSqI9OhGZAwd5Sb+T3ZtPfPx7 Nk1vGCd6BzGBHL326J2DFxfzmo9awh09djnDQeS4/4iyHvAWPiTETT+J9hlh6/s4yUet ojEbGXPr0UjncAYzMRbbmsuILDZQ6mOj/h+LdI1e1fcVBq5MTx9/LzK0Wv/Ql0gW4QRI S71Ku2XwOyfcYcUmXaBUnE3GjviRg2EfQgwWrpeXarbgeHx+ZNjvNeUSVAZF3ZhLHPVp b2hg== X-Gm-Message-State: ABy/qLYWDPXpzW3eyC5vHqYryXjxzrGkS+WHcf3zDlotKOG7UeUjLfdF N9iu009KXBKM1g0fta8zff22auP78xikkjtRfNc= X-Google-Smtp-Source: APBJJlGGKJUPX9zKGu3j7bheBiAy9QpBMFUNiQ56otABz73VtyPfm8rT9IqTE+uw3ImyQfldicdnPg== X-Received: by 2002:a7b:c319:0:b0:3fc:8ab:762a with SMTP id k25-20020a7bc319000000b003fc08ab762amr790146wmj.18.1690357996247; Wed, 26 Jul 2023 00:53:16 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:15 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v4 09/11] mtd: spi-nor: spansion: let SFDP determine the flash and sector size Date: Wed, 26 Jul 2023 10:52:55 +0300 Message-Id: <20230726075257.12985-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2622; i=tudor.ambarus@linaro.org; h=from:subject; bh=NWgsTDYFKhLtFe1K3wQNDGm5Jii1w6YuOY2WYJMPxYk=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYxqAXwIx9um/ULZdRtFO/54oPjAlOZo3WV 4xeGJRr5K+JATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6fDXCACmE/+X59ggt+KG1kP7Do7JSnTBG9Yl+9ZLzTJ60ZG18uQ5N7K62ujAyuU2wGAyoPEpCDJ 6wC9Ec2XzCrD1xCn54hJZ9/KTSQi0EENoBPkvgnQ/ZkF75GungoqAxvvBTaGzT3xwyWziJr4tQN dL/4l46b23943U7VeMjVPPXpISWZeXi9znDvnEy5uw4W1GltVT6rHQ7aYkVGP+9zQAaW2ywWWas xEqPzjfSzC2pN3JagClyNmPlHKDBecOf6jGWpcOasqACbMdCgrmrdX7+53hk5wkKqy2wkEmIUFp c+P07MetPKJt7pckkYdJwOuMTZtECX0QFhpbt3UWETIsxFQP X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" sector_size is used to determine the flash size and the erase size in case of uniform erase. n_sectors is used to determine the flash_size. But the flash size and the erase sizes are determined when parsing SFDP, let SFDP determine them. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 1c5671a3751a..30a3ffbfa381 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -873,11 +873,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25fs256t_fixups }, - { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) + { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, - { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) + { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, @@ -886,11 +886,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, - { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) + { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, - { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) + { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, @@ -901,22 +901,22 @@ static const struct flash_info spansion_nor_parts[] = =3D { .fixups =3D &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, - { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) + { "s28hl512t", INFO(0x345a1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) + { "s28hl01gt", INFO(0x345a1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) + { "s28hs512t", INFO(0x345b1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) + { "s28hs01gt", INFO(0x345b1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8595DC001DE for ; Wed, 26 Jul 2023 08:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232585AbjGZICe (ORCPT ); Wed, 26 Jul 2023 04:02:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232812AbjGZIBR (ORCPT ); Wed, 26 Jul 2023 04:01:17 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C8D4C26 for ; Wed, 26 Jul 2023 00:53:19 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fba8e2aa52so64347255e9.1 for ; Wed, 26 Jul 2023 00:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357998; x=1690962798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5OR4WatIj1vDPYbZVDclfDkYALtpmV2GorGc4TguZ9g=; b=Jz3uDiHidmkOdHqQ4A15ozND+FenOh0akWPvH168WQkS1ulMaER6nfRl9L/yUu/yT8 tm+X3r56QMEYUzaioEswopvrQaqqBZNVgeUtcZH99wMcv/YKJMp39Co3F97ewaUjxYQs FW6uAgjTV8NUw1k8wmQBJkE2XwtRIqmgtykRdgDMZtp1Wrj410nKRm0SslzYC29aabKg 5XRMz02kdUXh7MMWRZ9ngTjTnfkxU4Nr8+9kPzITZmHXORgKG6P0wT65gOphuHcU4NjJ XcNL98mIpfocURNFsJEzpplNEmKGzzqvQOyyFUP3XO6Yuncft9yPKVJMvbm775ob8FjX ZYNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357998; x=1690962798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5OR4WatIj1vDPYbZVDclfDkYALtpmV2GorGc4TguZ9g=; b=jJplsBln+q6K2xYNAVI9h2IrUl3O5bPAFhBsLoYfo9H0gYz7+vZl97weul1s51/oYk 0GF8bGatF/sqosP/+q8epCvmhgcYr3yTGHlcvvmj/ypOAw3OKaQzLP47WEr8J14iNA1g Rfbe49MBCtb+YVDIl/w4ktSZXxZI1bDs140uvGXboIucDhln8l5G/GM8yBkeSKX0kG1h YJCxBlJpa02OkhjJaTaMlo2R2LDeXgu8XNpfyA4k3oBVXd6qYhYXF1jGvSgckvB2kexH keLvg5O3VxpqQek39Yv4YfumeT0yazYAwZf+NvMvCokN6DGYa9BouXur/riZRCOsajMY mX5A== X-Gm-Message-State: ABy/qLZKD7JG+NAWvLZ3r3wQ70U/ikpLoyaR+x1jWPRnJrUQAyXokEy/ Kgs3HMeIKStFTbpo1AL90Mw+7w== X-Google-Smtp-Source: APBJJlHbavuz0p8nucrQuOaoL5YFpD5cb/Psc+qFF06gSLSvyRwttFangsg+w898wdRx7yDfaLeK7Q== X-Received: by 2002:a7b:c407:0:b0:3fb:ef86:e2e with SMTP id k7-20020a7bc407000000b003fbef860e2emr785798wmi.19.1690357997872; Wed, 26 Jul 2023 00:53:17 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:17 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v4 10/11] mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable() Date: Wed, 26 Jul 2023 10:52:56 +0300 Message-Id: <20230726075257.12985-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2125; i=tudor.ambarus@linaro.org; h=from:subject; bh=QdB1CqYeo+E0vRmCT5AKj+737qFOif1g4DSnqlL1Z6o=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYWzzJw8YDhGmjAHNiDSE8hUDVOK83EN137 yf6F7ibY/aJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6TaBB/9OD4NAVj0Ze+yCwu+WLSTy9opP6fNQcZ6JV8WDN5h11aIzOo2vW3Lt1VPTKpL8Fxpr/7U 7syEMtg2iTm3aBOjM/4B73+vwAxFd4xon9PDcZ2f8YOOgiuOhKeyhA+r4JK/qFmEE1usbf6ssof wtXJast8GMQqjx8rD6jO0KDx6CZeG5vnw4XvpO+SWb361znYdbRxFtmWFJ5jCMaawhh12k4z9au Bw6QnJz1PO5u05Jzwi0sD4gBX5dGBFm9/cWWspuSFT8hpiq3B+2gkZ+wt34v7dcUpPnsH8LHzmG ixoMeoAoLpMMtAlETLwlXqiO1JV6JhWpwv6PqPdqFzlLkjXV X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All s25hx_t flashes have single or multi chip flavors and already use n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t to always use vreg_offset for the quad_enable() method, so that we use the same code base for both single and multi chip package flashes. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 30a3ffbfa381..6abef5b515a1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -24,8 +24,6 @@ #define SPINOR_REG_CYPRESS_STR1V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) #define SPINOR_REG_CYPRESS_CFR1 0x2 -#define SPINOR_REG_CYPRESS_CFR1V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR1) #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ @@ -348,10 +346,6 @@ static int cypress_nor_quad_enable_volatile(struct spi= _nor *nor) u8 i; int ret; =20 - if (!params->n_dice) - return cypress_nor_quad_enable_volatile_reg(nor, - SPINOR_REG_CYPRESS_CFR1V); - for (i =3D 0; i < params->n_dice; i++) { addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; ret =3D cypress_nor_quad_enable_volatile_reg(nor, addr); @@ -657,15 +651,17 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; - + params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 - /* Replace ready() with multi die version */ - if (params->n_dice) - params->ready =3D cypress_nor_sr_ready_and_clear; - return 0; } =20 --=20 2.34.1 From nobody Tue Sep 9 01:01:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1E9BC001DE for ; Wed, 26 Jul 2023 08:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232397AbjGZICj (ORCPT ); Wed, 26 Jul 2023 04:02:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232834AbjGZIBS (ORCPT ); Wed, 26 Jul 2023 04:01:18 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231274C28 for ; Wed, 26 Jul 2023 00:53:21 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b700e85950so93844231fa.3 for ; Wed, 26 Jul 2023 00:53:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690357999; x=1690962799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X5jcS1qvmfeGuaQwUWQlurqi39Eg/E+0di+mOyaXrvI=; b=nsZniQwd928rjHv8N0YUoY18C0hZZ4OKCNz9qYqK1GMZ9f+0tu21Ib9aoaLzgQItdA WuVhEVpUkIJfrrdDrNDta1NsL4DCX4vb6dxQb44q04v+tM4m6p+ffqpE9+wJCQz6HVha z+xVBRqQuX5VBPpfh+cXuvL7We+3K8xDkJyMDd2iAyjVYawjcx5Tj/ymx91MrHW9JKeP P6akq/vC52ae4Z7W4ZgryfYJFjGYNwRl8wR4HOwapGJ3objZtPYTNJtIIDVmSA6mBInK Jmo6Iv9s4O5Qw9QtgKSFOuHCOupIsMzHV4kz3tDbOa7hV5K3eSQ9I3F15iL8FV138C0V TMVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357999; x=1690962799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X5jcS1qvmfeGuaQwUWQlurqi39Eg/E+0di+mOyaXrvI=; b=dkJnWUSqaBCPLLzeTzcYqoXfzbqy5l8At+5jXS9DTpDFqNTOBrpQ02i+084d4AZxQ+ 9bD++GdKk7WEC1TY8NpzQMZchJoceZvc18CXgJ5VUvonxlYdcCArPqy25TKuc3K+Krm3 SHSHGmDyOEyEi6wH+v59VHc8HHczG/Hr30ExVtFdrh1JllEsUF4Pbw0F6QyjYRHKUqMj ohtCXYGaLcWkNhc8qf71tjOdZXDubw0k5oXf4I2/Ppf3AnDZSI4WmjfjyANybKZ2pyqx eEY0H3IXnaRgoITzFGgj349DGaawM7XC/k2aYuE+fELoYYMT+i03gOxBzguHuQl+luV3 Lf1Q== X-Gm-Message-State: ABy/qLZC9TjwWBozbantpIf7vFIlRXJUdRTnmqazXSglVR5zNIQmfWF+ I69YTvt0gbrn9ruz+YGXhNss5w== X-Google-Smtp-Source: APBJJlEvBR+0YDOzl0+01yUiRq0NFNaRHew75JOQ5wEpYR/E8ZKz0lcpzHaesMh+oGmFdQ/BMa957A== X-Received: by 2002:a2e:b163:0:b0:2b5:68ad:291f with SMTP id a3-20020a2eb163000000b002b568ad291fmr832496ljm.19.1690357999459; Wed, 26 Jul 2023 00:53:19 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id h14-20020a05600c260e00b003fbca942499sm1264346wma.14.2023.07.26.00.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:53:18 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v4 11/11] mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offset Date: Wed, 26 Jul 2023 10:52:57 +0300 Message-Id: <20230726075257.12985-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726075257.12985-1-tudor.ambarus@linaro.org> References: <20230726075257.12985-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7480; i=tudor.ambarus@linaro.org; h=from:subject; bh=6eTHq2NR9v4yz00ZyFtEXFO52VWKVfLrd5UtS7Vf+L8=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkwNDYP/pogcFjD8Enf1q4+mfRGt0OIeM7D54FU xi6nM+wHBKJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZMDQ2AAKCRBLVU9HpY0U 6dIDB/9RNq1W9pOH9zI6GApqMHrqYjmLmSCU9aG63oJphZ+xNXqbsBIpLuSnCx3FFQHYcY1oxx1 L9RMlwM08eOG5Xm675XrM6GxSgLIDRXaVFzNRq821I/bBYCeo6n6D/0B5nFNdXRlPT0yLN0hUr2 X0m4OjbCr9cBTVxJeeUhLwH72CqufBXT7vBh2kka5lg8n1YKwubTb9Tc0dSzguj5Ivgeo+E4cD7 IQRMzYexPhllTngHL8omuQ13CFHGlNeHtVoK3NWfm/1QXfN7hW92nRD3Iu7si7m9hSmsuxGyNva +BMY5dRVuiz1og0ydGYJSDoVd7FUaUqLMWiGywOdMPj+OavH X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All users of cypress_nor_get_page_size() but S25FS256T retrieve n_dice and vreg_offset from SFDP. S25FS256T does not define the SCCR map to retrive the vreg_offset, but it does support it: SPINOR_REG_CYPRESS_VREG. Switch cypress_nor_get_page_size() to always use vreg_offset so that we use the same code base for both single and multi chip package flashes. cypress_nor_get_page_size() is now called in the post_sfdp() hook instead of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT. Consequently the null checks on n_dice and vreg_offset are moved to the post_sfdp() hook. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 113 ++++++++++++++------------------- 1 file changed, 48 insertions(+), 65 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6abef5b515a1..a23eb2ae9488 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -32,8 +32,6 @@ #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 -#define SPINOR_REG_CYPRESS_CFR3V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) @@ -467,28 +465,17 @@ static int cypress_nor_set_addr_mode_nbytes(struct sp= i_nor *nor) return 0; } =20 -static int cypress_nor_get_page_size_single_chip(struct spi_nor *nor) -{ - struct spi_mem_op op =3D - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR3V, 0, - nor->bouncebuf); - int ret; - - ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) - nor->params->page_size =3D 512; - else - nor->params->page_size =3D 256; - - return 0; -} - - -static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) +/** + * cypress_nor_get_page_size() - Get flash page size configuration. + * @nor: pointer to a 'struct spi_nor' + * + * The BFPT table advertises a 512B or 256B page size depending on part bu= t the + * page size is actually configurable (with the default being 256B). Read = from + * CFR3V[4] and set the correct size. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_get_page_size(struct spi_nor *nor) { struct spi_mem_op op =3D CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, @@ -518,23 +505,6 @@ static int cypress_nor_get_page_size_mcp(struct spi_no= r *nor) return 0; } =20 -/** - * cypress_nor_get_page_size() - Get flash page size configuration. - * @nor: pointer to a 'struct spi_nor' - * - * The BFPT table advertises a 512B or 256B page size depending on part bu= t the - * page size is actually configurable (with the default being 256B). Read = from - * CFR3V[4] and set the correct size. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_get_page_size(struct spi_nor *nor) -{ - if (nor->params->n_dice) - return cypress_nor_get_page_size_mcp(nor); - return cypress_nor_get_page_size_single_chip(nor); -} - static void cypress_nor_ecc_init(struct spi_nor *nor) { /* @@ -571,20 +541,32 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, if (nor->bouncebuf[0]) return -ENODEV; =20 - return cypress_nor_get_page_size(nor); + return 0; } =20 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + /* + * S25FS256T does not define the SCCR map, but we would like to use the + * same code base for both single and multi chip package devices, thus + * set the vreg_offset and n_dice to be able to do so. + */ + params->vreg_offset =3D devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL); + if (!params->vreg_offset) + return -ENOMEM; + + params->vreg_offset[0] =3D SPINOR_REG_CYPRESS_VREG; + params->n_dice =3D 1; + /* PP_1_1_4_4B is supported but missing in 4BAIT. */ params->hwcaps.mask |=3D SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4); =20 - return 0; + return cypress_nor_get_page_size(nor); } =20 static int s25fs256t_late_init(struct spi_nor *nor) @@ -619,10 +601,20 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) { - struct spi_nor_erase_type *erase_type =3D - nor->params->erase_map.erase_type; + struct spi_nor_flash_parameter *params =3D nor->params; + struct spi_nor_erase_type *erase_type =3D params->erase_map.erase_type; unsigned int i; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * In some parts, 3byte erase opcodes are advertised by 4BAIT. * Convert them to 4byte erase opcodes. @@ -640,10 +632,6 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) } } =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (nor->params->size =3D=3D SZ_256M) - nor->params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -651,12 +639,6 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; params->ready =3D cypress_nor_sr_ready_and_clear; @@ -690,6 +672,17 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *n= or, bool enable) static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. @@ -715,10 +708,6 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) */ params->rdsr_addr_nbytes =3D 4; =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (params->size =3D=3D SZ_256M) - params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -733,12 +722,6 @@ static int s28hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - params->set_octal_dtr =3D cypress_nor_set_octal_dtr; params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); --=20 2.34.1