From nobody Fri Dec 19 19:18:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 793E8C0015E for ; Wed, 26 Jul 2023 06:54:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231733AbjGZGyf (ORCPT ); Wed, 26 Jul 2023 02:54:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbjGZGya (ORCPT ); Wed, 26 Jul 2023 02:54:30 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4C4A1BFB; Tue, 25 Jul 2023 23:54:27 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36Q6sGqR125642; Wed, 26 Jul 2023 01:54:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1690354457; bh=HYvKSPC1lxV1Pgg9D+hvA9yuxZNj88tDZChJC8z98I0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MzFLxiLwX/BY8wc3aN29H1LdMzhPU2ipEw93MwpKbYKPg6d5G0p0PiC9XMVDgLdo9 2RtNKO6gkj8UK4B5VlLWFFJH0H4FNUj/Af4+F9saxPxsXe5HcHMhrvMW8LNU5I/Muh 7RmRiD4wi26GmyxgjIGE1LXJdwg8uQPFTJP8ydn4= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36Q6sGkG048126 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Jul 2023 01:54:16 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Jul 2023 01:54:16 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Jul 2023 01:54:16 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36Q6s8Te013490; Wed, 26 Jul 2023 01:54:13 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , , Subject: [PATCH v3 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node Date: Wed, 26 Jul 2023 12:24:06 +0530 Message-ID: <20230726065407.378455-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230726065407.378455-1-s-vadapalli@ti.com> References: <20230726065407.378455-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch. Add devicetree node for it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Siddharth Vadapalli Reviewed-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index ed79ab3a3271..4d0d27e7ca1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 { mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; =20 + phy_gmii_sel_cpsw: phy@34 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x34 0x4>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible =3D "mmio-mux"; reg =3D <0x80 0x10>; @@ -1039,6 +1045,69 @@ cpts@310d0000 { }; }; =20 + main_cpsw: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-coherent; + clocks =3D <&k3_clks 28 28>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw_port1: port@1 { + reg =3D <1>; + ti,mac-only; + label =3D "port1"; + phys =3D <&phy_gmii_sel_cpsw 1>; + status =3D "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 28 28>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 28 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + usbss0: cdns-usb@4104000 { compatible =3D "ti,j721e-usb"; reg =3D <0x00 0x04104000 0x00 0x100>; --=20 2.34.1