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[83.9.3.221]) by smtp.gmail.com with ESMTPSA id r5-20020a5d52c5000000b003143bb5ecd5sm15672475wrv.69.2023.07.25.01.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 01:52:00 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jul 2023 10:51:56 +0200 Subject: [PATCH] clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org> X-B4-Tracking: v=1; b=H4sIACuNv2QC/x2NWwqDMBAAryL73UAeiNKrlCLJZqMLEkO2LQXx7 l36OQPDnCDUmQTuwwmdPix8VAV3GwC3WFcynJXBWx/s5EfzOhqjmf1sl8zSEJc1C5rk4lQCja4 EBI1TFDKpx4qb5vW97ypbp8Lf/+3xvK4fo7t4CX0AAAA= To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690275119; l=1704; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3kl4LXmb8XT+BmJFp1ldVHzPBlPIncVLnyDnPvEkf+U=; b=OUIRvNEgX4mC28YR+Lg3sgPwTO4sdyfWZs7WgYm63ie8AJiVdyBxq3nOkWtMbdnUlSjXvW1VN to8vJ7tWhJZDCNh9fljTcFCgpy9PbRI09R5iqleWDk5lgCbrZrXqRH4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sc8280xp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-s= c8280xp.c index 167470beb369..30f636b9f0ec 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3057,7 +3057,7 @@ static struct gdsc disp0_mdss_gdsc =3D { .name =3D "disp0_mdss_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct gdsc disp1_mdss_gdsc =3D { @@ -3069,7 +3069,7 @@ static struct gdsc disp1_mdss_gdsc =3D { .name =3D "disp1_mdss_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct gdsc disp0_mdss_int2_gdsc =3D { @@ -3081,7 +3081,7 @@ static struct gdsc disp0_mdss_int2_gdsc =3D { .name =3D "disp0_mdss_int2_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct gdsc disp1_mdss_int2_gdsc =3D { @@ -3093,7 +3093,7 @@ static struct gdsc disp1_mdss_int2_gdsc =3D { .name =3D "disp1_mdss_int2_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct gdsc *disp0_cc_sc8280xp_gdscs[] =3D { --- base-commit: 1e25dd7772483f477f79986d956028e9f47f990a change-id: 20230725-topic-8280_dispcc_gdsc-b1a7f3e51f3c Best regards, --=20 Konrad Dybcio