From nobody Fri Dec 19 07:48:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A990AC001DE for ; Mon, 24 Jul 2023 13:38:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231812AbjGXNi0 (ORCPT ); Mon, 24 Jul 2023 09:38:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230181AbjGXNhw (ORCPT ); Mon, 24 Jul 2023 09:37:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E13B22118 for ; Mon, 24 Jul 2023 06:36:24 -0700 (PDT) Message-ID: <20230724132047.380150373@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690205706; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=dj21GG+2OIX1Rs+wEX+47dOzfVF0PHc+KOqDglhdL7U=; b=2zBWH4Xrw/+c0Gh1+32l5LYBobo891WmCfQOIcG46JR3wKkV1NLOpbia4cyC+2Jg2iRxOm 1wgwtBp2rSXT9azwN7f0txzXVPndc5Fywa+prcZTYYwWqn3oqYaYQSpsnqwNQqGKcUlfCt v5DzRrdtF11KKx5u06FHzkcnn8S511L16TwDrVX14C5B2OE6HeGkL/EEhn4Ddrx1xn92am PTUZ5qNMEMuJKgp4o4gr8Qa/xxnUjv4K31r7ZSyvh1/JpNrEG5r/H+SB08yQ00eY2Q9sYO xcCBmw+OOjPlTnWDWhoPsakVB8ZzUBjbNNJuG+ZVPq+rXYCdyA4CfIa2GqqsIg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690205706; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=dj21GG+2OIX1Rs+wEX+47dOzfVF0PHc+KOqDglhdL7U=; b=T8H9LxnqxvhWfh4IAVSNctom+C1Qpim8d1yTuAqjACWtpGRw/OqX3WVxkikUQo4Rr/1Jqw CvusRbgG4MFchIBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross , Michael Kelley , Peter Keresztes Schmidt , "Peter Zijlstra (Intel)" Subject: [patch V2 47/58] x86/apic: Remove pointless arguments from [native_]eoi_write() References: <20230724131206.500814398@linutronix.de> MIME-Version: 1.0 Date: Mon, 24 Jul 2023 15:35:05 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Every callsite hands in the same constants which is a pointless exercise and cannot be optimized by the compiler due to the indirect calls. Use the constants in the eoi() callbacks and remove the arguments. Signed-off-by: Thomas Gleixner Reviewed-by: Wei Liu Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_apic.c | 6 +++--- arch/x86/include/asm/apic.h | 17 +++++++++++------ arch/x86/kernel/apic/apic.c | 8 ++++---- arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 3 ++- arch/x86/kernel/apic/apic_numachip.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/probe_32.c | 2 +- arch/x86/kernel/apic/x2apic_cluster.c | 2 +- arch/x86/kernel/apic/x2apic_phys.c | 2 +- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/kernel/kvm.c | 6 +++--- arch/x86/xen/apic.c | 7 ++++++- 13 files changed, 38 insertions(+), 27 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -86,14 +86,14 @@ static void hv_apic_write(u32 reg, u32 v } } =20 -static void hv_apic_eoi_write(u32 reg, u32 val) +static void hv_apic_eoi_write(void) { struct hv_vp_assist_page *hvp =3D hv_vp_assist_page[smp_processor_id()]; =20 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) return; =20 - wrmsr(HV_X64_MSR_EOI, val, 0); + wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); } =20 static bool cpu_is_self(int cpu) @@ -310,7 +310,7 @@ void __init hv_apic_init(void) * lazy EOI when available, but the same accessor works for * both xapic and x2apic because the field layout is the same. */ - apic_set_eoi_write(hv_apic_eoi_write); + apic_set_eoi_cb(hv_apic_eoi_write); if (!x2apic_enabled()) { apic->read =3D hv_apic_read; apic->write =3D hv_apic_write; --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,6 +98,11 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } =20 +static inline void native_apic_mem_eoi(void) +{ + native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); +} + extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); =20 @@ -189,7 +194,7 @@ static inline void native_apic_msr_write wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); } =20 -static inline void native_apic_msr_eoi_write(u32 reg, u32 v) +static inline void native_apic_msr_eoi(void) { __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); } @@ -250,8 +255,8 @@ struct irq_data; */ struct apic { /* Hotpath functions first */ - void (*eoi_write)(u32 reg, u32 v); - void (*native_eoi_write)(u32 reg, u32 v); + void (*eoi)(void); + void (*native_eoi)(void); void (*write)(u32 reg, u32 v); u32 (*read)(u32 reg); =20 @@ -351,7 +356,7 @@ static inline void apic_write(u32 reg, u =20 static inline void apic_eoi(void) { - apic->eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->eoi(); } =20 static inline u64 apic_icr_read(void) @@ -380,7 +385,7 @@ static inline bool apic_id_valid(u32 api return apic_id <=3D apic->max_apic_id; } =20 -extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); +extern void __init apic_set_eoi_cb(void (*eoi)(void)); =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 @@ -391,7 +396,7 @@ static inline u64 apic_icr_read(void) { static inline void apic_icr_write(u32 low, u32 high) { } static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} +static inline void apic_set_eoi_cb(void (*eoi)(void)) {} =20 #endif /* CONFIG_X86_LOCAL_APIC */ =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2502,15 +2502,15 @@ void __init acpi_wake_cpu_handler_update * interrupts disabled, so we know this does not race with actual APIC dri= ver * use. */ -void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) +void __init apic_set_eoi_cb(void (*eoi)(void)) { struct apic **drv; =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { /* Should happen once for each apic */ - WARN_ON((*drv)->eoi_write =3D=3D eoi_write); - (*drv)->native_eoi_write =3D (*drv)->eoi_write; - (*drv)->eoi_write =3D eoi_write; + WARN_ON((*drv)->eoi =3D=3D eoi); + (*drv)->native_eoi =3D (*drv)->eoi; + (*drv)->eoi =3D eoi; } } =20 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -106,7 +106,7 @@ static struct apic apic_flat __ro_after_ =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, @@ -182,7 +182,7 @@ static struct apic apic_physflat __ro_af =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -29,6 +29,7 @@ static int noop_wakeup_secondary_cpu(int static u64 noop_apic_icr_read(void) { return 0; } static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } static unsigned int noop_get_apic_id(unsigned long x) { return 0; } +static void noop_apic_eoi(void) { } =20 static u32 noop_apic_read(u32 reg) { @@ -71,7 +72,7 @@ struct apic apic_noop __ro_after_init =3D =20 .read =3D noop_apic_read, .write =3D noop_apic_write, - .eoi_write =3D noop_apic_write, + .eoi =3D noop_apic_eoi, .icr_read =3D noop_apic_icr_read, .icr_write =3D noop_apic_icr_write, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -247,7 +247,7 @@ static const struct apic apic_numachip1 =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, }; @@ -284,7 +284,7 @@ static const struct apic apic_numachip2 =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -105,7 +105,7 @@ static struct apic apic_bigsmp __ro_afte =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,7 @@ static struct apic apic_default __ro_aft =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -254,7 +254,7 @@ static struct apic apic_x2apic_cluster _ =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -169,7 +169,7 @@ static struct apic apic_x2apic_phys __ro =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -831,7 +831,7 @@ static struct apic apic_x2apic_uv_x __ro =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -332,7 +332,7 @@ static void kvm_register_steal_time(void =20 static DEFINE_PER_CPU_DECRYPTED(unsigned long, kvm_apic_eoi) =3D KVM_PV_EO= I_DISABLED; =20 -static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) +static notrace void kvm_guest_apic_eoi_write(void) { /** * This relies on __test_and_clear_bit to modify the memory @@ -343,7 +343,7 @@ static notrace void kvm_guest_apic_eoi_w */ if (__test_and_clear_bit(KVM_PV_EOI_BIT, this_cpu_ptr(&kvm_apic_eoi))) return; - apic->native_eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->native_eoi(); } =20 static void kvm_guest_cpu_init(void) @@ -825,7 +825,7 @@ static void __init kvm_guest_init(void) } =20 if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) - apic_set_eoi_write(kvm_guest_apic_eoi_write); + apic_set_eoi_cb(kvm_guest_apic_eoi_write); =20 if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -81,6 +81,11 @@ static void xen_apic_write(u32 reg, u32 WARN(1,"register: %x, value: %x\n", reg, val); } =20 +static void xen_apic_eoi(void) +{ + WARN_ON_ONCE(1); +} + static u64 xen_apic_icr_read(void) { return 0; @@ -147,7 +152,7 @@ static struct apic xen_pv_apic =3D { #endif .read =3D xen_apic_read, .write =3D xen_apic_write, - .eoi_write =3D xen_apic_write, + .eoi =3D xen_apic_eoi, =20 .icr_read =3D xen_apic_icr_read, .icr_write =3D xen_apic_icr_write,