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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:24 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [RESEND PATCH v3 11/11] mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offset Date: Mon, 24 Jul 2023 11:12:47 +0300 Message-Id: <20230724081247.4779-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6780; i=tudor.ambarus@linaro.org; h=from:subject; bh=MUJq2mMJ7nIureH4NTnSp4c0il3VTp5/1NGTZmdRv8E=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ/AjClsiJy+r+/oUJQL9lKwKRmy/640tCVi cFl1S4x6XeJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfwAKCRBLVU9HpY0U 6UyACACihYeFek6vZM2wuP6gooTVtrkuQT5Myp3MWn40rPLrLh3/dTfZyuhJl8GEDwfykX24Ecc aEj0LnTn1IGBg9q0diCEtiGkoOmcIcqdXNWpMlsC0VlifsOZ+JXS9Lc8bHVGEyTnfX8w58DaZTN yM1+opq/Tz/u3Fmn1FAM2f1UNX+9r7AgDqIRKitESVkmD/OYeoO92RbAoXJZ6WX0X5GnhzJfgFP vSk/GNok44dcUaj5RRrGXVKdvaLSiodma8LRekoOUC3gyhOyQzEq3o2QVE5Vo9NpeoLeY3bm8lb 8Kp9DGsZI+5fzj9+dleV+rAnqFJAJcN7GgpRuO/nrbCogAgr X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All users of cypress_nor_get_page_size() retrieve n_dice and vreg_offset from SFDP. Switch cypress_nor_get_page_size() to always use vreg_offset so that we use the same code base for both single and multi chip package flashes. cypress_nor_get_page_size() is now called in the post_sfdp() hook instead of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT and we now use them to get the page size in the post_sfdp hook. Consequently the null checks on n_dice and vreg_offset are moved to the post_sfdp() hook. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 105 +++++++++++++-------------------- 1 file changed, 42 insertions(+), 63 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 4027f0038ce5..0b01af33aa57 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -471,28 +471,17 @@ static int cypress_nor_set_addr_mode_nbytes(struct sp= i_nor *nor) return 0; } =20 -static int cypress_nor_get_page_size_single_chip(struct spi_nor *nor) -{ - struct spi_mem_op op =3D - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR3V, 0, - nor->bouncebuf); - int ret; - - ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) - nor->params->page_size =3D 512; - else - nor->params->page_size =3D 256; - - return 0; -} - - -static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) +/** + * cypress_nor_get_page_size() - Get flash page size configuration. + * @nor: pointer to a 'struct spi_nor' + * + * The BFPT table advertises a 512B or 256B page size depending on part bu= t the + * page size is actually configurable (with the default being 256B). Read = from + * CFR3V[4] and set the correct size. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_get_page_size(struct spi_nor *nor) { struct spi_mem_op op =3D CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, @@ -522,23 +511,6 @@ static int cypress_nor_get_page_size_mcp(struct spi_no= r *nor) return 0; } =20 -/** - * cypress_nor_get_page_size() - Get flash page size configuration. - * @nor: pointer to a 'struct spi_nor' - * - * The BFPT table advertises a 512B or 256B page size depending on part bu= t the - * page size is actually configurable (with the default being 256B). Read = from - * CFR3V[4] and set the correct size. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_get_page_size(struct spi_nor *nor) -{ - if (nor->params->n_dice) - return cypress_nor_get_page_size_mcp(nor); - return cypress_nor_get_page_size_single_chip(nor); -} - static void cypress_nor_ecc_init(struct spi_nor *nor) { /* @@ -575,20 +547,26 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, if (nor->bouncebuf[0]) return -ENODEV; =20 - return cypress_nor_get_page_size(nor); + return 0; } =20 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* PP_1_1_4_4B is supported but missing in 4BAIT. */ params->hwcaps.mask |=3D SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4); =20 - return 0; + return cypress_nor_get_page_size(nor); } =20 static int s25fs256t_late_init(struct spi_nor *nor) @@ -623,10 +601,20 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) { - struct spi_nor_erase_type *erase_type =3D - nor->params->erase_map.erase_type; + struct spi_nor_flash_parameter *params =3D nor->params; + struct spi_nor_erase_type *erase_type =3D params->erase_map.erase_type; unsigned int i; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * In some parts, 3byte erase opcodes are advertised by 4BAIT. * Convert them to 4byte erase opcodes. @@ -644,10 +632,6 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) } } =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (nor->params->size =3D=3D SZ_256M) - nor->params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -655,12 +639,6 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; params->ready =3D cypress_nor_sr_ready_and_clear; @@ -694,6 +672,17 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *n= or, bool enable) static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. @@ -719,10 +708,6 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) */ params->rdsr_addr_nbytes =3D 4; =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (params->size =3D=3D SZ_256M) - params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -737,12 +722,6 @@ static int s28hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - params->set_octal_dtr =3D cypress_nor_set_octal_dtr; params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); --=20 2.34.1