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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:12:53 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 01/11] mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR Date: Mon, 24 Jul 2023 11:12:37 +0300 Message-Id: <20230724081247.4779-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15492; i=tudor.ambarus@linaro.org; h=from:subject; bh=abt/KuEBLk/2uHPj4mik4XS7fR2pRwv3tmtN9KYUxeY=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+vmmbTvWhjt87EjyA0hTvCArKszPFUvy7G 1BYCiNskOSJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6cY3CACZuruFa311/QPGrZZwn9YrxcvKJ8spaayw5PVRxXR5J52ryfkOCUza+eAHamcdCp6osuD +FUaji9DDsqVOD+8SLjwiD1DBhxNpwfsGd+vn6iW85mP37li7AoQ6EQuCBLJJ91hRgzNapYRr89 ZH+IAXBChSmOYd9k1mWqFOtNddFUD2z4H51gpZuoUh135zelfl25vA0G91WaSN8C2BeHW6OpA9c XSQAHCqEnsgCe516Lp+0KV8+Cryev9lMcOUZs7ZewZ/BIKNqv9Ii21RHygoUq7fx8vQyxuak7QB +DF3nqQPFuBUeeAgD1bLJXpGMm9WKaer4si9dGki3Wcv4JkY X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/atmel.c | 8 +++- drivers/mtd/spi-nor/core.c | 23 +++++++---- drivers/mtd/spi-nor/core.h | 4 +- drivers/mtd/spi-nor/issi.c | 4 +- drivers/mtd/spi-nor/macronix.c | 4 +- drivers/mtd/spi-nor/micron-st.c | 4 +- drivers/mtd/spi-nor/spansion.c | 72 ++++++++++++++++++++++++++------- drivers/mtd/spi-nor/sst.c | 8 +++- drivers/mtd/spi-nor/winbond.c | 4 +- drivers/mtd/spi-nor/xilinx.c | 4 +- 10 files changed, 103 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 656dd80a0be7..58968c1e7d2f 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -48,9 +48,11 @@ static const struct spi_nor_locking_ops at25fs_nor_locki= ng_ops =3D { .is_locked =3D at25fs_nor_is_locked, }; =20 -static void at25fs_nor_late_init(struct spi_nor *nor) +static int at25fs_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &at25fs_nor_locking_ops; + + return 0; } =20 static const struct spi_nor_fixups at25fs_nor_fixups =3D { @@ -149,9 +151,11 @@ static const struct spi_nor_locking_ops atmel_nor_glob= al_protection_ops =3D { .is_locked =3D atmel_nor_is_global_protected, }; =20 -static void atmel_nor_global_protection_late_init(struct spi_nor *nor) +static int atmel_nor_global_protection_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &atmel_nor_global_protection_ops; + + return 0; } =20 static const struct spi_nor_fixups atmel_nor_global_protection_fixups =3D { diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 273258f7e77f..614960c7d22c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2900,16 +2900,23 @@ static void spi_nor_init_fixup_flags(struct spi_nor= *nor) * SFDP standard, or where SFDP tables are not defined at all. * Will replace the spi_nor_manufacturer_init_params() method. */ -static void spi_nor_late_init_params(struct spi_nor *nor) +static int spi_nor_late_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; + int ret; =20 if (nor->manufacturer && nor->manufacturer->fixups && - nor->manufacturer->fixups->late_init) - nor->manufacturer->fixups->late_init(nor); + nor->manufacturer->fixups->late_init) { + ret =3D nor->manufacturer->fixups->late_init(nor); + if (ret) + return ret; + } =20 - if (nor->info->fixups && nor->info->fixups->late_init) - nor->info->fixups->late_init(nor); + if (nor->info->fixups && nor->info->fixups->late_init) { + ret =3D nor->info->fixups->late_init(nor); + if (ret) + return ret; + } =20 /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) @@ -2927,6 +2934,8 @@ static void spi_nor_late_init_params(struct spi_nor *= nor) =20 if (nor->info->n_banks > 1) params->bank_size =3D div64_u64(params->size, nor->info->n_banks); + + return 0; } =20 /** @@ -3085,9 +3094,7 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } =20 - spi_nor_late_init_params(nor); - - return 0; + return spi_nor_late_init_params(nor); } =20 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f2fc2cf78e55..9217379b9cfe 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -378,6 +378,7 @@ struct spi_nor_otp { * than reading the status register to indicate they * are ready for a new command * @locking_ops: SPI NOR locking methods. + * @priv: flash's private data. */ struct spi_nor_flash_parameter { u64 bank_size; @@ -406,6 +407,7 @@ struct spi_nor_flash_parameter { int (*ready)(struct spi_nor *nor); =20 const struct spi_nor_locking_ops *locking_ops; + void *priv; }; =20 /** @@ -432,7 +434,7 @@ struct spi_nor_fixups { const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); int (*post_sfdp)(struct spi_nor *nor); - void (*late_init)(struct spi_nor *nor); + int (*late_init)(struct spi_nor *nor); }; =20 /** diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 400e2b42f45a..accdf7aa2bfd 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,7 +29,7 @@ static const struct spi_nor_fixups is25lp256_fixups =3D { .post_bfpt =3D is25lp256_post_bfpt_fixups, }; =20 -static void pm25lv_nor_late_init(struct spi_nor *nor) +static int pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map =3D &nor->params->erase_map; int i; @@ -38,6 +38,8 @@ static void pm25lv_nor_late_init(struct spi_nor *nor) for (i =3D 0; i < SNOR_ERASE_TYPE_MAX; i++) if (map->erase_type[i].size =3D=3D 4096) map->erase_type[i].opcode =3D SPINOR_OP_BE_4K_PMC; + + return 0; } =20 static const struct spi_nor_fixups pm25lv_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 04888258e891..eb149e517c1f 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -110,10 +110,12 @@ static void macronix_nor_default_init(struct spi_nor = *nor) nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; } =20 -static void macronix_nor_late_init(struct spi_nor *nor) +static int macronix_nor_late_init(struct spi_nor *nor) { if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; + + return 0; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index f79e71d99124..6ad080c52ab5 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -429,7 +429,7 @@ static void micron_st_nor_default_init(struct spi_nor *= nor) nor->params->quad_enable =3D NULL; } =20 -static void micron_st_nor_late_init(struct spi_nor *nor) +static int micron_st_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -438,6 +438,8 @@ static void micron_st_nor_late_init(struct spi_nor *nor) =20 if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex= 4b; + + return 0; } =20 static const struct spi_nor_fixups micron_st_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 314667d4b8a8..6b2532ed053c 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,14 +4,17 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ =20 +#include #include =20 #include "core.h" =20 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ #define USE_CLSR BIT(0) +#define USE_CLPEF BIT(1) =20 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -57,22 +60,32 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(1, buf, 0)) =20 -#define SPANSION_CLSR_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ +#define SPANSION_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 +/** + * struct spansion_nor_params - Spansion private parameters. + * @clsr: Clear Status Register or Clear Program and Erase Failure Flag + * opcode. + */ +struct spansion_nor_params { + u8 clsr; +}; + /** * spansion_nor_clear_sr() - Clear the Status Register. * @nor: pointer to 'struct spi_nor'. */ static void spansion_nor_clear_sr(struct spi_nor *nor) { + const struct spansion_nor_params *priv_params =3D nor->params->priv; int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPANSION_CLSR_OP; + struct spi_mem_op op =3D SPANSION_OP(priv_params->clsr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -528,9 +541,11 @@ static int s25fs256t_post_sfdp_fixup(struct spi_nor *n= or) return 0; } =20 -static void s25fs256t_late_init(struct spi_nor *nor) +static int s25fs256t_late_init(struct spi_nor *nor) { cypress_nor_ecc_init(nor); + + return 0; } =20 static struct spi_nor_fixups s25fs256t_fixups =3D { @@ -586,7 +601,7 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) return cypress_nor_get_page_size(nor); } =20 -static void s25hx_t_late_init(struct spi_nor *nor) +static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -598,6 +613,8 @@ static void s25hx_t_late_init(struct spi_nor *nor) /* Replace ready() with multi die version */ if (params->n_dice) params->ready =3D cypress_nor_sr_ready_and_clear; + + return 0; } =20 static struct spi_nor_fixups s25hx_t_fixups =3D { @@ -659,10 +676,12 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *no= r, return cypress_nor_set_addr_mode_nbytes(nor); } =20 -static void s28hx_t_late_init(struct spi_nor *nor) +static int s28hx_t_late_init(struct spi_nor *nor) { nor->params->set_octal_dtr =3D cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); + + return 0; } =20 static const struct spi_nor_fixups s28hx_t_fixups =3D { @@ -786,47 +805,54 @@ static const struct flash_info spansion_nor_parts[] = =3D { FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25fs256t_fixups }, { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, }; @@ -870,17 +896,35 @@ static int spansion_nor_sr_ready_and_clear(struct spi= _nor *nor) return !(nor->bouncebuf[0] & SR_WIP); } =20 -static void spansion_nor_late_init(struct spi_nor *nor) +static int spansion_nor_late_init(struct spi_nor *nor) { - if (nor->params->size > SZ_16M) { + struct spi_nor_flash_parameter *params =3D nor->params; + struct spansion_nor_params *priv_params; + u8 mfr_flags =3D nor->info->mfr_flags; + + if (params->size > SZ_16M) { nor->flags |=3D SNOR_F_4B_OPCODES; /* No small sector erase for 4-byte command set */ nor->erase_opcode =3D SPINOR_OP_SE; nor->mtd.erasesize =3D nor->info->sector_size; } =20 - if (nor->info->mfr_flags & USE_CLSR) - nor->params->ready =3D spansion_nor_sr_ready_and_clear; + if (mfr_flags & (USE_CLSR | USE_CLPEF)) { + priv_params =3D devm_kmalloc(nor->dev, sizeof(*priv_params), + GFP_KERNEL); + if (!priv_params) + return -ENOMEM; + + if (mfr_flags & USE_CLSR) + priv_params->clsr =3D SPINOR_OP_CLSR; + else if (mfr_flags & USE_CLPEF) + priv_params->clsr =3D SPINOR_OP_CLPEF; + + params->priv =3D priv_params; + params->ready =3D spansion_nor_sr_ready_and_clear; + } + + return 0; } =20 static const struct spi_nor_fixups spansion_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 688eb20c763e..09fdc7023e09 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -49,9 +49,11 @@ static const struct spi_nor_locking_ops sst26vf_nor_lock= ing_ops =3D { .is_locked =3D sst26vf_nor_is_locked, }; =20 -static void sst26vf_nor_late_init(struct spi_nor *nor) +static int sst26vf_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops =3D &sst26vf_nor_locking_ops; + + return 0; } =20 static const struct spi_nor_fixups sst26vf_nor_fixups =3D { @@ -203,10 +205,12 @@ static int sst_nor_write(struct mtd_info *mtd, loff_t= to, size_t len, return ret; } =20 -static void sst_nor_late_init(struct spi_nor *nor) +static int sst_nor_late_init(struct spi_nor *nor) { if (nor->info->mfr_flags & SST_WRITE) nor->mtd._write =3D sst_nor_write; + + return 0; } =20 static const struct spi_nor_fixups sst_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 63ba8e3a96f5..cd99c9a1c568 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -217,7 +217,7 @@ static const struct spi_nor_otp_ops winbond_nor_otp_ops= =3D { .is_locked =3D spi_nor_otp_is_locked_sr2, }; =20 -static void winbond_nor_late_init(struct spi_nor *nor) +static int winbond_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 @@ -233,6 +233,8 @@ static void winbond_nor_late_init(struct spi_nor *nor) * from BFPT, if any. */ params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; + + return 0; } =20 static const struct spi_nor_fixups winbond_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 7175de8aa336..00d53eae5ee8 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -155,10 +155,12 @@ static int xilinx_nor_setup(struct spi_nor *nor, return 0; } =20 -static void xilinx_nor_late_init(struct spi_nor *nor) +static int xilinx_nor_late_init(struct spi_nor *nor) { nor->params->setup =3D xilinx_nor_setup; nor->params->ready =3D xilinx_nor_sr_ready; + + return 0; } =20 static const struct spi_nor_fixups xilinx_nor_fixups =3D { --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E573C001B0 for ; Mon, 24 Jul 2023 08:13:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231410AbjGXINE (ORCPT ); Mon, 24 Jul 2023 04:13:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230232AbjGXIM7 (ORCPT ); Mon, 24 Jul 2023 04:12:59 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DC17115 for ; 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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:12:56 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano , stable@vger.kernel.org Subject: [RESEND PATCH v3 02/11] mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT Date: Mon, 24 Jul 2023 11:12:38 +0300 Message-Id: <20230724081247.4779-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1944; i=tudor.ambarus@linaro.org; h=from:subject; bh=kVZ7aQId7ERSbIGrhSxOKuGFZinAOtskWkM0179Q9K8=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+SIacWrtM6rqggQL3xW9NW3MgQizA9VFwu e+IRxfckVyJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6fIXB/4sxp2lHpr0bsLJOluiR+54Ai3rZFme+Z0Pca5oGlc2cJN4GcjbS3uuNnLbr7tfVFoByji wShomDl6y/CbrxwQzxMake0uet1egUDKMWMu2yTRNbwRE4ljVUgMEF9xh1WpId9T4CkC+CJ5pc0 FXWgZLt/0PjOw5XX+xjohQBXJ21y+U+C+2XPZJwkY+5Vh9uPkmc2qz6KrFOrpemfQRKYB/bWxsO I1IF9O5SU2xNxx1wJIL4/1HQISx1JFwpwJlzQnL51sa1tgg785Vx3zE4n7KJiy9VI+xADeSsD+u WUTXjxqujyuVPa5dvmLNFofEraQia4pr0HXRWfdH/DGgiR20 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read, update, write back fashion. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Sempe= r flash") Signed-off-by: Takahiro Kuwano Cc: stable@vger.kernel.org --- drivers/mtd/spi-nor/spansion.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6b2532ed053c..6460d2247bdf 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ =20 +#include #include #include =20 @@ -28,6 +29,7 @@ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 @@ -161,8 +163,18 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *no= r) int ret; u8 addr_mode_nbytes =3D nor->params->addr_mode_nbytes; =20 + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, + SPINOR_REG_CYPRESS_CFR2V, 0, buf); + + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + /* Use 24 dummy cycles for memory array reads. */ - *buf =3D SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; + *buf &=3D ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; + *buf |=3D FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, + SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op =3D (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR2V, 1, buf); --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66B3AC001B0 for ; Mon, 24 Jul 2023 08:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230427AbjGXINN (ORCPT ); Mon, 24 Jul 2023 04:13:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231397AbjGXINC (ORCPT ); Mon, 24 Jul 2023 04:13:02 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 929E712E for ; Mon, 24 Jul 2023 01:13:00 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-993d1f899d7so717963966b.2 for ; Mon, 24 Jul 2023 01:13:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186379; x=1690791179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eOW1ZpE6/v2ajQK+LnlqMKJQMOzTE7yoF7vscLDu6Gs=; b=JDj+wnF8yQouCVrrQKETHEvvp6b3VpVDNs5K5tqUgWfGuih0tmOk83JGe9at5g06wr XkgzGrDO83Gaw4+TRv84K2Dw1a7drN/HMLi8Xsb+2/p9xWcBKKcqMIy8PFdgK1nPmKDx EEPKdf9xhYBO6pR5AFAUJIjbVKUQAYdYP3kfT2LqjwVRduK44LCHCsbOQhrQ/cYvktMq 58hIG5EFzx+XpJpaWVuT6hqPYu0cyy/1SLjyp+SFxoJWDaNWqGoEfjahm48hO9k+icjx 6q6ncxxmhF3DZs6InQ8wGWSv4WvV9Mr348wWJ4N3UT3ADWO9wo0uDX5kiVGoj04ekxgb DhYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186379; x=1690791179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eOW1ZpE6/v2ajQK+LnlqMKJQMOzTE7yoF7vscLDu6Gs=; b=RacgcEjlo4X+NhOhrfr9kng32uMwgakM6ydQoVDGfPS49r/oqB/uQdmP0oAkjaLCEE TEpyiOyhpvBgL+7PQmgB7BXn1NqWuZC1/6FlTR2MCngtDAFJW8ArEgwxCVVkhzdcaD0x GtKrWsbmuJB775nakB0PdctAGKiTxtOuM3m/q7y0C0iIqRNdj3GLvgdmD2Vu3C4V1Mbm JdL/5ry21ifsOGtK+ICTbNYxmMJhtXsIoKSkCsDNTD2ooC9CSJ9Sxtnr/ZF1+8EsQDNC JwdSxk2eAQV/0UxGUXBN0Hc7LpTJAjJcmAvC0wp+OqYLSeAcBWTkb0Vz9CdBPbw+f22R Hwfg== X-Gm-Message-State: ABy/qLaA24l/U+3ezC1xh2RBNg0EWvO2J988ZoZyyz2pkYfDvf2HRCuj 6lBWpdIX3+iIRM0OAfKzNbX25Q== X-Google-Smtp-Source: APBJJlF5DN5lXH8fTejLZtW8eJla8OQDmeW6ZRpLHgk8ob9ppkwAXRuwapkwP5Cr6qktk0vTBm5dJw== X-Received: by 2002:a17:906:20c6:b0:96f:1f79:c0a6 with SMTP id c6-20020a17090620c600b0096f1f79c0a6mr8864498ejc.70.1690186379120; Mon, 24 Jul 2023 01:12:59 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:12:58 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 03/11] mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support Date: Mon, 24 Jul 2023 11:12:39 +0300 Message-Id: <20230724081247.4779-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3820; i=tudor.ambarus@linaro.org; h=from:subject; bh=xpyv1UNUOm+7WUBWb0Vl59R+HvbIVKf4klrF0ttDcrA=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+cL1Tyl84sNIYkyBfq2rFtCaH7yjWfYS7u dc1OqqEJMiJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6bwwCACZMu+rPl8e8uNTwrWcuFUGYQBaS9XZuG8XIKvziwOQI07kaK1F2tHjzDhOExyHcrKTmDS kKUJNHHnxz2RbevGYR1sjJJyGVtdEN7yvFBxZrBQ9maIOFg0SJowEtnANesQRaBLMs8Qjxyv7ho KRNkkU/G6mF1R6QnFVMIezeiFEqZCIT7o+GQGWQATpz/pUOMZuiw91p8h915Kw/kXxBv99m8VXo aXUZwXMqiBf/EEYLr0Fg2s7mNI9/yoSiNVUIgDekgIwwriQbp/2mP6H6NeTCI/ztKGH+Ddqkd9w 7rSJ3kAHilhWRbiNySha+9gSBrvmWbhxq2/YTGvsT5V77GZx X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon's multi-chip package (MCP) devices require the octal DTR configuration to be set for each die. Split common code in dedicated methods to ease the octal DDR MCP support addition. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6460d2247bdf..51eabddf2b16 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_no= r *nor) return 1; } =20 -static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; @@ -164,8 +164,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) u8 addr_mode_nbytes =3D nor->params->addr_mode_nbytes; =20 op =3D (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 0, buf); + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); =20 ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) @@ -176,8 +175,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) *buf |=3D FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); =20 ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) @@ -185,13 +183,33 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) =20 nor->read_dummy =3D 24; =20 + return 0; +} + +static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + /* Set the octal and DTR enable bits. */ buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, + addr, 1, buf); =20 - ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); +} + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + if (ret) + return ret; + + ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 @@ -209,11 +227,10 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) return 0; } =20 -static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; - int ret; =20 /* * The register is 1-byte wide, but 1-byte transactions are not allowed @@ -223,9 +240,16 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *n= or) buf[0] =3D SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] =3D 0; op =3D (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 2, buf); - ret =3D spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); + return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); +} + +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + u8 *buf =3D nor->bouncebuf; + int ret; + + ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; =20 --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB087C001DF for ; Mon, 24 Jul 2023 08:13:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231159AbjGXINR (ORCPT ); Mon, 24 Jul 2023 04:13:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbjGXINL (ORCPT ); Mon, 24 Jul 2023 04:13:11 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 944E31BF for ; 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([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:00 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 04/11] mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset Date: Mon, 24 Jul 2023 11:12:40 +0300 Message-Id: <20230724081247.4779-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2594; i=tudor.ambarus@linaro.org; h=from:subject; bh=kgTcomoQU7JsYNjD2ojxcF6vrGgWFcnW4j+zTTO9fWg=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+F1McRGWHDR/dosXymqrH8LFtXFXqWHGWg YCEuhu05uqJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6THrB/9hGcQ+dUFmN1EHMfc9PNt80BWHmBTNhdkusNicxLfEwfliKYVTpYiOuZlHUzBmLCAkCff xIqfJb9TryAKIA+tr1YQjaVCRdlHoB+rqDf1R0mpU5vEN5VI/jtjgV9gr62Di1m9D/AdsY/0HhG OsNOIVhYQSHXQ1R2IehWb9T7ntb5CJmPDNP/PezvC1U9bBqneaSgYfBuJsjFjV7SMdrbChMghSl RbtbnsvYdVjE1we9rdOwglgQM1Ia1Zx6hT8nn3T0ssebFiQei6ILrueLwV+xN8EOCOEMN0JpMbl e2bH9KS+8auJq/Yh5hBMp42eaNMy8XmxTgiSLn9/guMiar1S X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano All the Infineon flashes that currently support octal DTR mode define the optional SCCR SFDP table, thus all retrieve vreg_offset. Switch all the available octal DTR Infineon flashes to use the volatile register offset to set the configuration registers. The goal is to have a single pair of methods for both single/multi-chip package devices. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 51eabddf2b16..dc4841891b74 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "core.h" @@ -202,14 +203,18 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_= nor *nor, u64 addr) =20 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; + ret =3D cypress_nor_set_memlat(nor, addr); if (ret) return ret; =20 - ret =3D cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); if (ret) return ret; =20 @@ -247,9 +252,11 @@ static int cypress_nor_set_single_spi_bits(struct spi_= nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { u8 *buf =3D nor->bouncebuf; + u64 addr; int ret; =20 - ret =3D cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr =3D nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_single_spi_bits(nor, addr); if (ret) return ret; =20 @@ -714,7 +721,15 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s28hx_t_late_init(struct spi_nor *nor) { - nor->params->set_octal_dtr =3D cypress_nor_set_octal_dtr; + struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + params->set_octal_dtr =3D cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); =20 return 0; --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51C0AC001DE for ; Mon, 24 Jul 2023 08:13:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231447AbjGXINg (ORCPT ); Mon, 24 Jul 2023 04:13:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231441AbjGXINO (ORCPT ); Mon, 24 Jul 2023 04:13:14 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 072E7E79 for ; Mon, 24 Jul 2023 01:13:06 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-51e56749750so5769678a12.0 for ; Mon, 24 Jul 2023 01:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186385; x=1690791185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hQWD6o2QmQMIWADk9Uuk1r2hOrPJzs9WMOrl4s2UcP4=; b=TOspIZRVdxW+KctBUpzedxlrRyCBWoiE4/Y43E0WszgR4uL2m5kri2Cm2crujjE6Xb WaSPPQtb1VI0KIWu/JaMHAkE7gb7FGnMCx67INEINzHhzclnBur3wAUsulYwFNKcn7Q3 0/p18ZUYciCIvQ3FnOns88/A9p05Ge/RbDlv+q1Wro9a8e/CHIkmZTvH6RcZpV2+omoW r+3lDpi2DGk9Gb6p0MbFYDKcMFz9nTV1zG/cgDZxQeXTGSiryM2V3ZdW91UVWi4Yyoai ja1nPqz0gWTsQjKMapq8LYWVAskMTc8VtmZ5RdD2tHqyJjO6gGpmzUg32UFABSHXhkxO xmKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186385; x=1690791185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hQWD6o2QmQMIWADk9Uuk1r2hOrPJzs9WMOrl4s2UcP4=; b=Qlj/UUSSJs0Z4FHizCpCdOw6uci3u7CGh3jUAN9SQx8sJ24yfmALjbl7T0n3edWyde tde3IlS2Lu7CdvmbLXohuvgLV08MsH0YJBGfMdB+Q5pNFqd8k3KP9qDQTH5PU0/zFJ5F MKOxhLQM5Gc5RkUvvse/uG7EU7dJfQeWB1nFfY7GPH59G3qODlQ9Qy1wjIj+dC8at2Vj VPIwYHfyBLKYh0+SvfPpm2TmzZDNGui61w8s2mHC4rcol8C6j7X8N9PnFqcqKxUSKF+D i9hSQVV+ZitviVmbkU3DtWpsatcGFFxoPreUb7m/098EbhJ4Jq12vCbjfJ6ONy2zFe1u u7CA== X-Gm-Message-State: ABy/qLZNkecBXEDQTFOy/M/t+fe9+ivbfpSXD91KgLTpoN+Ddh6MYWwX xFPBdhakyMBhoX6ruN9One1Xow== X-Google-Smtp-Source: APBJJlEMJswmOKOAqJzwRQ5aFVr0jQaI5nq1DEVa4URq69sVkBeRtwC3r2KBUvBj511T9cXfd5lwiw== X-Received: by 2002:a17:906:cc0e:b0:99b:4a29:fb6a with SMTP id ml14-20020a170906cc0e00b0099b4a29fb6amr9268494ejb.59.1690186385224; Mon, 24 Jul 2023 01:13:05 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:03 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 05/11] mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset Date: Mon, 24 Jul 2023 11:12:41 +0300 Message-Id: <20230724081247.4779-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=851; i=tudor.ambarus@linaro.org; h=from:subject; bh=WVFbE2wfxt/8hLhyWshKgP+KuZXcvV9Z2hzSYAD/Z5w=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+ywSNb/VFIiWHMUEXC6o5GvL5YbM7I7q4J IEexIEmBVOJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6eJNB/4+GW3Up54GTrKVZ3mORH/AXQ4goiqFedFcFMq5+rzCmlhsMNZMPtCayF3XYjkYioQePJ6 t77LMQ6vU0lhJhZc+cFFAajMT/KRpl2rL1CCBRmGsYBGupKFjEt2/kx1995y3vclQwGOo5QEHZi LzOeN3QfUMJvfQkJKkPPUuTyFtZO+on+ZxG1pTb/v8+vmNUMW8VfRIFtDTsBntBJEUOvH5bBfqs sKiuaOD6DyQgiaMfeCg06P86hkgmF6vvdz8JwsfcZf8cyJClhHeGzRrerrRsK+T8bqfBVwEdMqZ zpFUiN5MiLajo+IXlGncp/ROz/y4mMixiUOQ4iyvbDhb37il X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano s28hx is the sole user of cypress_nor_set_octal_dtr, which already uses vreg_offset to set octal DTR. Switch the ready method to use vreg_offset as well. This is a preparation patch. The goal is to use the same s28hx methods for the multi die version of the flash. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index dc4841891b74..5b6f36b56e9f 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -730,6 +730,7 @@ static int s28hx_t_late_init(struct spi_nor *nor) } =20 params->set_octal_dtr =3D cypress_nor_set_octal_dtr; + params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 return 0; --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9788C001DE for ; Mon, 24 Jul 2023 08:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231512AbjGXINm (ORCPT ); Mon, 24 Jul 2023 04:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231429AbjGXIN0 (ORCPT ); Mon, 24 Jul 2023 04:13:26 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D39E110DC for ; Mon, 24 Jul 2023 01:13:09 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-9891c73e0fbso849854966b.1 for ; Mon, 24 Jul 2023 01:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186387; x=1690791187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0zR/M8U1wHDKNH5FK18SqWQfcxUTegtHbVe9hHuhxRk=; b=gSFQ/HpK5N6H/8kytfRh2+IX2a3eYAbeGHw5wmyZ/Q4cegnjB7xhpYXGDLuZRjRA5X fsH3lktwBPTPkQQhnj508dZGvPlzSF3WqdRXM1IwjnuW/azppW2sJiLQeaGywEl7rX0C HpobsrPlf/jbuwR7c43IgxGuiT5ExiQRMevZxhnrdRTBxuKbE6FM8LueSHyNsATzxahX 3x0IlzZfeMPVJQ9CdVH6gOxGmFs6+URZGyAitNvAMrgMUuMVL31Nkl75IYeB+8EjizNM vdHk2Ra4FRfqZH4rUbSOD7h/NeA/1Z4FGhD6XniVXhWCZSwlMPaCvdArYZrQo2m+i2bZ 9CHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186387; x=1690791187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0zR/M8U1wHDKNH5FK18SqWQfcxUTegtHbVe9hHuhxRk=; b=eutg8aObJPfQXcJ2ndBW02+FRQBcBy/lrbasrKxSg9/yn0zWyBekOmMoSxMul76aNT WEHMksbR8Ia2+XcZVL9ExF5dInOh4fYsb8RVUtkIEY0PSgP5I7coFy479vq96ViSfqMe ECrN06VQCSW5aQxTaY8iAy7r+YV+lXcX5eNSefbr8gXSV7zibOgkxJITorAkZoiz3HWP J6muf6hTV5DMrFG4fYimNJYKQm2oDkuUNYBiKY/8Ct4UrlmUb3vQtGfN+GbnjEMtwxaZ tPA3uNxAyuMsPMgU64884NxMEsSTvL6SKiDJmGSnuZ7Omp++MCdQb90nENn8qdpKDAr9 wz6w== X-Gm-Message-State: ABy/qLbdeuWsTWB4QQg9jPhcAWcIzUaIkr76kjViJIO8Q9pdl+HIBGMQ SZVN8zHZWP6DayUnreXftGNOrw== X-Google-Smtp-Source: APBJJlF2heJfl8MQDDlm7U5LJn0RmLJ7fM7Slrql6tkji5QwnlxEqIZI61hThIeekB1eqyZykKJMrw== X-Received: by 2002:a17:907:75e2:b0:99b:4bab:2841 with SMTP id jz2-20020a17090775e200b0099b4bab2841mr9525489ejc.26.1690186387421; Mon, 24 Jul 2023 01:13:07 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:06 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 06/11] mtd: spi-nor: spansion: add MCP support in set_octal_dtr() Date: Mon, 24 Jul 2023 11:12:42 +0300 Message-Id: <20230724081247.4779-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2370; i=tudor.ambarus@linaro.org; h=from:subject; bh=Wrd7TgCxXlMqnk/UDwQEgLVdRWdaYJRKC05Rf/3Xxx0=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+6rh7ujEX5KOJrzAwohHe3MP6fhRRPEZAn HCFY1KuZRqJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6bOzB/9ghK8NGTdi3IxM8Df5fdqtBbV5rzTB4CsDwL1WCLfQ09LY+dMOZpq3FoZpgwYwi3O/9Co nC4s1mzWjdxGCrY5XXgEUwu06zIvJqn4uhHm1frKCOByHs2LuvDh4BHsjnEXeaPzaJCf8o4xOcV 3VKswMoEvYd51FNnzQognRKtxlTr+2hAf7tqRciVUWQjk/MqfXM4011rfGRKXc1WLdgrNN+N9FQ QY++8UKrFkpJ1UifZoresZHuZUStoqYfGdZKY1Ar+s+0wgCg9Ib3yu/A/c2mRfQYW6b6l++2PrT PMYrBuwSBbfSoUceEHPA0ubhdk3drrFXomwplP/ggMXQDwf+ X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Infineon multi-chip package (MCP) devices require the Octal DTR configuraion to be set on each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] populated from SFDP. Add MCP support in set_octal_dtr(). Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 5b6f36b56e9f..28d0a995f3b9 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -206,17 +206,19 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *n= or) const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; u64 addr; - int ret; + int i, ret; =20 - addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; - ret =3D cypress_nor_set_memlat(nor, addr); - if (ret) - return ret; + for (i =3D 0; i < params->n_dice; i++) { + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; + ret =3D cypress_nor_set_memlat(nor, addr); + if (ret) + return ret; =20 - addr =3D params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); - if (ret) - return ret; + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_octal_dtr_bits(nor, addr); + if (ret) + return ret; + } =20 /* Read flash ID to make sure the switch was successful. */ ret =3D spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, @@ -251,14 +253,17 @@ static int cypress_nor_set_single_spi_bits(struct spi= _nor *nor, u64 addr) =20 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params =3D nor->params; u8 *buf =3D nor->bouncebuf; u64 addr; - int ret; + int i, ret; =20 - addr =3D nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret =3D cypress_nor_set_single_spi_bits(nor, addr); - if (ret) - return ret; + for (i =3D 0; i < params->n_dice; i++) { + addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret =3D cypress_nor_set_single_spi_bits(nor, addr); + if (ret) + return ret; + } =20 /* Read flash ID to make sure the switch was successful. */ ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94317C001B0 for ; Mon, 24 Jul 2023 08:13:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbjGXIN5 (ORCPT ); Mon, 24 Jul 2023 04:13:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbjGXINb (ORCPT ); Mon, 24 Jul 2023 04:13:31 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FFEF1705 for ; Mon, 24 Jul 2023 01:13:13 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-992e22c09edso596709766b.2 for ; Mon, 24 Jul 2023 01:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186391; x=1690791191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RkHM3RFGQ0WIr5v2TWHAHkTdJrhHVucyrUvsad9WfOo=; b=deuRTZstRG4cjvLu+clvj8bi6F+b/ABQ00rFEdb/nZpASZp4DaGZWenjE4cGdrRm4M 9htdKtMmA21QkObKsHHKINz2Oi0+UZDHkq02z0kM8zRu/LXF64qf6r/ISUdS0H5W9Zom QV0nxQycoAYQIcYpFqow0Szavf7JSW2OYa9OnlOjWcaAeeKv6deuP29rLjFcNs0acE8Q Zyhriv5zVWhdoaBXowGFJZSdRbmfvR5rtT2u3fNdq+g8PsopZCOxY/6I5c7SPZLEAgkt U09FFJzvp2lnk73nmBPpG4uD5VU3bvLaPjLdG7M8ghECJKRpGNsYy++jqaBtoDJQCpOu VnnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186391; x=1690791191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RkHM3RFGQ0WIr5v2TWHAHkTdJrhHVucyrUvsad9WfOo=; b=DephssKUAabpGaTe1D9fu866wHYos+t7izLhIM6Sn9OS3IyrAxzYtArwbmIJIL/33u ACjVcT+l3GzJBC167MpMaHFRQLAQNdjdW4lYUAMO1Haa1FBfxFLjVFmlSPmsCZYGJMNu XLpoD6r1IhWwfRh6j8zMIwDna7sROTIbKjF914R6HGGNf+j3kC6qgL1b5123/RSziNHa ExqrS4kbcvRBsr44CHPqs3i3QAfkpyfiffCiia/bDr6jF4XJVdurqUJLKIdinYE9agkC elPeckz2XAPPuT4GPCTwjCGLOnDKVObjifZccjoMLMDRTxP5BEwUtbE/LUwymbDEnbqO LHTw== X-Gm-Message-State: ABy/qLZwpe/D+OOR01uM91u5F3dbTUVhMznlW24C1r2J2acPbbOnUDbb GYQsWJZ+4hxH48vSVcrG57VwVg== X-Google-Smtp-Source: APBJJlHSxOp0xPKToV9ONheJ//o5w9GLr/jPtmw5rrpfHCOWAJ13ocXV1lLD8LOrgl9iQBS3bEGs4w== X-Received: by 2002:a17:906:31d3:b0:993:f90b:e549 with SMTP id f19-20020a17090631d300b00993f90be549mr8877382ejf.37.1690186391119; Mon, 24 Jul 2023 01:13:11 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:08 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano Subject: [RESEND PATCH v3 07/11] mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP Date: Mon, 24 Jul 2023 11:12:43 +0300 Message-Id: <20230724081247.4779-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1173; i=tudor.ambarus@linaro.org; h=from:subject; bh=ARtE+Fv/l4a+BkMfBrTfq2ov79VZLg+i8bYbcphxQmM=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+bqmEDqHMfs1PJlBNahV34jcDlLvGaPX+Z cKEiovvOcyJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6ed+CACMM3slBgYr2/UDm63/4pQWiMj1acdFTz6d2k3eD13QyQClOeGJIqfqwPCSfGWO94K8CAh h7DmAjYFrttVS6/Lb5HLhPkhtEY0holI46g6IRpyvipqRcdTK8hf7nQPejfO49PuwfnCosiEUzu zLJ2tBN5s3OUsZauWrCmBeC3Wpp4P6DIGfDQ4N5vxuwwAa4EFLvrRGHB7XzmK52llClTWmxDSmB 0IILcuxRBw9mqRytpVm+RGKB+cJg7WrDFkroIA43qvK7PVLJ20c5iLUJp7T1UVqy48Sz+zftLtI nh6dFLVBmFWwrHZVEQWZhiUbgkscQIdx8i9dARJ1bfXnrXdo X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano S28HS02GT uses RD_ANY_REG_OP to read status of each die. In Octal DTR mode, RD_ANY_REG_OP needs dummy cycles (same as params->rdsr_dummy) and data length should be 2. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 28d0a995f3b9..2fc3e65686b3 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -104,11 +104,17 @@ static void spansion_nor_clear_sr(struct spi_nor *nor) =20 static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 add= r) { + struct spi_nor_flash_parameter *params =3D nor->params; struct spi_mem_op op =3D - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, addr, + CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, 0, nor->bouncebuf); int ret; =20 + if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { + op.dummy.nbytes =3D params->rdsr_dummy; + op.data.nbytes =3D 2; + } + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) return ret; --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68C5BC001B0 for ; Mon, 24 Jul 2023 08:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231408AbjGXIOK (ORCPT ); Mon, 24 Jul 2023 04:14:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231497AbjGXINk (ORCPT ); Mon, 24 Jul 2023 04:13:40 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC6C5171E for ; Mon, 24 Jul 2023 01:13:16 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-98dfb3f9af6so717044366b.2 for ; Mon, 24 Jul 2023 01:13:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186395; x=1690791195; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uVktBm6sJYLsfwDSxkCEMzdAYO9ly2+TwdXhkfjytSk=; b=sGq3JK8o46jSpuHPepL1m9b3U5faB2dCmQuUcMqsm9ZY4m0Kx5d+MkS9CbuncxZBBn rGfVVPh8hI0m4aVPpAmW2Wbn8m23gJpTLuhy15OY3vjJ6KbQCQcvhrtJ6S1B3O8/Q+P5 U7YGLc97db1/5/vcvlEnZwP+D1wE/w2p6OB6WzjZDzW9n7WrXUCOm0uta40++euYzURw t63Io3sgEOMT3SvyYwcQyrs/x7r15XHfvTWJU9F0OIoNSAg+yY6DzfBacrXnNdmJ4zwq harQtGHM/ptRmIA2c2eAuWwqOUKoRP7Ss1+hrYIS5dPsTwCVif7mOqKsiUb62+cGsBMr TyWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186395; x=1690791195; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uVktBm6sJYLsfwDSxkCEMzdAYO9ly2+TwdXhkfjytSk=; b=NpqcoxJ3Rc/Y//yqZI1QodDf6in7KuyExhALSCYdnO4sniVcpjg1HwNXy6rMTjsL/w n4SyK9Z4uHU2zk8U4yPPiGTVz9PaUotgtvhUWEDuGWPQFhGu6Xfao5CevZyOq2Qt4k/P mMZCBDOKhIF02zPFTM2mx5gERjlHGayGrLm/+Fktn2qMS8iMy+KWkYwvRDyc+WEOXWII xKBm4l0wqIAiEXmDp5ki2eSWMTDUFYziCzabBE/PlGSDNLko0mBoGaeRZPc6QmsZV4Oz JSu4Jl6dZoT38fIlaz6H7yPi+0DiLvOeTlA9OYdovsDRWB/MdlO5SmP8/Et90aQY4UaB Y4CQ== X-Gm-Message-State: ABy/qLZCwgq5yWeC3MPt3z3dFW2EFPHPLr9mXc0ybj2itHaQ1bkvLfQy UaOBdWrmAjJhqRR92mDV3rw5hA== X-Google-Smtp-Source: APBJJlExAx+HV8ZAaCKyf2Qp7rDblH1XsgOcs5UU9eKDTe7YZDFVoX9leKmqYV0UXmOvE0Zl0WliSA== X-Received: by 2002:a17:907:2e0d:b0:969:93f2:259a with SMTP id ig13-20020a1709072e0d00b0096993f2259amr9076158ejc.73.1690186395027; Mon, 24 Jul 2023 01:13:15 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:12 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Takahiro Kuwano , Tudor Ambarus Subject: [RESEND PATCH v3 08/11] mtd: spi-nor: spansion: add support for S28HS02GT Date: Mon, 24 Jul 2023 11:12:44 +0300 Message-Id: <20230724081247.4779-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2496; i=tudor.ambarus@linaro.org; h=from:subject; bh=42jO3KEj6TPMriTkqWSNGWStki92z6JnENZKEl1DzBQ=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+3DJLbcgDJ/Bnw8XTtxSY3c8EYXmtEi73A UxghPLI3sKJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6W47CACKy1GhVpCclmoAAJYiRpqVPkMcBm58dTZrbpSQ5BzjyW3k/+/u9kNK8cbHzDLP2GFtUIe B+U/vNTce/C7jYROWAfo+DveIyQBzf/T26CrY097wYMKT6LihvmSvt/3PRYwsjfiIPGTXZupjgF bNF32zD1zZc8NVPhzqu1gxy6Lqi589iq/QWaE/CqJn3B8Wo9BeZR2FzusgZWsr+EwOLfNRH/00j riPSj2Cq2coFjjLjbaQhG7ncvxO+4cF9pClsBfFx6p1zgF8h5/Yl2wAT9RemB0IletkvaYy/tLu peI+CFd1c+a5LB2PrVL9YVNtmOcL7az/G8a3N0bikC85dz9j X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb, multi-chip package, Octal SPI Flash. Signed-off-by: Takahiro Kuwano Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 2fc3e65686b3..1f2b4a469719 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -695,22 +695,23 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *= nor, bool enable) =20 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. */ - if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D=3D 0) - nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D + if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D=3D 0) + params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =3D SPINOR_OP_CYPRESS_RD_FAST; =20 /* This flash is also missing the 4-byte Page Program opcode bit. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); /* * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR= ], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); =20 /* @@ -718,7 +719,11 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) * address bytes needed for Read Status Register command as 0 but the * actual value for that is 4. */ - nor->params->rdsr_addr_nbytes =3D 4; + params->rdsr_addr_nbytes =3D 4; + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; =20 return cypress_nor_get_page_size(nor); } @@ -918,6 +923,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, + { "s28hs02gt", INFO(0x345b1c, 0, 0, 0) + PARSE_SFDP + MFR_FLAGS(USE_CLPEF) + .fixups =3D &s28hx_t_fixups, + }, }; =20 /** --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA34BC001B0 for ; Mon, 24 Jul 2023 08:14:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbjGXIOP (ORCPT ); Mon, 24 Jul 2023 04:14:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231433AbjGXINn (ORCPT ); Mon, 24 Jul 2023 04:13:43 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 343E3E64 for ; Mon, 24 Jul 2023 01:13:19 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-98de21518fbso698600766b.0 for ; Mon, 24 Jul 2023 01:13:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186397; x=1690791197; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lvn9Ytvulvk1EXRz+zaqNbSkQ8OMJCRDUn6E/2+cB9o=; b=tV+QpqasoevnXMwEWXs3J6oR6XwrLiFCZZUpCf37Act6PRhdldtR3xB1mvxG3yUo36 6ZzWaOXPxHWUkQhRjvLfKg5bQxoj1cEI0DkS0WoTw6c9CeDVz+3JsULY2iP3pt031EDq VT5STqpGNF3ik586JBJNeD0psTuWWVaA94cLOPZ7u0KVIjAihueT8HMuZUGHE0ltAvP9 Mzo+ELsnPSM7Hztq8GFNJmbTj0qNb5nmAJEC4h2KqA/Fb29NaKLPKF8hImenn/BP5+Sv 5KIO/CmhXUiWeY4CCXGSuSdtLW3OzshDmtf8OxA2JIJiUNrKGQ6Dj0By0TxbmXxdMvil 8I4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186397; x=1690791197; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lvn9Ytvulvk1EXRz+zaqNbSkQ8OMJCRDUn6E/2+cB9o=; b=PqklwEdbIttYSSzHa77ola8bBUabn8TLfp6xOVMDi8IbC8vsedzVhI5CmPW5fth7Pw u1hJLG6lMayRGS9oiu+2/yz4eEMutRDfB+4wwBnrOzu5TCDYV3n1/g6G4y+OTRK+tAij XIb7BuUScS9OJ6oqWp01a5cxMiestXYU3qr13Xun16KjNwXuKWc1ZpAm6QZVc9q5S7Il 25lcjCVeGbEel8eulr6c6ty9JkoU9HQRi398f9sXClw3cCELghLv4zFWg5JDRknWskp3 KqAKQpxK/GWp8/pTlEBMO0ERvfjUxiP/ONYpRQ+pHXZghbNDllj+qo8DuqxQB0SHZTy4 occg== X-Gm-Message-State: ABy/qLZ2n3RzYYDrQq49gfPZ00zSX1VtUVOeORS6SMQuztWjlcSYhOhq j4dhyh8uO7hIQGXHG0tACj/xUg== X-Google-Smtp-Source: APBJJlEezsECpGZwPWX72NBkdrzZ1Q0LndDTGl9NGNm9L8lP1tvSxGyJHOB5WF+b5Q0Ee4CZazYP/g== X-Received: by 2002:a17:906:18c:b0:98d:e696:de4f with SMTP id 12-20020a170906018c00b0098de696de4fmr10641335ejb.26.1690186397359; Mon, 24 Jul 2023 01:13:17 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:16 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [RESEND PATCH v3 09/11] mtd: spi-nor: spansion: let SFDP determine the flash and sector size Date: Mon, 24 Jul 2023 11:12:45 +0300 Message-Id: <20230724081247.4779-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2622; i=tudor.ambarus@linaro.org; h=from:subject; bh=pCpO/9Mvf8zp3/Qd2t0AYPeMg7+RmKPsnX2goFSGCbY=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ+eWNAnfU88wBv7B1V3EOb+sqK02NWWJWNR Vt28fFlzHOJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfgAKCRBLVU9HpY0U 6VS0CACVIspLQT7Pfz+tb0BedC8TvEfvu5UqqCJxPkdVQQ1hs4TLyHj/+48cTmZgRS/qWXF2VDa NEpcR8hEZ4s6/a9allG6epnM+1zitmkB9O3DNZ+u1HvK5d1xGlYw5ahwQ+75Fd789+NVIchhexD Xtnvtft12qJ1r3Yx9DIg55fqI5WKDsbxuIEZHLIMnpr6kfW6tgdO0lN9iD6LJ1kqROVxahwy8bb MREsBmYkeOxGZSdXwHAXvaBhgsIdYMrWtXjfyREyFZWdGf/JxZOPP+B4aEDeft1sIMjyMzh+S9q 0i/McXURNzlBxhjhkict7cxCcYIM8Ci9hsLLNDR8wYC6vA7t X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" sector_size is used to determine the flash size and the erase size in case of uniform erase. n_sectors is used to determine the flash_size. But the flash size and the erase sizes are determined when parsing SFDP, let SFDP determine them. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 1f2b4a469719..413573cdb4fc 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -875,11 +875,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25fs256t_fixups }, - { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) + { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, - { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) + { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, @@ -888,11 +888,11 @@ static const struct flash_info spansion_nor_parts[] = =3D { MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups =3D &s25hx_t_fixups }, - { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) + { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, - { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) + { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s25hx_t_fixups }, @@ -903,22 +903,22 @@ static const struct flash_info spansion_nor_parts[] = =3D { .fixups =3D &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, - { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) + { "s28hl512t", INFO(0x345a1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) + { "s28hl01gt", INFO(0x345a1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) + { "s28hs512t", INFO(0x345b1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, }, - { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) + { "s28hs01gt", INFO(0x345b1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups =3D &s28hx_t_fixups, --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE94DC001B0 for ; Mon, 24 Jul 2023 08:14:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231523AbjGXIOv (ORCPT ); Mon, 24 Jul 2023 04:14:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231217AbjGXIOZ (ORCPT ); Mon, 24 Jul 2023 04:14:25 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFD1D10E3 for ; Mon, 24 Jul 2023 01:13:47 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-98df3dea907so641009766b.3 for ; Mon, 24 Jul 2023 01:13:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186402; x=1690791202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r1B2NCe5HAwiQi6+47CtZiZu+Vu5z0uOnlROiU8PNpA=; b=QY7rh/pAquoo378N4CyA6AZKj1v++zcN/3Ww5oKLwMS3+S8dU4IF0lj7RjaS2CAEGY Isr3wXYFsc2lc8QS2yD1D2FJqI7UWjW1EGh2Uz37QduASB1I2QFVv6nvGDEPHZDpgWEJ caiwYhTdWpH8yTEsQgO33RIiWs8ZZECP+CSrEhw5ml0u8wqwCmgxN5dYzbScDuQ6vFuI qE4OlLll9IbgR9gIMy/vEiJaDjST4+OBEn+2LyWHetaIgG0cWPg2ZGKZ4/pXN05UroPC Vu+QMggpzaQegiisHi/LhJUGDM4gu/zQ2SV73D6bgaIYcPi23lRNAbpIl4vJStFs6izi 7gTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186402; x=1690791202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r1B2NCe5HAwiQi6+47CtZiZu+Vu5z0uOnlROiU8PNpA=; b=Cw/nXzxE8LUhy7MTip8PrCTnfJJM1tymqFo3W5pVWYygu/ewY5T37MTF9QJuwW8xFt CoNyKc86r2B1Wjq69NxQLSO4O7JoKNvqahN8QlPpPhaSaUywVcjKRvm+e+s2eltHNuak gEXT8Lzti4kjt+zsbJYIgHJXnQSi8qATT0EjWcuZSL+VAb+gGnfZI/59kbnKwcySuPF9 SzwwFCnuGbpi+8acy/8ClDjSP11bQn3JQfg2ijpn8GQa7mr4l3daSU+qFTqwFZ302fQn HO9T8hec/oVkrT5AHkEezgTkgt0P0dsMqUna8kM4SBcQ1Gh3H9EHxtUfZuZgUKzKkt3s QD7g== X-Gm-Message-State: ABy/qLYammdRcyzixtlYJSKgE6Uup9bFOrWKP1RqbDXNpT9anAjIV/8F C25WZ2wbJHNznkUWDi06jS1yXA== X-Google-Smtp-Source: APBJJlEaKG5Dt3U+fEqgqoE/BxTER41uI27lLaRY7hkr8e7uknLgy0tvjNvR5pFAKRwACqZEycM3Xg== X-Received: by 2002:a17:906:5393:b0:99b:4956:e4df with SMTP id g19-20020a170906539300b0099b4956e4dfmr8859714ejo.11.1690186401974; Mon, 24 Jul 2023 01:13:21 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:19 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [RESEND PATCH v3 10/11] mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable() Date: Mon, 24 Jul 2023 11:12:46 +0300 Message-Id: <20230724081247.4779-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1722; i=tudor.ambarus@linaro.org; h=from:subject; bh=m09E4D2SbSB/QXfTnPlKEg92z13fHEFqiJ3l0puhOlE=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ/rJZTBzC/giI8SYKUWTg+y0y5OCBsOq+TO AFXiVivf7SJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfwAKCRBLVU9HpY0U 6Y8XCACdkKLonzkXNLmbOIc30Xy4RMFAPgZZN2E71+WJcm6QkDzPko/G6Itava2mbzFlxNn2mCS jaOK4RXgSkuGI7jLfPHBzGyfYf0GJEtpvIjobh+3jbFtKK2+YzzhDb8c4lfOW3nWl6kAQh9i8Ng OU+9x/jecpEDS4wOZH+4vYrgEfb0bVSFqr5OBf2crbsYi+CC4mJZijeym7Pxc0cUkiho3fCJzjh oZVjQU3rlbe7bczuwe6LJg7dOwjoq2/O6AGCT4y2jje/TM4zAB5gvlDXK5phT14S3iyuNANp1dX sSYnWD/CE8b6UJNyfnashTsrOal7yU/Xd9jkRcgwh54rnV75 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All s25hx_t flashes have single or multi chip flavors and already use n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t to always use vreg_offset for the quad_enable() method, so that we use the same code base for both single and multi chip package flashes. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 413573cdb4fc..4027f0038ce5 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -350,10 +350,6 @@ static int cypress_nor_quad_enable_volatile(struct spi= _nor *nor) u8 i; int ret; =20 - if (!params->n_dice) - return cypress_nor_quad_enable_volatile_reg(nor, - SPINOR_REG_CYPRESS_CFR1V); - for (i =3D 0; i < params->n_dice; i++) { addr =3D params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; ret =3D cypress_nor_quad_enable_volatile_reg(nor, addr); @@ -659,15 +655,17 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; - + params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 - /* Replace ready() with multi die version */ - if (params->n_dice) - params->ready =3D cypress_nor_sr_ready_and_clear; - return 0; } =20 --=20 2.34.1 From nobody Tue Sep 9 01:01:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1514C001DE for ; Mon, 24 Jul 2023 08:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231448AbjGXIO7 (ORCPT ); Mon, 24 Jul 2023 04:14:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231400AbjGXIOc (ORCPT ); Mon, 24 Jul 2023 04:14:32 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D9FD1AE for ; Mon, 24 Jul 2023 01:13:52 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-52229f084beso1574442a12.2 for ; Mon, 24 Jul 2023 01:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690186407; x=1690791207; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FjpE0CTKohDZ2ehuACLTkZqrmJb/Yntt3sN7R44vEtA=; b=xnK7gh0F2XnAfmAj7Ba1o3LJ6gE86oxlduR7gzGsnqUaQDPW0DjO6k+wKCrWJolfMV YFQAJTae5IuAHo31uL/QrUyJPzR6OaqHN3jLrkBGcTvak4Kycx7E4h3lonGmDuElS1Bx z6guQ4efnsjzSPgTIosyC8T9zqXD7npWb/xRPq7zTvO+NLrfKmq2Z1GJi7guVeckwhPi mVO+Baljx36aLdOu0AyqDDSwWJfJFwzueLK6sDRsoZ5Y7Fj9SodKIvqhlWWCxSq9ZE8i hqGc2wDUkDYkYYzc3og0mFBAI8QE+mL7HDMA/b0GulSzLa7k0Xivj+Yq0YhigcwxgUhl PP8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690186407; x=1690791207; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FjpE0CTKohDZ2ehuACLTkZqrmJb/Yntt3sN7R44vEtA=; b=H3uaMUS5VM6gnuP0P9SWJPaD+wK9ZhjQvL4wErSaKyLQO4LLgmSV1JTpVfXMDCp1iZ CYBzhrUekysp4U1nVFrPw5Cn+1AwUYX39ndTRWZwtdD0j4bzjmMfohK5g881L+iOOFEz QkyAeXMqukDHN+WQUXfHeB/VnGqvY1IdWrYEM2qJrRoVWOS4+k7jwUnLSPlNqy+IMWhY whI3s/bFpt/zLE0cIQzgjinAtBw6wOHZRgUxQrsDyF1ZROMNqvd5vxpUedx4FryyIIcC yqI+bVLyyaDgbQuQ1mXiLXkuHApyY8GbByF6lXWO9Vk7d45bNKbpwUCS8kvUa2dVDAkL wFmw== X-Gm-Message-State: ABy/qLZFK84+cdvCHOqEs/gluXwDCG0f321dcVMqG9AlMVwb7hvLMd8Y HeU9nFJKCbIZgkXcYjlEfN8snQ== X-Google-Smtp-Source: APBJJlGUL2q0PX1PyO+HWJGPTCESCX+Zx0heqGiwB2fUoec14FFM4neH/1+XpitqtN1NgIf8XO++Ng== X-Received: by 2002:a17:907:1de6:b0:982:79fa:4532 with SMTP id og38-20020a1709071de600b0098279fa4532mr9124481ejc.53.1690186407034; Mon, 24 Jul 2023 01:13:27 -0700 (PDT) Received: from 1.. ([79.115.63.48]) by smtp.gmail.com with ESMTPSA id a6-20020a1709065f8600b0098ec690e6d7sm6355395eju.73.2023.07.24.01.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 01:13:24 -0700 (PDT) From: Tudor Ambarus To: tkuw584924@gmail.com, takahiro.kuwano@infineon.com, michael@walle.cc Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [RESEND PATCH v3 11/11] mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offset Date: Mon, 24 Jul 2023 11:12:47 +0300 Message-Id: <20230724081247.4779-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724081247.4779-1-tudor.ambarus@linaro.org> References: <20230724081247.4779-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6780; i=tudor.ambarus@linaro.org; h=from:subject; bh=MUJq2mMJ7nIureH4NTnSp4c0il3VTp5/1NGTZmdRv8E=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBkvjJ/AjClsiJy+r+/oUJQL9lKwKRmy/640tCVi cFl1S4x6XeJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZL4yfwAKCRBLVU9HpY0U 6UyACACihYeFek6vZM2wuP6gooTVtrkuQT5Myp3MWn40rPLrLh3/dTfZyuhJl8GEDwfykX24Ecc aEj0LnTn1IGBg9q0diCEtiGkoOmcIcqdXNWpMlsC0VlifsOZ+JXS9Lc8bHVGEyTnfX8w58DaZTN yM1+opq/Tz/u3Fmn1FAM2f1UNX+9r7AgDqIRKitESVkmD/OYeoO92RbAoXJZ6WX0X5GnhzJfgFP vSk/GNok44dcUaj5RRrGXVKdvaLSiodma8LRekoOUC3gyhOyQzEq3o2QVE5Vo9NpeoLeY3bm8lb 8Kp9DGsZI+5fzj9+dleV+rAnqFJAJcN7GgpRuO/nrbCogAgr X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All users of cypress_nor_get_page_size() retrieve n_dice and vreg_offset from SFDP. Switch cypress_nor_get_page_size() to always use vreg_offset so that we use the same code base for both single and multi chip package flashes. cypress_nor_get_page_size() is now called in the post_sfdp() hook instead of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT and we now use them to get the page size in the post_sfdp hook. Consequently the null checks on n_dice and vreg_offset are moved to the post_sfdp() hook. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 105 +++++++++++++-------------------- 1 file changed, 42 insertions(+), 63 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 4027f0038ce5..0b01af33aa57 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -471,28 +471,17 @@ static int cypress_nor_set_addr_mode_nbytes(struct sp= i_nor *nor) return 0; } =20 -static int cypress_nor_get_page_size_single_chip(struct spi_nor *nor) -{ - struct spi_mem_op op =3D - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR3V, 0, - nor->bouncebuf); - int ret; - - ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) - nor->params->page_size =3D 512; - else - nor->params->page_size =3D 256; - - return 0; -} - - -static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) +/** + * cypress_nor_get_page_size() - Get flash page size configuration. + * @nor: pointer to a 'struct spi_nor' + * + * The BFPT table advertises a 512B or 256B page size depending on part bu= t the + * page size is actually configurable (with the default being 256B). Read = from + * CFR3V[4] and set the correct size. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_get_page_size(struct spi_nor *nor) { struct spi_mem_op op =3D CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, @@ -522,23 +511,6 @@ static int cypress_nor_get_page_size_mcp(struct spi_no= r *nor) return 0; } =20 -/** - * cypress_nor_get_page_size() - Get flash page size configuration. - * @nor: pointer to a 'struct spi_nor' - * - * The BFPT table advertises a 512B or 256B page size depending on part bu= t the - * page size is actually configurable (with the default being 256B). Read = from - * CFR3V[4] and set the correct size. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_get_page_size(struct spi_nor *nor) -{ - if (nor->params->n_dice) - return cypress_nor_get_page_size_mcp(nor); - return cypress_nor_get_page_size_single_chip(nor); -} - static void cypress_nor_ecc_init(struct spi_nor *nor) { /* @@ -575,20 +547,26 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, if (nor->bouncebuf[0]) return -ENODEV; =20 - return cypress_nor_get_page_size(nor); + return 0; } =20 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* PP_1_1_4_4B is supported but missing in 4BAIT. */ params->hwcaps.mask |=3D SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4); =20 - return 0; + return cypress_nor_get_page_size(nor); } =20 static int s25fs256t_late_init(struct spi_nor *nor) @@ -623,10 +601,20 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, =20 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) { - struct spi_nor_erase_type *erase_type =3D - nor->params->erase_map.erase_type; + struct spi_nor_flash_parameter *params =3D nor->params; + struct spi_nor_erase_type *erase_type =3D params->erase_map.erase_type; unsigned int i; =20 + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * In some parts, 3byte erase opcodes are advertised by 4BAIT. * Convert them to 4byte erase opcodes. @@ -644,10 +632,6 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) } } =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (nor->params->size =3D=3D SZ_256M) - nor->params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -655,12 +639,6 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =3D 8; params->ready =3D cypress_nor_sr_ready_and_clear; @@ -694,6 +672,17 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *n= or, bool enable) static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size =3D=3D SZ_256M) + params->n_dice =3D 2; + /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. @@ -719,10 +708,6 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) */ params->rdsr_addr_nbytes =3D 4; =20 - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (params->size =3D=3D SZ_256M) - params->n_dice =3D 2; - return cypress_nor_get_page_size(nor); } =20 @@ -737,12 +722,6 @@ static int s28hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be = retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - params->set_octal_dtr =3D cypress_nor_set_octal_dtr; params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); --=20 2.34.1