From nobody Tue Sep 9 07:27:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47999C001B0 for ; Mon, 24 Jul 2023 06:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230063AbjGXGwJ (ORCPT ); Mon, 24 Jul 2023 02:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231214AbjGXGwG (ORCPT ); Mon, 24 Jul 2023 02:52:06 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1EA7F4; Sun, 23 Jul 2023 23:52:04 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id B2EBB24E154; Mon, 24 Jul 2023 14:52:01 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 14:52:01 +0800 Received: from SD-Server.starfivetech.com (183.27.99.135) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 24 Jul 2023 14:52:00 +0800 From: Walker Chen To: Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Hal Feng CC: , , , Walker Chen Subject: [PATCH v1 2/2] riscv: dts: starfive: jh7110: add the node and pins configuration for tdm Date: Mon, 24 Jul 2023 14:51:58 +0800 Message-ID: <20230724065158.925-3-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230724065158.925-1-walker.chen@starfivetech.com> References: <20230724065158.925-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.99.135] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Reviewed-by: Hal Feng Signed-off-by: Walker Chen --- .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 5feff4673503..f49992097448 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -265,6 +265,40 @@ slew-rate =3D <0>; }; }; + + tdm_pins: tdm-0 { + tx-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <2>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pinmux =3D ; + input-enable; + }; + + sync-pins { + pinmux =3D ; + input-enable; + }; + + pcmclk-pins { + pinmux =3D ; + input-enable; + }; + }; }; =20 &uart0 { @@ -273,6 +307,12 @@ status =3D "okay"; }; =20 +&tdm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tdm_pins>; + status =3D "okay"; +}; + &U74_1 { cpu-supply =3D <&vdd_cpu>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 411a1bd4ddc9..d3973f5e315c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -446,6 +446,27 @@ status =3D "disabled"; }; =20 + tdm: tdm@10090000 { + compatible =3D "starfive,jh7110-tdm"; + reg =3D <0x0 0x10090000 0x0 0x1000>; + clocks =3D <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names =3D "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets =3D <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas =3D <&dma 20>, <&dma 21>; + dma-names =3D "rx","tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + stgcrg: clock-controller@10230000 { compatible =3D "starfive,jh7110-stgcrg"; reg =3D <0x0 0x10230000 0x0 0x10000>; --=20 2.17.1